src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_format.h"
  43 #include "fd3_zsa.h"
  44
  45 static inline uint32_t
  46 add_sat(uint32_t a, int32_t b)
  47 {
  48         int64_t ret = (uint64_t)a + (int64_t)b;
  49         if (ret > ~0U)
  50                 return ~0U;
  51         if (ret < 0)
  52                 return 0;
  53         return (uint32_t)ret;
  54 }
  55
  56 static void
  57 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  58                 struct fd3_emit *emit)
  59 {
  60         const struct pipe_draw_info *info = emit->info;
  61         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  62
  63         fd3_emit_state(ctx, ring, emit);
  64
  65         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  66                 fd3_emit_vertex_bufs(ring, emit);
  67
  68         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  69         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  70
  71         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  72         OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
  73         OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
  74         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  75         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  76
  77         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  78         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  79                         info->restart_index : 0xffffffff);
  80
  81         /* points + psize -> spritelist: */
  82         if (ctx->rasterizer->point_size_per_vertex &&
  83                         fd3_emit_get_vp(emit)->writes_psize &&
  84                         (info->mode == PIPE_PRIM_POINTS))
  85                 primtype = DI_PT_POINTLIST_PSIZE;
  86
  87         fd_draw_emit(ctx->batch, ring, primtype,
  88                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  89                         info);
  90 }
  91
  92 /* fixup dirty shader state in case some "unrelated" (from the state-
  93  * tracker's perspective) state change causes us to switch to a
  94  * different variant.
  95  */
  96 static void
  97 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  98 {
  99         struct fd3_context *fd3_ctx = fd3_context(ctx);
 100         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
 101
 102         if (!ir3_shader_key_equal(last_key, key)) {
 103                 if (last_key->has_per_samp || key->has_per_samp) {
 104                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
 105                                         (last_key->vsaturate_t != key->vsaturate_t) ||
 106                                         (last_key->vsaturate_r != key->vsaturate_r))
 107                                 ctx->dirty |= FD_SHADER_DIRTY_VP;
 108
 109                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 110                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 111                                         (last_key->fsaturate_r != key->fsaturate_r))
 112                                 ctx->dirty |= FD_SHADER_DIRTY_FP;
 113                 }
 114
 115                 if (last_key->vclamp_color != key->vclamp_color)
 116                         ctx->dirty |= FD_SHADER_DIRTY_VP;
 117
 118                 if (last_key->fclamp_color != key->fclamp_color)
 119                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 120
 121                 if (last_key->color_two_side != key->color_two_side)
 122                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 123
 124                 if (last_key->half_precision != key->half_precision)
 125                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 126
 127                 fd3_ctx->last_key = *key;
 128         }
 129 }
 130
 131 static bool
 132 fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 133 {
 134         struct fd3_context *fd3_ctx = fd3_context(ctx);
 135         struct fd3_emit emit = {
 136                 .debug = &ctx->debug,
 137                 .vtx  = &ctx->vtx,
 138                 .prog = &ctx->prog,
 139                 .info = info,
 140                 .key = {
 141                         .color_two_side = ctx->rasterizer->light_twoside,
 142                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 143                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 144                         // TODO set .half_precision based on render target format,
 145                         // ie. float16 and smaller use half, float32 use full..
 146                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 147                         .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate),
 148                         .vsaturate_s = fd3_ctx->vsaturate_s,
 149                         .vsaturate_t = fd3_ctx->vsaturate_t,
 150                         .vsaturate_r = fd3_ctx->vsaturate_r,
 151                         .fsaturate_s = fd3_ctx->fsaturate_s,
 152                         .fsaturate_t = fd3_ctx->fsaturate_t,
 153                         .fsaturate_r = fd3_ctx->fsaturate_r,
 154                 },
 155                 .rasterflat = ctx->rasterizer->flatshade,
 156                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 157                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 158         };
 159
 160         fixup_shader_state(ctx, &emit.key);
 161
 162         unsigned dirty = ctx->dirty;
 163
 164         /* do regular pass first, since that is more likely to fail compiling: */
 165
 166         if (!(fd3_emit_get_vp(&emit) && fd3_emit_get_fp(&emit)))
 167                 return false;
 168
 169         emit.key.binning_pass = false;
 170         emit.dirty = dirty;
 171         draw_impl(ctx, ctx->batch->draw, &emit);
 172
 173         /* and now binning pass: */
 174         emit.key.binning_pass = true;
 175         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 176         emit.vp = NULL;   /* we changed key so need to refetch vp */
 177         emit.fp = NULL;
 178         draw_impl(ctx, ctx->batch->binning, &emit);
 179
 180         return true;
 181 }
 182
 183 /* clear operations ignore viewport state, so we need to reset it
 184  * based on framebuffer state:
 185  */
 186 static void
 187 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 188 {
 189         float half_width = pfb->width * 0.5f;
 190         float half_height = pfb->height * 0.5f;
 191
 192         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 193         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 194         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 195         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 196         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 197 }
 198
 199 /* binning pass cmds for a clear:
 200  * NOTE: newer blob drivers don't use binning for clear, which is probably
 201  * preferable since it is low vtx count.  However that doesn't seem to
 202  * actually work for me.  Not sure if it is depending on support for
 203  * clear pass (rather than using solid-fill shader), or something else
 204  * that newer blob is doing differently.  Once that is figured out, we
 205  * can remove fd3_clear_binning().
 206  */
 207 static void
 208 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 209 {
 210         struct fd_ringbuffer *ring = ctx->batch->binning;
 211         struct fd3_emit emit = {
 212                 .debug = &ctx->debug,
 213                 .vtx  = &ctx->solid_vbuf_state,
 214                 .prog = &ctx->solid_prog,
 215                 .key = {
 216                         .binning_pass = true,
 217                         .half_precision = true,
 218                 },
 219                 .dirty = dirty,
 220         };
 221
 222         fd3_emit_state(ctx, ring, &emit);
 223         fd3_emit_vertex_bufs(ring, &emit);
 224         reset_viewport(ring, &ctx->batch->framebuffer);
 225
 226         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 227         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 228                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 229                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 230                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 231         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 232         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 233         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 234         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 235         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 236         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 237         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 238
 239         fd_event_write(ctx->batch, ring, PERFCOUNTER_STOP);
 240
 241         fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 242                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 243 }
 244
 245 static void
 246 fd3_clear(struct fd_context *ctx, unsigned buffers,
 247                 const union pipe_color_union *color, double depth, unsigned stencil)
 248 {
 249         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 250         struct fd_ringbuffer *ring = ctx->batch->draw;
 251         unsigned dirty = ctx->dirty;
 252         unsigned i;
 253         struct fd3_emit emit = {
 254                 .debug = &ctx->debug,
 255                 .vtx  = &ctx->solid_vbuf_state,
 256                 .prog = &ctx->solid_prog,
 257                 .key = {
 258                         .half_precision = fd_half_precision(pfb),
 259                 },
 260         };
 261
 262         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 263         dirty |= FD_DIRTY_PROG;
 264         emit.dirty = dirty;
 265
 266         fd3_clear_binning(ctx, dirty);
 267
 268         /* emit generic state now: */
 269         fd3_emit_state(ctx, ring, &emit);
 270         reset_viewport(ring, &ctx->batch->framebuffer);
 271
 272         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 273         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 274                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 275
 276         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 277         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 278                         &ctx->batch->rbrc_patches);
 279
 280         if (buffers & PIPE_CLEAR_DEPTH) {
 281                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 282                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 283                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 284                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 285
 286                 fd_wfi(ctx->batch, ring);
 287                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 288                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 289                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 290                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 291         } else {
 292                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 293                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 294         }
 295
 296         if (buffers & PIPE_CLEAR_STENCIL) {
 297                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 298                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 299                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 300                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 301                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 302                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 303                                 0xff000000 | // XXX ???
 304                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 305
 306                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 307                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 308                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 309                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 310                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 311                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 312                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 313                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 314                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 315                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 316         } else {
 317                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 318                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 319                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 320                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 321                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 322                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 323                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 324
 325                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 326                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 327                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 328                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 329                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 330                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 331                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 332                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 333                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 334         }
 335
 336         for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
 337                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 338                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 339                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 340                                 COND(buffers & (PIPE_CLEAR_COLOR0 << i),
 341                                          A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
 342
 343                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 344                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 345                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 346                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 347                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 348                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 349                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 350         }
 351
 352         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 353         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 354
 355         fd3_emit_vertex_bufs(ring, &emit);
 356
 357         fd3_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 358
 359         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 360         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 361                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 362                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 363                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 364         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 365         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 366         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 367         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 368         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 369         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 370         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 371
 372         fd_event_write(ctx->batch, ring, PERFCOUNTER_STOP);
 373
 374         fd_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 375                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 376 }
 377
 378 void
 379 fd3_draw_init(struct pipe_context *pctx)
 380 {
 381         struct fd_context *ctx = fd_context(pctx);
 382         ctx->draw_vbo = fd3_draw_vbo;
 383         ctx->clear = fd3_clear;
 384 }