src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_format.h"
  43 #include "fd3_zsa.h"
  44
  45 static inline uint32_t
  46 add_sat(uint32_t a, int32_t b)
  47 {
  48         int64_t ret = (uint64_t)a + (int64_t)b;
  49         if (ret > ~0U)
  50                 return ~0U;
  51         if (ret < 0)
  52                 return 0;
  53         return (uint32_t)ret;
  54 }
  55
  56 static void
  57 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  58                 struct fd3_emit *emit)
  59 {
  60         const struct pipe_draw_info *info = emit->info;
  61         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  62
  63         fd3_emit_state(ctx, ring, emit);
  64
  65         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  66                 fd3_emit_vertex_bufs(ring, emit);
  67
  68         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  69         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  70
  71         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  72         OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
  73         OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
  74         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  75         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  76
  77         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  78         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  79                         info->restart_index : 0xffffffff);
  80
  81         if (ctx->rasterizer && ctx->rasterizer->point_size_per_vertex &&
  82                 info->mode == PIPE_PRIM_POINTS)
  83                 primtype = DI_PT_POINTLIST_A2XX;
  84
  85         fd_draw_emit(ctx, ring,
  86                         primtype,
  87                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  88                         info);
  89 }
  90
  91 /* fixup dirty shader state in case some "unrelated" (from the state-
  92  * tracker's perspective) state change causes us to switch to a
  93  * different variant.
  94  */
  95 static void
  96 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  97 {
  98         struct fd3_context *fd3_ctx = fd3_context(ctx);
  99         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
 100
 101         if (!ir3_shader_key_equal(last_key, key)) {
 102                 ctx->dirty |= FD_DIRTY_PROG;
 103
 104                 if (last_key->has_per_samp || key->has_per_samp) {
 105                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
 106                                         (last_key->vsaturate_t != key->vsaturate_t) ||
 107                                         (last_key->vsaturate_r != key->vsaturate_r) ||
 108                                         (last_key->vinteger_s != key->vinteger_s))
 109                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
 110
 111                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 112                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 113                                         (last_key->fsaturate_r != key->fsaturate_r) ||
 114                                         (last_key->finteger_s != key->finteger_s))
 115                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 116                 }
 117
 118                 if (last_key->color_two_side != key->color_two_side)
 119                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 120
 121                 if (last_key->half_precision != key->half_precision)
 122                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 123
 124                 fd3_ctx->last_key = *key;
 125         }
 126 }
 127
 128 static void
 129 fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 130 {
 131         struct fd3_context *fd3_ctx = fd3_context(ctx);
 132         struct fd3_emit emit = {
 133                 .vtx  = &ctx->vtx,
 134                 .prog = &ctx->prog,
 135                 .info = info,
 136                 .key = {
 137                         /* do binning pass first: */
 138                         .binning_pass = true,
 139                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 140                         // TODO set .half_precision based on render target format,
 141                         // ie. float16 and smaller use half, float32 use full..
 142                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 143                         .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate ||
 144                                                          fd3_ctx->vinteger_s || fd3_ctx->finteger_s),
 145                         .vsaturate_s = fd3_ctx->vsaturate_s,
 146                         .vsaturate_t = fd3_ctx->vsaturate_t,
 147                         .vsaturate_r = fd3_ctx->vsaturate_r,
 148                         .fsaturate_s = fd3_ctx->fsaturate_s,
 149                         .fsaturate_t = fd3_ctx->fsaturate_t,
 150                         .fsaturate_r = fd3_ctx->fsaturate_r,
 151                         .vinteger_s = fd3_ctx->vinteger_s,
 152                         .finteger_s = fd3_ctx->finteger_s,
 153                 },
 154                 .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 155                 .sprite_coord_enable = ctx->rasterizer ? ctx->rasterizer->sprite_coord_enable : 0,
 156         };
 157         unsigned dirty;
 158
 159         fixup_shader_state(ctx, &emit.key);
 160
 161         dirty = ctx->dirty;
 162         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 163         draw_impl(ctx, ctx->binning_ring, &emit);
 164
 165         /* and now regular (non-binning) pass: */
 166         emit.key.binning_pass = false;
 167         emit.dirty = dirty;
 168         emit.vp = NULL;   /* we changed key so need to refetch vp */
 169         draw_impl(ctx, ctx->ring, &emit);
 170 }
 171
 172 /* clear operations ignore viewport state, so we need to reset it
 173  * based on framebuffer state:
 174  */
 175 static void
 176 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 177 {
 178         float half_width = pfb->width * 0.5f;
 179         float half_height = pfb->height * 0.5f;
 180
 181         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 182         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 183         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 184         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 185         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 186 }
 187
 188 /* binning pass cmds for a clear:
 189  * NOTE: newer blob drivers don't use binning for clear, which is probably
 190  * preferable since it is low vtx count.  However that doesn't seem to
 191  * actually work for me.  Not sure if it is depending on support for
 192  * clear pass (rather than using solid-fill shader), or something else
 193  * that newer blob is doing differently.  Once that is figured out, we
 194  * can remove fd3_clear_binning().
 195  */
 196 static void
 197 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 198 {
 199         struct fd3_context *fd3_ctx = fd3_context(ctx);
 200         struct fd_ringbuffer *ring = ctx->binning_ring;
 201         struct fd3_emit emit = {
 202                 .vtx  = &fd3_ctx->solid_vbuf_state,
 203                 .prog = &ctx->solid_prog,
 204                 .key = {
 205                         .binning_pass = true,
 206                         .half_precision = true,
 207                 },
 208                 .dirty = dirty,
 209         };
 210
 211         fd3_emit_state(ctx, ring, &emit);
 212         fd3_emit_vertex_bufs(ring, &emit);
 213         reset_viewport(ring, &ctx->framebuffer);
 214
 215         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 216         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 217                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 218                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 219                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 220         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 221         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 222         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 223         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 224         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 225         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 226         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 227
 228         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 229
 230         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 231                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 232 }
 233
 234 static void
 235 fd3_clear(struct fd_context *ctx, unsigned buffers,
 236                 const union pipe_color_union *color, double depth, unsigned stencil)
 237 {
 238         struct fd3_context *fd3_ctx = fd3_context(ctx);
 239         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 240         struct fd_ringbuffer *ring = ctx->ring;
 241         unsigned dirty = ctx->dirty;
 242         unsigned i;
 243         struct fd3_emit emit = {
 244                 .vtx  = &fd3_ctx->solid_vbuf_state,
 245                 .prog = &ctx->solid_prog,
 246                 .key = {
 247                         .half_precision = (fd3_half_precision(pfb->cbufs[0]) &&
 248                                                            fd3_half_precision(pfb->cbufs[1]) &&
 249                                                            fd3_half_precision(pfb->cbufs[2]) &&
 250                                                            fd3_half_precision(pfb->cbufs[3])),
 251                 },
 252         };
 253
 254         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 255         dirty |= FD_DIRTY_PROG;
 256         emit.dirty = dirty;
 257
 258         fd3_clear_binning(ctx, dirty);
 259
 260         /* emit generic state now: */
 261         fd3_emit_state(ctx, ring, &emit);
 262         reset_viewport(ring, &ctx->framebuffer);
 263
 264         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 265         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 266                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 267
 268         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 269         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 270                         &fd3_ctx->rbrc_patches);
 271
 272         if (buffers & PIPE_CLEAR_DEPTH) {
 273                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 274                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 275                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 276                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 277
 278                 fd_wfi(ctx, ring);
 279                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 280                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 281                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 282                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 283         } else {
 284                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 285                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 286         }
 287
 288         if (buffers & PIPE_CLEAR_STENCIL) {
 289                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 290                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 291                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 292                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 293                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 294                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 295                                 0xff000000 | // XXX ???
 296                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 297
 298                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 299                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 300                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 301                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 302                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 303                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 304                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 305                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 306                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 307                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 308         } else {
 309                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 310                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 311                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 312                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 313                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 314                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 315                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 316
 317                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 318                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 319                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 320                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 321                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 322                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 323                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 324                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 325                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 326         }
 327
 328         for (i = 0; i < 4; i++) {
 329                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 330                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 331                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 332                                 COND(buffers & (PIPE_CLEAR_COLOR0 << i),
 333                                          A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
 334
 335                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 336                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 337                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 338                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 339                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 340                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 341                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 342         }
 343
 344         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 345         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 346
 347         fd3_emit_vertex_bufs(ring, &emit);
 348
 349         fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 350
 351         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 352         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 353                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 354                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 355                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 356         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 357         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 358         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 359         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 360         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 361         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 362         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 363
 364         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 365
 366         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 367                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 368 }
 369
 370 void
 371 fd3_draw_init(struct pipe_context *pctx)
 372 {
 373         struct fd_context *ctx = fd_context(pctx);
 374         ctx->draw_vbo = fd3_draw_vbo;
 375         ctx->clear = fd3_clear;
 376 }