1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
33 #include "util/u_format.h"
35 #include "freedreno_state.h"
36 #include "freedreno_resource.h"
39 #include "fd3_context.h"
41 #include "fd3_program.h"
42 #include "fd3_format.h"
47 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
48 struct fd3_emit
*emit
)
50 const struct pipe_draw_info
*info
= emit
->info
;
52 fd3_emit_state(ctx
, ring
, emit
);
54 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
55 fd3_emit_vertex_bufs(ring
, emit
);
57 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
58 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
60 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
61 OUT_RING(ring
, info
->min_index
); /* VFD_INDEX_MIN */
62 OUT_RING(ring
, info
->max_index
); /* VFD_INDEX_MAX */
63 OUT_RING(ring
, info
->start_instance
); /* VFD_INSTANCEID_OFFSET */
64 OUT_RING(ring
, info
->start
); /* VFD_INDEX_OFFSET */
66 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
67 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
68 info
->restart_index
: 0xffffffff);
70 fd_draw_emit(ctx
, ring
,
71 emit
->key
.binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
75 /* fixup dirty shader state in case some "unrelated" (from the state-
76 * tracker's perspective) state change causes us to switch to a
80 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
82 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
83 struct ir3_shader_key
*last_key
= &fd3_ctx
->last_key
;
85 if (!ir3_shader_key_equal(last_key
, key
)) {
86 ctx
->dirty
|= FD_DIRTY_PROG
;
88 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
89 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
90 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
91 (last_key
->vsaturate_r
!= key
->vsaturate_r
))
92 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_VP
;
94 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
95 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
96 (last_key
->fsaturate_r
!= key
->fsaturate_r
))
97 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
100 if (last_key
->color_two_side
!= key
->color_two_side
)
101 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
103 if (last_key
->half_precision
!= key
->half_precision
)
104 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
106 if (last_key
->alpha
!= key
->alpha
)
107 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
109 fd3_ctx
->last_key
= *key
;
114 fd3_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
116 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
117 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
118 struct fd3_emit emit
= {
123 /* do binning pass first: */
124 .binning_pass
= true,
125 .color_two_side
= ctx
->rasterizer
? ctx
->rasterizer
->light_twoside
: false,
126 .alpha
= util_format_is_alpha(pipe_surface_format(pfb
->cbufs
[0])),
127 // TODO set .half_precision based on render target format,
128 // ie. float16 and smaller use half, float32 use full..
129 .half_precision
= !!(fd_mesa_debug
& FD_DBG_FRAGHALF
),
130 .has_per_samp
= fd3_ctx
->fsaturate
|| fd3_ctx
->vsaturate
,
131 .vsaturate_s
= fd3_ctx
->vsaturate_s
,
132 .vsaturate_t
= fd3_ctx
->vsaturate_t
,
133 .vsaturate_r
= fd3_ctx
->vsaturate_r
,
134 .fsaturate_s
= fd3_ctx
->fsaturate_s
,
135 .fsaturate_t
= fd3_ctx
->fsaturate_t
,
136 .fsaturate_r
= fd3_ctx
->fsaturate_r
,
138 .format
= pipe_surface_format(pfb
->cbufs
[0]),
139 .rasterflat
= ctx
->rasterizer
&& ctx
->rasterizer
->flatshade
,
143 fixup_shader_state(ctx
, &emit
.key
);
146 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
147 draw_impl(ctx
, ctx
->binning_ring
, &emit
);
149 /* and now regular (non-binning) pass: */
150 emit
.key
.binning_pass
= false;
152 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
153 draw_impl(ctx
, ctx
->ring
, &emit
);
156 /* clear operations ignore viewport state, so we need to reset it
157 * based on framebuffer state:
160 reset_viewport(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
)
162 float half_width
= pfb
->width
* 0.5f
;
163 float half_height
= pfb
->height
* 0.5f
;
165 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 4);
166 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(half_width
- 0.5));
167 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(half_width
));
168 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(half_height
- 0.5));
169 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-half_height
));
172 /* binning pass cmds for a clear:
173 * NOTE: newer blob drivers don't use binning for clear, which is probably
174 * preferable since it is low vtx count. However that doesn't seem to
175 * actually work for me. Not sure if it is depending on support for
176 * clear pass (rather than using solid-fill shader), or something else
177 * that newer blob is doing differently. Once that is figured out, we
178 * can remove fd3_clear_binning().
181 fd3_clear_binning(struct fd_context
*ctx
, unsigned dirty
)
183 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
184 struct fd_ringbuffer
*ring
= ctx
->binning_ring
;
185 struct fd3_emit emit
= {
186 .vtx
= &fd3_ctx
->solid_vbuf_state
,
187 .prog
= &ctx
->solid_prog
,
189 .binning_pass
= true,
190 .half_precision
= true,
195 fd3_emit_state(ctx
, ring
, &emit
);
196 fd3_emit_vertex_bufs(ring
, &emit
);
197 reset_viewport(ring
, &ctx
->framebuffer
);
199 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
200 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
201 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
202 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
203 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
204 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
205 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
206 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
207 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
208 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
209 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
210 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
212 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
214 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
215 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
219 fd3_clear(struct fd_context
*ctx
, unsigned buffers
,
220 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
222 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
223 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
224 enum pipe_format format
= pipe_surface_format(pfb
->cbufs
[0]);
225 struct fd_ringbuffer
*ring
= ctx
->ring
;
226 unsigned dirty
= ctx
->dirty
;
228 struct fd3_emit emit
= {
229 .vtx
= &fd3_ctx
->solid_vbuf_state
,
230 .prog
= &ctx
->solid_prog
,
232 .half_precision
= fd3_half_precision(format
),
237 dirty
&= FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
;
238 dirty
|= FD_DIRTY_PROG
;
241 fd3_clear_binning(ctx
, dirty
);
243 /* emit generic state now: */
244 fd3_emit_state(ctx
, ring
, &emit
);
245 reset_viewport(ring
, &ctx
->framebuffer
);
247 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_ALPHA
, 1);
248 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
249 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
251 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
252 OUT_RINGP(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
),
253 &fd3_ctx
->rbrc_patches
);
255 if (buffers
& PIPE_CLEAR_DEPTH
) {
256 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
257 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
258 A3XX_RB_DEPTH_CONTROL_Z_ENABLE
|
259 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
));
262 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_ZOFFSET
, 2);
263 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
264 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(depth
));
265 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
267 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
268 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
271 if (buffers
& PIPE_CLEAR_STENCIL
) {
272 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
273 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(stencil
) |
274 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil
) |
275 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
276 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
277 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
278 0xff000000 | // XXX ???
279 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
281 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
282 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
283 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
284 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
285 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE
) |
286 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
287 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
288 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
289 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
290 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
292 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
293 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
294 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
295 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
296 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
297 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
298 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
300 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
301 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
302 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
303 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
304 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
305 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
306 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
307 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
308 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
311 if (buffers
& PIPE_CLEAR_COLOR
) {
317 for (i
= 0; i
< 4; i
++) {
318 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
319 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
320 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS
) |
321 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce
));
323 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
324 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
325 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
326 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
327 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
328 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
329 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
332 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
333 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
335 fd3_emit_vertex_bufs(ring
, &emit
);
337 fd3_emit_constant(ring
, SB_FRAG_SHADER
, 0, 0, 4, color
->ui
, NULL
);
339 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
340 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
341 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
342 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
343 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
344 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
345 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
346 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
347 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
348 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
349 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
350 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
352 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
354 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, USE_VISIBILITY
,
355 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
359 fd3_draw_init(struct pipe_context
*pctx
)
361 struct fd_context
*ctx
= fd_context(pctx
);
362 ctx
->draw_vbo
= fd3_draw_vbo
;
363 ctx
->clear
= fd3_clear
;