src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd3_draw.h"
  38 #include "fd3_context.h"
  39 #include "fd3_emit.h"
  40 #include "fd3_program.h"
  41 #include "fd3_util.h"
  42 #include "fd3_zsa.h"
  43
  44
  45 static void
  46 emit_vertexbufs(struct fd_context *ctx, struct fd_ringbuffer *ring)
  47 {
  48         struct fd_vertex_stateobj *vtx = ctx->vtx;
  49         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vertexbuf;
  50         struct fd3_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  51         unsigned i;
  52
  53         if (!vtx->num_elements)
  54                 return;
  55
  56         for (i = 0; i < vtx->num_elements; i++) {
  57                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  58                 struct pipe_vertex_buffer *vb =
  59                                 &vertexbuf->vb[elem->vertex_buffer_index];
  60                 bufs[i].offset = vb->buffer_offset + elem->src_offset;
  61                 bufs[i].stride = vb->stride;
  62                 bufs[i].prsc   = vb->buffer;
  63                 bufs[i].format = elem->src_format;
  64         }
  65
  66         fd3_emit_vertex_bufs(ring, &ctx->prog, bufs, vtx->num_elements);
  67 }
  68
  69 static void
  70 draw_impl(struct fd_context *ctx, const struct pipe_draw_info *info,
  71                 struct fd_ringbuffer *ring, unsigned dirty, bool binning)
  72 {
  73         fd3_emit_state(ctx, ring, &ctx->prog, dirty, binning);
  74
  75         if (dirty & FD_DIRTY_VTXBUF)
  76                 emit_vertexbufs(ctx, ring);
  77
  78         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  79         OUT_RING(ring, 0x0000000b);                  /* PC_VERTEX_REUSE_BLOCK_CNTL */
  80
  81         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  82         OUT_RING(ring, info->min_index);        /* VFD_INDEX_MIN */
  83         OUT_RING(ring, info->max_index);        /* VFD_INDEX_MAX */
  84         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  85         OUT_RING(ring, info->start);            /* VFD_INDEX_OFFSET */
  86
  87         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  88         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  89                         info->restart_index : 0xffffffff);
  90
  91         fd_draw_emit(ctx, ring, binning ? IGNORE_VISIBILITY : USE_VISIBILITY, info);
  92 }
  93
  94 static void
  95 fd3_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
  96 {
  97         unsigned dirty = ctx->dirty;
  98         draw_impl(ctx, info, ctx->binning_ring,
  99                         dirty & ~(FD_DIRTY_BLEND), true);
 100         draw_impl(ctx, info, ctx->ring, dirty, false);
 101 }
 102
 103 /* binning pass cmds for a clear:
 104  * NOTE: newer blob drivers don't use binning for clear, which is probably
 105  * preferable since it is low vtx count.  However that doesn't seem to
 106  * actually work for me.  Not sure if it is depending on support for
 107  * clear pass (rather than using solid-fill shader), or something else
 108  * that newer blob is doing differently.  Once that is figured out, we
 109  * can remove fd3_clear_binning().
 110  */
 111 static void
 112 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 113 {
 114         struct fd3_context *fd3_ctx = fd3_context(ctx);
 115         struct fd_ringbuffer *ring = ctx->binning_ring;
 116
 117         fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, true);
 118
 119         fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
 120                         { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
 121                 }, 1);
 122
 123         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 124         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 125                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 126                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 127                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 128         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 129         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 130         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 131         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 132         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 133         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 134         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 135
 136         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 137         OUT_RING(ring, PERFCOUNTER_STOP);
 138
 139         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 140                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 141 }
 142
 143 static void
 144 fd3_clear(struct fd_context *ctx, unsigned buffers,
 145                 const union pipe_color_union *color, double depth, unsigned stencil)
 146 {
 147         struct fd3_context *fd3_ctx = fd3_context(ctx);
 148         struct fd_ringbuffer *ring = ctx->ring;
 149         unsigned dirty = ctx->dirty;
 150         unsigned ce, i;
 151
 152         dirty &= FD_DIRTY_VIEWPORT | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 153         dirty |= FD_DIRTY_PROG;
 154
 155         fd3_clear_binning(ctx, dirty);
 156
 157         /* emit generic state now: */
 158         fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, false);
 159
 160         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 161         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 162                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 163
 164         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 165         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 166                         &fd3_ctx->rbrc_patches);
 167
 168         if (buffers & PIPE_CLEAR_DEPTH) {
 169                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 170                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 171                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 172                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 173
 174                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 175                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 176                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 177                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 178         } else {
 179                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 180                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 181         }
 182
 183         if (buffers & PIPE_CLEAR_STENCIL) {
 184                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 185                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 186                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 187                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 188                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 189                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 190                                 0xff000000 | // XXX ???
 191                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 192
 193                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 194                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 195                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 196                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 197                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 198                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 199                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 200                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 201                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 202                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 203         } else {
 204                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 205                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 206                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 207                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 208                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 209                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 210                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 211
 212                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 213                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 214                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 215                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 216                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 217                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 218                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 219                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 220                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 221         }
 222
 223         if (buffers & PIPE_CLEAR_COLOR) {
 224                 ce = 0xf;
 225         } else {
 226                 ce = 0x0;
 227         }
 228
 229         for (i = 0; i < 4; i++) {
 230                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 231                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(12) |
 232                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 233                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 234
 235                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 236                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 237                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 238                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 239                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 240                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 241                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
 242                                 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
 243         }
 244
 245         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 246         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 247
 248         fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
 249                         { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
 250                 }, 1);
 251
 252         fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 253
 254         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 255         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 256                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 257                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 258                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 259         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 260         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 261         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 262         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 263         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 264         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 265         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 266
 267         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 268         OUT_RING(ring, PERFCOUNTER_STOP);
 269
 270         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 271                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 272 }
 273
 274 void
 275 fd3_draw_init(struct pipe_context *pctx)
 276 {
 277         struct fd_context *ctx = fd_context(pctx);
 278         ctx->draw = fd3_draw;
 279         ctx->clear = fd3_clear;
 280 }