src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_format.h"
  43 #include "fd3_zsa.h"
  44
  45 static inline uint32_t
  46 add_sat(uint32_t a, int32_t b)
  47 {
  48         int64_t ret = (uint64_t)a + (int64_t)b;
  49         if (ret > ~0U)
  50                 return ~0U;
  51         if (ret < 0)
  52                 return 0;
  53         return (uint32_t)ret;
  54 }
  55
  56 static void
  57 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  58                 struct fd3_emit *emit)
  59 {
  60         const struct pipe_draw_info *info = emit->info;
  61         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  62
  63         if (!(fd3_emit_get_vp(emit) && fd3_emit_get_fp(emit)))
  64                 return;
  65
  66         fd3_emit_state(ctx, ring, emit);
  67
  68         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  69                 fd3_emit_vertex_bufs(ring, emit);
  70
  71         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  72         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  73
  74         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  75         OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
  76         OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
  77         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  78         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  79
  80         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  81         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  82                         info->restart_index : 0xffffffff);
  83
  84         if (ctx->rasterizer->point_size_per_vertex &&
  85                         (info->mode == PIPE_PRIM_POINTS))
  86                 primtype = DI_PT_POINTLIST_PSIZE;
  87
  88         fd_draw_emit(ctx, ring,
  89                         primtype,
  90                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  91                         info);
  92 }
  93
  94 /* fixup dirty shader state in case some "unrelated" (from the state-
  95  * tracker's perspective) state change causes us to switch to a
  96  * different variant.
  97  */
  98 static void
  99 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 100 {
 101         struct fd3_context *fd3_ctx = fd3_context(ctx);
 102         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
 103
 104         if (!ir3_shader_key_equal(last_key, key)) {
 105                 ctx->dirty |= FD_DIRTY_PROG;
 106
 107                 if (last_key->has_per_samp || key->has_per_samp) {
 108                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
 109                                         (last_key->vsaturate_t != key->vsaturate_t) ||
 110                                         (last_key->vsaturate_r != key->vsaturate_r))
 111                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
 112
 113                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 114                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 115                                         (last_key->fsaturate_r != key->fsaturate_r))
 116                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 117                 }
 118
 119                 if (last_key->color_two_side != key->color_two_side)
 120                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 121
 122                 if (last_key->half_precision != key->half_precision)
 123                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 124
 125                 fd3_ctx->last_key = *key;
 126         }
 127 }
 128
 129 static void
 130 fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 131 {
 132         struct fd3_context *fd3_ctx = fd3_context(ctx);
 133         struct fd3_emit emit = {
 134                 .vtx  = &ctx->vtx,
 135                 .prog = &ctx->prog,
 136                 .info = info,
 137                 .key = {
 138                         /* do binning pass first: */
 139                         .binning_pass = true,
 140                         .color_two_side = ctx->rasterizer->light_twoside,
 141                         // TODO set .half_precision based on render target format,
 142                         // ie. float16 and smaller use half, float32 use full..
 143                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 144                         .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate),
 145                         .vsaturate_s = fd3_ctx->vsaturate_s,
 146                         .vsaturate_t = fd3_ctx->vsaturate_t,
 147                         .vsaturate_r = fd3_ctx->vsaturate_r,
 148                         .fsaturate_s = fd3_ctx->fsaturate_s,
 149                         .fsaturate_t = fd3_ctx->fsaturate_t,
 150                         .fsaturate_r = fd3_ctx->fsaturate_r,
 151                 },
 152                 .rasterflat = ctx->rasterizer->flatshade,
 153                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 154                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 155         };
 156         unsigned dirty;
 157
 158         fixup_shader_state(ctx, &emit.key);
 159
 160         dirty = ctx->dirty;
 161         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 162         draw_impl(ctx, ctx->binning_ring, &emit);
 163
 164         /* and now regular (non-binning) pass: */
 165         emit.key.binning_pass = false;
 166         emit.dirty = dirty;
 167         emit.vp = NULL;   /* we changed key so need to refetch vp */
 168         draw_impl(ctx, ctx->ring, &emit);
 169 }
 170
 171 /* clear operations ignore viewport state, so we need to reset it
 172  * based on framebuffer state:
 173  */
 174 static void
 175 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 176 {
 177         float half_width = pfb->width * 0.5f;
 178         float half_height = pfb->height * 0.5f;
 179
 180         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 181         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 182         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 183         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 184         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 185 }
 186
 187 /* binning pass cmds for a clear:
 188  * NOTE: newer blob drivers don't use binning for clear, which is probably
 189  * preferable since it is low vtx count.  However that doesn't seem to
 190  * actually work for me.  Not sure if it is depending on support for
 191  * clear pass (rather than using solid-fill shader), or something else
 192  * that newer blob is doing differently.  Once that is figured out, we
 193  * can remove fd3_clear_binning().
 194  */
 195 static void
 196 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 197 {
 198         struct fd3_context *fd3_ctx = fd3_context(ctx);
 199         struct fd_ringbuffer *ring = ctx->binning_ring;
 200         struct fd3_emit emit = {
 201                 .vtx  = &fd3_ctx->solid_vbuf_state,
 202                 .prog = &ctx->solid_prog,
 203                 .key = {
 204                         .binning_pass = true,
 205                         .half_precision = true,
 206                 },
 207                 .dirty = dirty,
 208         };
 209
 210         fd3_emit_state(ctx, ring, &emit);
 211         fd3_emit_vertex_bufs(ring, &emit);
 212         reset_viewport(ring, &ctx->framebuffer);
 213
 214         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 215         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 216                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 217                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 218                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 219         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 220         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 221         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 222         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 223         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 224         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 225         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 226
 227         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 228
 229         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 230                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 231 }
 232
 233 static void
 234 fd3_clear(struct fd_context *ctx, unsigned buffers,
 235                 const union pipe_color_union *color, double depth, unsigned stencil)
 236 {
 237         struct fd3_context *fd3_ctx = fd3_context(ctx);
 238         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 239         struct fd_ringbuffer *ring = ctx->ring;
 240         unsigned dirty = ctx->dirty;
 241         unsigned i;
 242         struct fd3_emit emit = {
 243                 .vtx  = &fd3_ctx->solid_vbuf_state,
 244                 .prog = &ctx->solid_prog,
 245                 .key = {
 246                         .half_precision = fd_half_precision(pfb),
 247                 },
 248         };
 249
 250         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 251         dirty |= FD_DIRTY_PROG;
 252         emit.dirty = dirty;
 253
 254         fd3_clear_binning(ctx, dirty);
 255
 256         /* emit generic state now: */
 257         fd3_emit_state(ctx, ring, &emit);
 258         reset_viewport(ring, &ctx->framebuffer);
 259
 260         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 261         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 262                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 263
 264         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 265         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 266                         &fd3_ctx->rbrc_patches);
 267
 268         if (buffers & PIPE_CLEAR_DEPTH) {
 269                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 270                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 271                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 272                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 273
 274                 fd_wfi(ctx, ring);
 275                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 276                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 277                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 278                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 279         } else {
 280                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 281                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 282         }
 283
 284         if (buffers & PIPE_CLEAR_STENCIL) {
 285                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 286                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 287                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 288                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 289                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 290                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 291                                 0xff000000 | // XXX ???
 292                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 293
 294                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 295                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 296                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 297                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 298                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 299                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 300                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 301                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 302                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 303                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 304         } else {
 305                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 306                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 307                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 308                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 309                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 310                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 311                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 312
 313                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 314                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 315                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 316                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 317                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 318                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 319                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 320                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 321                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 322         }
 323
 324         for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
 325                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 326                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 327                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 328                                 COND(buffers & (PIPE_CLEAR_COLOR0 << i),
 329                                          A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
 330
 331                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 332                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 333                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 334                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 335                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 336                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 337                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 338         }
 339
 340         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 341         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 342
 343         fd3_emit_vertex_bufs(ring, &emit);
 344
 345         fd3_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 346
 347         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 348         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 349                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 350                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 351                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 352         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 353         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 354         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 355         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 356         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 357         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 358         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 359
 360         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 361
 362         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 363                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 364 }
 365
 366 void
 367 fd3_draw_init(struct pipe_context *pctx)
 368 {
 369         struct fd_context *ctx = fd_context(pctx);
 370         ctx->draw_vbo = fd3_draw_vbo;
 371         ctx->clear = fd3_clear;
 372 }