1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
33 #include "util/u_format.h"
35 #include "freedreno_state.h"
36 #include "freedreno_resource.h"
39 #include "fd3_context.h"
41 #include "fd3_program.h"
42 #include "fd3_format.h"
45 static inline uint32_t
46 add_sat(uint32_t a
, int32_t b
)
48 int64_t ret
= (uint64_t)a
+ (int64_t)b
;
57 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
58 struct fd3_emit
*emit
)
60 const struct pipe_draw_info
*info
= emit
->info
;
61 enum pc_di_primtype primtype
= ctx
->primtypes
[info
->mode
];
63 if (!(fd3_emit_get_vp(emit
) && fd3_emit_get_fp(emit
)))
66 fd3_emit_state(ctx
, ring
, emit
);
68 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
69 fd3_emit_vertex_bufs(ring
, emit
);
71 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
72 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
74 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
75 OUT_RING(ring
, add_sat(info
->min_index
, info
->index_bias
)); /* VFD_INDEX_MIN */
76 OUT_RING(ring
, add_sat(info
->max_index
, info
->index_bias
)); /* VFD_INDEX_MAX */
77 OUT_RING(ring
, info
->start_instance
); /* VFD_INSTANCEID_OFFSET */
78 OUT_RING(ring
, info
->indexed
? info
->index_bias
: info
->start
); /* VFD_INDEX_OFFSET */
80 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
81 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
82 info
->restart_index
: 0xffffffff);
84 /* points + psize -> spritelist: */
85 if (ctx
->rasterizer
->point_size_per_vertex
&&
86 fd3_emit_get_vp(emit
)->writes_psize
&&
87 (info
->mode
== PIPE_PRIM_POINTS
))
88 primtype
= DI_PT_POINTLIST_PSIZE
;
90 fd_draw_emit(ctx
, ring
,
92 emit
->key
.binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
96 /* fixup dirty shader state in case some "unrelated" (from the state-
97 * tracker's perspective) state change causes us to switch to a
101 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
103 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
104 struct ir3_shader_key
*last_key
= &fd3_ctx
->last_key
;
106 if (!ir3_shader_key_equal(last_key
, key
)) {
107 ctx
->dirty
|= FD_DIRTY_PROG
;
109 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
110 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
111 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
112 (last_key
->vsaturate_r
!= key
->vsaturate_r
))
113 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_VP
;
115 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
116 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
117 (last_key
->fsaturate_r
!= key
->fsaturate_r
))
118 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
121 if (last_key
->color_two_side
!= key
->color_two_side
)
122 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
124 if (last_key
->half_precision
!= key
->half_precision
)
125 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
127 fd3_ctx
->last_key
= *key
;
132 fd3_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
134 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
135 struct fd3_emit emit
= {
140 /* do binning pass first: */
141 .binning_pass
= true,
142 .color_two_side
= ctx
->rasterizer
->light_twoside
,
143 // TODO set .half_precision based on render target format,
144 // ie. float16 and smaller use half, float32 use full..
145 .half_precision
= !!(fd_mesa_debug
& FD_DBG_FRAGHALF
),
146 .has_per_samp
= (fd3_ctx
->fsaturate
|| fd3_ctx
->vsaturate
),
147 .vsaturate_s
= fd3_ctx
->vsaturate_s
,
148 .vsaturate_t
= fd3_ctx
->vsaturate_t
,
149 .vsaturate_r
= fd3_ctx
->vsaturate_r
,
150 .fsaturate_s
= fd3_ctx
->fsaturate_s
,
151 .fsaturate_t
= fd3_ctx
->fsaturate_t
,
152 .fsaturate_r
= fd3_ctx
->fsaturate_r
,
154 .rasterflat
= ctx
->rasterizer
->flatshade
,
155 .sprite_coord_enable
= ctx
->rasterizer
->sprite_coord_enable
,
156 .sprite_coord_mode
= ctx
->rasterizer
->sprite_coord_mode
,
160 fixup_shader_state(ctx
, &emit
.key
);
163 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
164 draw_impl(ctx
, ctx
->binning_ring
, &emit
);
166 /* and now regular (non-binning) pass: */
167 emit
.key
.binning_pass
= false;
169 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
170 draw_impl(ctx
, ctx
->ring
, &emit
);
173 /* clear operations ignore viewport state, so we need to reset it
174 * based on framebuffer state:
177 reset_viewport(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
)
179 float half_width
= pfb
->width
* 0.5f
;
180 float half_height
= pfb
->height
* 0.5f
;
182 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 4);
183 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(half_width
- 0.5));
184 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(half_width
));
185 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(half_height
- 0.5));
186 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-half_height
));
189 /* binning pass cmds for a clear:
190 * NOTE: newer blob drivers don't use binning for clear, which is probably
191 * preferable since it is low vtx count. However that doesn't seem to
192 * actually work for me. Not sure if it is depending on support for
193 * clear pass (rather than using solid-fill shader), or something else
194 * that newer blob is doing differently. Once that is figured out, we
195 * can remove fd3_clear_binning().
198 fd3_clear_binning(struct fd_context
*ctx
, unsigned dirty
)
200 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
201 struct fd_ringbuffer
*ring
= ctx
->binning_ring
;
202 struct fd3_emit emit
= {
203 .vtx
= &fd3_ctx
->solid_vbuf_state
,
204 .prog
= &ctx
->solid_prog
,
206 .binning_pass
= true,
207 .half_precision
= true,
212 fd3_emit_state(ctx
, ring
, &emit
);
213 fd3_emit_vertex_bufs(ring
, &emit
);
214 reset_viewport(ring
, &ctx
->framebuffer
);
216 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
217 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
218 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
219 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
220 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
221 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
222 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
223 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
224 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
225 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
226 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
227 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
229 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
231 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
232 DI_SRC_SEL_AUTO_INDEX
, 2, 0, INDEX_SIZE_IGN
, 0, 0, NULL
);
236 fd3_clear(struct fd_context
*ctx
, unsigned buffers
,
237 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
239 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
240 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
241 struct fd_ringbuffer
*ring
= ctx
->ring
;
242 unsigned dirty
= ctx
->dirty
;
244 struct fd3_emit emit
= {
245 .vtx
= &fd3_ctx
->solid_vbuf_state
,
246 .prog
= &ctx
->solid_prog
,
248 .half_precision
= fd_half_precision(pfb
),
252 dirty
&= FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
;
253 dirty
|= FD_DIRTY_PROG
;
256 fd3_clear_binning(ctx
, dirty
);
258 /* emit generic state now: */
259 fd3_emit_state(ctx
, ring
, &emit
);
260 reset_viewport(ring
, &ctx
->framebuffer
);
262 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_ALPHA
, 1);
263 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
264 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
266 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
267 OUT_RINGP(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
),
268 &fd3_ctx
->rbrc_patches
);
270 if (buffers
& PIPE_CLEAR_DEPTH
) {
271 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
272 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
273 A3XX_RB_DEPTH_CONTROL_Z_ENABLE
|
274 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
));
277 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_ZOFFSET
, 2);
278 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
279 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(depth
));
280 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
282 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
283 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
286 if (buffers
& PIPE_CLEAR_STENCIL
) {
287 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
288 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(stencil
) |
289 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil
) |
290 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
291 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
292 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
293 0xff000000 | // XXX ???
294 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
296 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
297 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
298 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
299 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
300 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE
) |
301 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
302 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
303 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
304 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
305 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
307 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
308 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
309 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
310 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
311 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
312 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
313 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
315 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
316 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
317 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
318 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
319 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
320 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
321 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
322 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
323 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
326 for (i
= 0; i
< A3XX_MAX_RENDER_TARGETS
; i
++) {
327 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
328 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
329 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS
) |
330 COND(buffers
& (PIPE_CLEAR_COLOR0
<< i
),
331 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
333 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
334 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
335 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
336 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
337 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
338 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
339 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
342 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
343 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
345 fd3_emit_vertex_bufs(ring
, &emit
);
347 fd3_emit_const(ring
, SHADER_FRAGMENT
, 0, 0, 4, color
->ui
, NULL
);
349 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
350 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
351 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
352 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
353 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
354 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
355 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
356 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
357 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
358 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
359 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
360 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
362 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
364 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, USE_VISIBILITY
,
365 DI_SRC_SEL_AUTO_INDEX
, 2, 0, INDEX_SIZE_IGN
, 0, 0, NULL
);
369 fd3_draw_init(struct pipe_context
*pctx
)
371 struct fd_context
*ctx
= fd_context(pctx
);
372 ctx
->draw_vbo
= fd3_draw_vbo
;
373 ctx
->clear
= fd3_clear
;