src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_format.h"
  43 #include "fd3_zsa.h"
  44
  45 static inline uint32_t
  46 add_sat(uint32_t a, int32_t b)
  47 {
  48         int64_t ret = (uint64_t)a + (int64_t)b;
  49         if (ret > ~0U)
  50                 return ~0U;
  51         if (ret < 0)
  52                 return 0;
  53         return (uint32_t)ret;
  54 }
  55
  56 static void
  57 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  58                 struct fd3_emit *emit)
  59 {
  60         const struct pipe_draw_info *info = emit->info;
  61
  62         fd3_emit_state(ctx, ring, emit);
  63
  64         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  65                 fd3_emit_vertex_bufs(ring, emit);
  66
  67         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  68         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  69
  70         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  71         OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
  72         OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
  73         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  74         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  75
  76         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  77         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  78                         info->restart_index : 0xffffffff);
  79
  80         fd_draw_emit(ctx, ring,
  81                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  82                         info);
  83 }
  84
  85 /* fixup dirty shader state in case some "unrelated" (from the state-
  86  * tracker's perspective) state change causes us to switch to a
  87  * different variant.
  88  */
  89 static void
  90 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  91 {
  92         struct fd3_context *fd3_ctx = fd3_context(ctx);
  93         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
  94
  95         if (!ir3_shader_key_equal(last_key, key)) {
  96                 ctx->dirty |= FD_DIRTY_PROG;
  97
  98                 if (last_key->has_per_samp || key->has_per_samp) {
  99                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
 100                                         (last_key->vsaturate_t != key->vsaturate_t) ||
 101                                         (last_key->vsaturate_r != key->vsaturate_r) ||
 102                                         (last_key->vinteger_s != key->vinteger_s))
 103                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
 104
 105                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 106                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 107                                         (last_key->fsaturate_r != key->fsaturate_r) ||
 108                                         (last_key->finteger_s != key->finteger_s))
 109                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 110                 }
 111
 112                 if (last_key->color_two_side != key->color_two_side)
 113                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 114
 115                 if (last_key->half_precision != key->half_precision)
 116                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 117
 118                 if (last_key->alpha != key->alpha)
 119                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 120
 121                 fd3_ctx->last_key = *key;
 122         }
 123 }
 124
 125 static void
 126 fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 127 {
 128         struct fd3_context *fd3_ctx = fd3_context(ctx);
 129         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 130         struct fd3_emit emit = {
 131                 .vtx  = &ctx->vtx,
 132                 .prog = &ctx->prog,
 133                 .info = info,
 134                 .key = {
 135                         /* do binning pass first: */
 136                         .binning_pass = true,
 137                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 138                         .alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])),
 139                         // TODO set .half_precision based on render target format,
 140                         // ie. float16 and smaller use half, float32 use full..
 141                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 142                         .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate ||
 143                                                          fd3_ctx->vinteger_s || fd3_ctx->finteger_s),
 144                         .vsaturate_s = fd3_ctx->vsaturate_s,
 145                         .vsaturate_t = fd3_ctx->vsaturate_t,
 146                         .vsaturate_r = fd3_ctx->vsaturate_r,
 147                         .fsaturate_s = fd3_ctx->fsaturate_s,
 148                         .fsaturate_t = fd3_ctx->fsaturate_t,
 149                         .fsaturate_r = fd3_ctx->fsaturate_r,
 150                         .vinteger_s = fd3_ctx->vinteger_s,
 151                         .finteger_s = fd3_ctx->finteger_s,
 152                 },
 153                 .format = pipe_surface_format(pfb->cbufs[0]),
 154                 .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 155         };
 156         unsigned dirty;
 157
 158         fixup_shader_state(ctx, &emit.key);
 159
 160         dirty = ctx->dirty;
 161         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 162         draw_impl(ctx, ctx->binning_ring, &emit);
 163
 164         /* and now regular (non-binning) pass: */
 165         emit.key.binning_pass = false;
 166         emit.dirty = dirty;
 167         emit.vp = NULL;   /* we changed key so need to refetch vp */
 168         draw_impl(ctx, ctx->ring, &emit);
 169 }
 170
 171 /* clear operations ignore viewport state, so we need to reset it
 172  * based on framebuffer state:
 173  */
 174 static void
 175 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 176 {
 177         float half_width = pfb->width * 0.5f;
 178         float half_height = pfb->height * 0.5f;
 179
 180         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 181         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 182         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 183         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 184         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 185 }
 186
 187 /* binning pass cmds for a clear:
 188  * NOTE: newer blob drivers don't use binning for clear, which is probably
 189  * preferable since it is low vtx count.  However that doesn't seem to
 190  * actually work for me.  Not sure if it is depending on support for
 191  * clear pass (rather than using solid-fill shader), or something else
 192  * that newer blob is doing differently.  Once that is figured out, we
 193  * can remove fd3_clear_binning().
 194  */
 195 static void
 196 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 197 {
 198         struct fd3_context *fd3_ctx = fd3_context(ctx);
 199         struct fd_ringbuffer *ring = ctx->binning_ring;
 200         struct fd3_emit emit = {
 201                 .vtx  = &fd3_ctx->solid_vbuf_state,
 202                 .prog = &ctx->solid_prog,
 203                 .key = {
 204                         .binning_pass = true,
 205                         .half_precision = true,
 206                 },
 207                 .dirty = dirty,
 208         };
 209
 210         fd3_emit_state(ctx, ring, &emit);
 211         fd3_emit_vertex_bufs(ring, &emit);
 212         reset_viewport(ring, &ctx->framebuffer);
 213
 214         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 215         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 216                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 217                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 218                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 219         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 220         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 221         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 222         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 223         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 224         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 225         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 226
 227         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 228
 229         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 230                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 231 }
 232
 233 static void
 234 fd3_clear(struct fd_context *ctx, unsigned buffers,
 235                 const union pipe_color_union *color, double depth, unsigned stencil)
 236 {
 237         struct fd3_context *fd3_ctx = fd3_context(ctx);
 238         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 239         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 240         struct fd_ringbuffer *ring = ctx->ring;
 241         unsigned dirty = ctx->dirty;
 242         unsigned ce, i;
 243         struct fd3_emit emit = {
 244                 .vtx  = &fd3_ctx->solid_vbuf_state,
 245                 .prog = &ctx->solid_prog,
 246                 .key = {
 247                         .half_precision = fd3_half_precision(format),
 248                 },
 249                 .format = format,
 250         };
 251
 252         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 253         dirty |= FD_DIRTY_PROG;
 254         emit.dirty = dirty;
 255
 256         fd3_clear_binning(ctx, dirty);
 257
 258         /* emit generic state now: */
 259         fd3_emit_state(ctx, ring, &emit);
 260         reset_viewport(ring, &ctx->framebuffer);
 261
 262         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 263         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 264                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 265
 266         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 267         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 268                         &fd3_ctx->rbrc_patches);
 269
 270         if (buffers & PIPE_CLEAR_DEPTH) {
 271                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 272                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 273                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 274                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 275
 276                 fd_wfi(ctx, ring);
 277                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 278                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 279                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 280                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 281         } else {
 282                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 283                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 284         }
 285
 286         if (buffers & PIPE_CLEAR_STENCIL) {
 287                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 288                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 289                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 290                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 291                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 292                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 293                                 0xff000000 | // XXX ???
 294                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 295
 296                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 297                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 298                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 299                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 300                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 301                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 302                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 303                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 304                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 305                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 306         } else {
 307                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 308                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 309                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 310                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 311                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 312                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 313                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 314
 315                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 316                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 317                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 318                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 319                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 320                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 321                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 322                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 323                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 324         }
 325
 326         if (buffers & PIPE_CLEAR_COLOR) {
 327                 ce = 0xf;
 328         } else {
 329                 ce = 0x0;
 330         }
 331
 332         for (i = 0; i < 4; i++) {
 333                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 334                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 335                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 336                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 337
 338                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 339                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 340                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 341                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 342                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 343                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 344                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 345         }
 346
 347         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 348         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 349
 350         fd3_emit_vertex_bufs(ring, &emit);
 351
 352         fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 353
 354         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 355         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 356                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 357                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 358                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 359         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 360         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 361         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 362         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 363         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 364         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 365         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 366
 367         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 368
 369         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 370                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 371 }
 372
 373 void
 374 fd3_draw_init(struct pipe_context *pctx)
 375 {
 376         struct fd_context *ctx = fd_context(pctx);
 377         ctx->draw_vbo = fd3_draw_vbo;
 378         ctx->clear = fd3_clear;
 379 }