src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd3_draw.h"
  38 #include "fd3_context.h"
  39 #include "fd3_emit.h"
  40 #include "fd3_program.h"
  41 #include "fd3_util.h"
  42 #include "fd3_zsa.h"
  43
  44
  45 static void
  46 emit_vertexbufs(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd3_shader_key key)
  48 {
  49         struct fd_vertex_stateobj *vtx = ctx->vtx;
  50         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vertexbuf;
  51         struct fd3_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  52         unsigned i;
  53
  54         if (!vtx->num_elements)
  55                 return;
  56
  57         for (i = 0; i < vtx->num_elements; i++) {
  58                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  59                 struct pipe_vertex_buffer *vb =
  60                                 &vertexbuf->vb[elem->vertex_buffer_index];
  61                 bufs[i].offset = vb->buffer_offset + elem->src_offset;
  62                 bufs[i].stride = vb->stride;
  63                 bufs[i].prsc   = vb->buffer;
  64                 bufs[i].format = elem->src_format;
  65         }
  66
  67         fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->prog.vp, key),
  68                         bufs, vtx->num_elements);
  69 }
  70
  71 static void
  72 draw_impl(struct fd_context *ctx, const struct pipe_draw_info *info,
  73                 struct fd_ringbuffer *ring, unsigned dirty, struct fd3_shader_key key)
  74 {
  75         fd3_emit_state(ctx, ring, &ctx->prog, dirty, key);
  76
  77         if (dirty & FD_DIRTY_VTXBUF)
  78                 emit_vertexbufs(ctx, ring, key);
  79
  80         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  81         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  82
  83         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  84         OUT_RING(ring, info->min_index);        /* VFD_INDEX_MIN */
  85         OUT_RING(ring, info->max_index);        /* VFD_INDEX_MAX */
  86         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  87         OUT_RING(ring, info->start);            /* VFD_INDEX_OFFSET */
  88
  89         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  90         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  91                         info->restart_index : 0xffffffff);
  92
  93         fd_draw_emit(ctx, ring,
  94                         key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  95                         info);
  96 }
  97
  98 static void
  99 fd3_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
 100 {
 101         unsigned dirty = ctx->dirty;
 102         struct fd3_shader_key key = {
 103                         /* do binning pass first: */
 104                         .binning_pass = true,
 105                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 106                         // TODO set .half_precision based on render target format,
 107                         // ie. float16 and smaller use half, float32 use full..
 108                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 109         };
 110         draw_impl(ctx, info, ctx->binning_ring,
 111                         dirty & ~(FD_DIRTY_BLEND), key);
 112         /* and now regular (non-binning) pass: */
 113         key.binning_pass = false;
 114         draw_impl(ctx, info, ctx->ring, dirty, key);
 115 }
 116
 117 /* binning pass cmds for a clear:
 118  * NOTE: newer blob drivers don't use binning for clear, which is probably
 119  * preferable since it is low vtx count.  However that doesn't seem to
 120  * actually work for me.  Not sure if it is depending on support for
 121  * clear pass (rather than using solid-fill shader), or something else
 122  * that newer blob is doing differently.  Once that is figured out, we
 123  * can remove fd3_clear_binning().
 124  */
 125 static void
 126 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 127 {
 128         struct fd3_context *fd3_ctx = fd3_context(ctx);
 129         struct fd_ringbuffer *ring = ctx->binning_ring;
 130         struct fd3_shader_key key = {
 131                         .binning_pass = true,
 132                         .half_precision = true,
 133         };
 134
 135         fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, key);
 136
 137         fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
 138                         (struct fd3_vertex_buf[]) {{
 139                                 .prsc = fd3_ctx->solid_vbuf,
 140                                 .stride = 12,
 141                                 .format = PIPE_FORMAT_R32G32B32_FLOAT,
 142                         }}, 1);
 143
 144         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 145         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 146                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 147                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 148                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 149         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 150         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 151         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 152         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 153         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 154         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 155         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 156
 157         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 158
 159         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 160                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 161 }
 162
 163 static void
 164 fd3_clear(struct fd_context *ctx, unsigned buffers,
 165                 const union pipe_color_union *color, double depth, unsigned stencil)
 166 {
 167         struct fd3_context *fd3_ctx = fd3_context(ctx);
 168         struct fd_ringbuffer *ring = ctx->ring;
 169         unsigned dirty = ctx->dirty;
 170         unsigned ce, i;
 171         struct fd3_shader_key key = {
 172                         .half_precision = true,
 173         };
 174
 175         dirty &= FD_DIRTY_VIEWPORT | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 176         dirty |= FD_DIRTY_PROG;
 177
 178         fd3_clear_binning(ctx, dirty);
 179
 180         /* emit generic state now: */
 181         fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, key);
 182
 183         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 184         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 185                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 186
 187         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 188         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 189                         &fd3_ctx->rbrc_patches);
 190
 191         if (buffers & PIPE_CLEAR_DEPTH) {
 192                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 193                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 194                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 195                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 196
 197                 fd_wfi(ctx, ring);
 198                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 199                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 200                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 201                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 202         } else {
 203                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 204                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 205         }
 206
 207         if (buffers & PIPE_CLEAR_STENCIL) {
 208                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 209                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 210                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 211                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 212                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 213                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 214                                 0xff000000 | // XXX ???
 215                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 216
 217                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 218                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 219                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 220                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 221                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 222                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 223                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 224                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 225                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 226                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 227         } else {
 228                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 229                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 230                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 231                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 232                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 233                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 234                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 235
 236                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 237                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 238                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 239                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 240                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 241                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 242                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 243                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 244                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 245         }
 246
 247         if (buffers & PIPE_CLEAR_COLOR) {
 248                 ce = 0xf;
 249         } else {
 250                 ce = 0x0;
 251         }
 252
 253         for (i = 0; i < 4; i++) {
 254                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 255                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 256                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 257                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 258
 259                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 260                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 261                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 262                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 263                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 264                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 265                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
 266                                 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
 267         }
 268
 269         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 270         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 271
 272         fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
 273                         (struct fd3_vertex_buf[]) {{
 274                                 .prsc = fd3_ctx->solid_vbuf,
 275                                 .stride = 12,
 276                                 .format = PIPE_FORMAT_R32G32B32_FLOAT,
 277                         }}, 1);
 278
 279         fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 280
 281         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 282         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 283                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 284                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 285                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 286         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 287         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 288         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 289         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 290         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 291         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 292         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 293
 294         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 295
 296         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 297                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 298 }
 299
 300 void
 301 fd3_draw_init(struct pipe_context *pctx)
 302 {
 303         struct fd_context *ctx = fd_context(pctx);
 304         ctx->draw = fd3_draw;
 305         ctx->clear = fd3_clear;
 306 }