src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_format.h"
  43 #include "fd3_zsa.h"
  44
  45 static inline uint32_t
  46 add_sat(uint32_t a, int32_t b)
  47 {
  48         int64_t ret = (uint64_t)a + (int64_t)b;
  49         if (ret > ~0U)
  50                 return ~0U;
  51         if (ret < 0)
  52                 return 0;
  53         return (uint32_t)ret;
  54 }
  55
  56 static void
  57 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  58                 struct fd3_emit *emit)
  59 {
  60         const struct pipe_draw_info *info = emit->info;
  61         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  62
  63         fd3_emit_state(ctx, ring, emit);
  64
  65         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  66                 fd3_emit_vertex_bufs(ring, emit);
  67
  68         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  69         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  70
  71         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  72         OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
  73         OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
  74         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  75         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  76
  77         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  78         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  79                         info->restart_index : 0xffffffff);
  80
  81         if (ctx->rasterizer && ctx->rasterizer->point_size_per_vertex &&
  82                 info->mode == PIPE_PRIM_POINTS)
  83                 primtype = DI_PT_POINTLIST_A2XX;
  84
  85         fd_draw_emit(ctx, ring,
  86                         primtype,
  87                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  88                         info);
  89 }
  90
  91 /* fixup dirty shader state in case some "unrelated" (from the state-
  92  * tracker's perspective) state change causes us to switch to a
  93  * different variant.
  94  */
  95 static void
  96 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  97 {
  98         struct fd3_context *fd3_ctx = fd3_context(ctx);
  99         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
 100
 101         if (!ir3_shader_key_equal(last_key, key)) {
 102                 ctx->dirty |= FD_DIRTY_PROG;
 103
 104                 if (last_key->has_per_samp || key->has_per_samp) {
 105                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
 106                                         (last_key->vsaturate_t != key->vsaturate_t) ||
 107                                         (last_key->vsaturate_r != key->vsaturate_r) ||
 108                                         (last_key->vinteger_s != key->vinteger_s))
 109                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
 110
 111                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 112                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 113                                         (last_key->fsaturate_r != key->fsaturate_r) ||
 114                                         (last_key->finteger_s != key->finteger_s))
 115                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 116                 }
 117
 118                 if (last_key->color_two_side != key->color_two_side)
 119                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 120
 121                 if (last_key->half_precision != key->half_precision)
 122                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 123
 124                 if (last_key->alpha != key->alpha)
 125                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 126
 127                 fd3_ctx->last_key = *key;
 128         }
 129 }
 130
 131 static void
 132 fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 133 {
 134         struct fd3_context *fd3_ctx = fd3_context(ctx);
 135         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 136         struct fd3_emit emit = {
 137                 .vtx  = &ctx->vtx,
 138                 .prog = &ctx->prog,
 139                 .info = info,
 140                 .key = {
 141                         /* do binning pass first: */
 142                         .binning_pass = true,
 143                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 144                         .alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])),
 145                         // TODO set .half_precision based on render target format,
 146                         // ie. float16 and smaller use half, float32 use full..
 147                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 148                         .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate ||
 149                                                          fd3_ctx->vinteger_s || fd3_ctx->finteger_s),
 150                         .vsaturate_s = fd3_ctx->vsaturate_s,
 151                         .vsaturate_t = fd3_ctx->vsaturate_t,
 152                         .vsaturate_r = fd3_ctx->vsaturate_r,
 153                         .fsaturate_s = fd3_ctx->fsaturate_s,
 154                         .fsaturate_t = fd3_ctx->fsaturate_t,
 155                         .fsaturate_r = fd3_ctx->fsaturate_r,
 156                         .vinteger_s = fd3_ctx->vinteger_s,
 157                         .finteger_s = fd3_ctx->finteger_s,
 158                 },
 159                 .format = pipe_surface_format(pfb->cbufs[0]),
 160                 .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 161                 .sprite_coord_enable = ctx->rasterizer ? ctx->rasterizer->sprite_coord_enable : 0,
 162         };
 163         unsigned dirty;
 164
 165         fixup_shader_state(ctx, &emit.key);
 166
 167         dirty = ctx->dirty;
 168         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 169         draw_impl(ctx, ctx->binning_ring, &emit);
 170
 171         /* and now regular (non-binning) pass: */
 172         emit.key.binning_pass = false;
 173         emit.dirty = dirty;
 174         emit.vp = NULL;   /* we changed key so need to refetch vp */
 175         draw_impl(ctx, ctx->ring, &emit);
 176 }
 177
 178 /* clear operations ignore viewport state, so we need to reset it
 179  * based on framebuffer state:
 180  */
 181 static void
 182 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 183 {
 184         float half_width = pfb->width * 0.5f;
 185         float half_height = pfb->height * 0.5f;
 186
 187         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 188         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 189         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 190         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 191         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 192 }
 193
 194 /* binning pass cmds for a clear:
 195  * NOTE: newer blob drivers don't use binning for clear, which is probably
 196  * preferable since it is low vtx count.  However that doesn't seem to
 197  * actually work for me.  Not sure if it is depending on support for
 198  * clear pass (rather than using solid-fill shader), or something else
 199  * that newer blob is doing differently.  Once that is figured out, we
 200  * can remove fd3_clear_binning().
 201  */
 202 static void
 203 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 204 {
 205         struct fd3_context *fd3_ctx = fd3_context(ctx);
 206         struct fd_ringbuffer *ring = ctx->binning_ring;
 207         struct fd3_emit emit = {
 208                 .vtx  = &fd3_ctx->solid_vbuf_state,
 209                 .prog = &ctx->solid_prog,
 210                 .key = {
 211                         .binning_pass = true,
 212                         .half_precision = true,
 213                 },
 214                 .dirty = dirty,
 215         };
 216
 217         fd3_emit_state(ctx, ring, &emit);
 218         fd3_emit_vertex_bufs(ring, &emit);
 219         reset_viewport(ring, &ctx->framebuffer);
 220
 221         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 222         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 223                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 224                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 225                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 226         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 227         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 228         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 229         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 230         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 231         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 232         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 233
 234         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 235
 236         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 237                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 238 }
 239
 240 static void
 241 fd3_clear(struct fd_context *ctx, unsigned buffers,
 242                 const union pipe_color_union *color, double depth, unsigned stencil)
 243 {
 244         struct fd3_context *fd3_ctx = fd3_context(ctx);
 245         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 246         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 247         struct fd_ringbuffer *ring = ctx->ring;
 248         unsigned dirty = ctx->dirty;
 249         unsigned ce, i;
 250         struct fd3_emit emit = {
 251                 .vtx  = &fd3_ctx->solid_vbuf_state,
 252                 .prog = &ctx->solid_prog,
 253                 .key = {
 254                         .half_precision = fd3_half_precision(format),
 255                 },
 256                 .format = format,
 257         };
 258
 259         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 260         dirty |= FD_DIRTY_PROG;
 261         emit.dirty = dirty;
 262
 263         fd3_clear_binning(ctx, dirty);
 264
 265         /* emit generic state now: */
 266         fd3_emit_state(ctx, ring, &emit);
 267         reset_viewport(ring, &ctx->framebuffer);
 268
 269         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 270         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 271                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 272
 273         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 274         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 275                         &fd3_ctx->rbrc_patches);
 276
 277         if (buffers & PIPE_CLEAR_DEPTH) {
 278                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 279                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 280                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 281                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 282
 283                 fd_wfi(ctx, ring);
 284                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 285                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 286                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 287                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 288         } else {
 289                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 290                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 291         }
 292
 293         if (buffers & PIPE_CLEAR_STENCIL) {
 294                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 295                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 296                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 297                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 298                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 299                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 300                                 0xff000000 | // XXX ???
 301                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 302
 303                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 304                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 305                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 306                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 307                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 308                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 309                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 310                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 311                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 312                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 313         } else {
 314                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 315                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 316                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 317                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 318                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 319                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 320                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 321
 322                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 323                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 324                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 325                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 326                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 327                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 328                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 329                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 330                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 331         }
 332
 333         if (buffers & PIPE_CLEAR_COLOR) {
 334                 ce = 0xf;
 335         } else {
 336                 ce = 0x0;
 337         }
 338
 339         for (i = 0; i < 4; i++) {
 340                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 341                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 342                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 343                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 344
 345                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 346                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 347                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 348                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 349                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 350                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 351                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 352         }
 353
 354         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 355         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 356
 357         fd3_emit_vertex_bufs(ring, &emit);
 358
 359         fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 360
 361         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 362         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 363                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 364                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 365                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 366         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 367         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 368         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 369         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 370         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 371         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 372         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 373
 374         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 375
 376         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 377                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 378 }
 379
 380 void
 381 fd3_draw_init(struct pipe_context *pctx)
 382 {
 383         struct fd_context *ctx = fd_context(pctx);
 384         ctx->draw_vbo = fd3_draw_vbo;
 385         ctx->clear = fd3_clear;
 386 }