1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
33 #include "util/u_format.h"
35 #include "freedreno_state.h"
36 #include "freedreno_resource.h"
39 #include "fd3_context.h"
41 #include "fd3_program.h"
42 #include "fd3_format.h"
45 static inline uint32_t
46 add_sat(uint32_t a
, int32_t b
)
48 int64_t ret
= (uint64_t)a
+ (int64_t)b
;
57 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
58 struct fd3_emit
*emit
)
60 const struct pipe_draw_info
*info
= emit
->info
;
61 enum pc_di_primtype primtype
= ctx
->primtypes
[info
->mode
];
63 fd3_emit_state(ctx
, ring
, emit
);
65 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
66 fd3_emit_vertex_bufs(ring
, emit
);
68 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
69 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
71 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
72 OUT_RING(ring
, add_sat(info
->min_index
, info
->index_bias
)); /* VFD_INDEX_MIN */
73 OUT_RING(ring
, add_sat(info
->max_index
, info
->index_bias
)); /* VFD_INDEX_MAX */
74 OUT_RING(ring
, info
->start_instance
); /* VFD_INSTANCEID_OFFSET */
75 OUT_RING(ring
, info
->indexed
? info
->index_bias
: info
->start
); /* VFD_INDEX_OFFSET */
77 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
78 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
79 info
->restart_index
: 0xffffffff);
81 /* points + psize -> spritelist: */
82 if (ctx
->rasterizer
->point_size_per_vertex
&&
83 fd3_emit_get_vp(emit
)->writes_psize
&&
84 (info
->mode
== PIPE_PRIM_POINTS
))
85 primtype
= DI_PT_POINTLIST_PSIZE
;
87 fd_draw_emit(ctx
->batch
, ring
, primtype
,
88 emit
->key
.binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
92 /* fixup dirty shader state in case some "unrelated" (from the state-
93 * tracker's perspective) state change causes us to switch to a
97 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
99 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
100 struct ir3_shader_key
*last_key
= &fd3_ctx
->last_key
;
102 if (!ir3_shader_key_equal(last_key
, key
)) {
103 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
104 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
105 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
106 (last_key
->vsaturate_r
!= key
->vsaturate_r
))
107 ctx
->dirty
|= FD_SHADER_DIRTY_VP
;
109 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
110 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
111 (last_key
->fsaturate_r
!= key
->fsaturate_r
))
112 ctx
->dirty
|= FD_SHADER_DIRTY_FP
;
115 if (last_key
->vclamp_color
!= key
->vclamp_color
)
116 ctx
->dirty
|= FD_SHADER_DIRTY_VP
;
118 if (last_key
->fclamp_color
!= key
->fclamp_color
)
119 ctx
->dirty
|= FD_SHADER_DIRTY_FP
;
121 if (last_key
->color_two_side
!= key
->color_two_side
)
122 ctx
->dirty
|= FD_SHADER_DIRTY_FP
;
124 if (last_key
->half_precision
!= key
->half_precision
)
125 ctx
->dirty
|= FD_SHADER_DIRTY_FP
;
127 fd3_ctx
->last_key
= *key
;
132 fd3_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
134 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
135 struct fd3_emit emit
= {
136 .debug
= &ctx
->debug
,
141 .color_two_side
= ctx
->rasterizer
->light_twoside
,
142 .vclamp_color
= ctx
->rasterizer
->clamp_vertex_color
,
143 .fclamp_color
= ctx
->rasterizer
->clamp_fragment_color
,
144 // TODO set .half_precision based on render target format,
145 // ie. float16 and smaller use half, float32 use full..
146 .half_precision
= !!(fd_mesa_debug
& FD_DBG_FRAGHALF
),
147 .has_per_samp
= (fd3_ctx
->fsaturate
|| fd3_ctx
->vsaturate
),
148 .vsaturate_s
= fd3_ctx
->vsaturate_s
,
149 .vsaturate_t
= fd3_ctx
->vsaturate_t
,
150 .vsaturate_r
= fd3_ctx
->vsaturate_r
,
151 .fsaturate_s
= fd3_ctx
->fsaturate_s
,
152 .fsaturate_t
= fd3_ctx
->fsaturate_t
,
153 .fsaturate_r
= fd3_ctx
->fsaturate_r
,
155 .rasterflat
= ctx
->rasterizer
->flatshade
,
156 .sprite_coord_enable
= ctx
->rasterizer
->sprite_coord_enable
,
157 .sprite_coord_mode
= ctx
->rasterizer
->sprite_coord_mode
,
160 fixup_shader_state(ctx
, &emit
.key
);
162 unsigned dirty
= ctx
->dirty
;
164 /* do regular pass first, since that is more likely to fail compiling: */
166 if (!(fd3_emit_get_vp(&emit
) && fd3_emit_get_fp(&emit
)))
169 emit
.key
.binning_pass
= false;
171 draw_impl(ctx
, ctx
->batch
->draw
, &emit
);
173 /* and now binning pass: */
174 emit
.key
.binning_pass
= true;
175 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
176 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
178 draw_impl(ctx
, ctx
->batch
->binning
, &emit
);
183 /* clear operations ignore viewport state, so we need to reset it
184 * based on framebuffer state:
187 reset_viewport(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
)
189 float half_width
= pfb
->width
* 0.5f
;
190 float half_height
= pfb
->height
* 0.5f
;
192 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 4);
193 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(half_width
- 0.5));
194 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(half_width
));
195 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(half_height
- 0.5));
196 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-half_height
));
199 /* binning pass cmds for a clear:
200 * NOTE: newer blob drivers don't use binning for clear, which is probably
201 * preferable since it is low vtx count. However that doesn't seem to
202 * actually work for me. Not sure if it is depending on support for
203 * clear pass (rather than using solid-fill shader), or something else
204 * that newer blob is doing differently. Once that is figured out, we
205 * can remove fd3_clear_binning().
208 fd3_clear_binning(struct fd_context
*ctx
, unsigned dirty
)
210 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
211 struct fd_ringbuffer
*ring
= ctx
->batch
->binning
;
212 struct fd3_emit emit
= {
213 .debug
= &ctx
->debug
,
214 .vtx
= &fd3_ctx
->solid_vbuf_state
,
215 .prog
= &ctx
->solid_prog
,
217 .binning_pass
= true,
218 .half_precision
= true,
223 fd3_emit_state(ctx
, ring
, &emit
);
224 fd3_emit_vertex_bufs(ring
, &emit
);
225 reset_viewport(ring
, &ctx
->batch
->framebuffer
);
227 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
228 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
229 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
230 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
231 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
232 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
233 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
234 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
235 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
236 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
237 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
238 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
240 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
242 fd_draw(ctx
->batch
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
243 DI_SRC_SEL_AUTO_INDEX
, 2, 0, INDEX_SIZE_IGN
, 0, 0, NULL
);
247 fd3_clear(struct fd_context
*ctx
, unsigned buffers
,
248 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
250 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
251 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
252 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
253 unsigned dirty
= ctx
->dirty
;
255 struct fd3_emit emit
= {
256 .debug
= &ctx
->debug
,
257 .vtx
= &fd3_ctx
->solid_vbuf_state
,
258 .prog
= &ctx
->solid_prog
,
260 .half_precision
= fd_half_precision(pfb
),
264 dirty
&= FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
;
265 dirty
|= FD_DIRTY_PROG
;
268 fd3_clear_binning(ctx
, dirty
);
270 /* emit generic state now: */
271 fd3_emit_state(ctx
, ring
, &emit
);
272 reset_viewport(ring
, &ctx
->batch
->framebuffer
);
274 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_ALPHA
, 1);
275 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
276 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
278 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
279 OUT_RINGP(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
),
280 &ctx
->batch
->rbrc_patches
);
282 if (buffers
& PIPE_CLEAR_DEPTH
) {
283 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
284 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
285 A3XX_RB_DEPTH_CONTROL_Z_ENABLE
|
286 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
));
289 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_ZOFFSET
, 2);
290 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
291 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(depth
));
292 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
294 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
295 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
298 if (buffers
& PIPE_CLEAR_STENCIL
) {
299 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
300 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(stencil
) |
301 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil
) |
302 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
303 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
304 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
305 0xff000000 | // XXX ???
306 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
308 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
309 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
310 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
311 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
312 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE
) |
313 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
314 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
315 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
316 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
317 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
319 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
320 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
321 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
322 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
323 OUT_RING(ring
, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
324 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
325 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
327 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
328 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
329 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
330 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
331 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
332 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
333 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
334 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
335 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
338 for (i
= 0; i
< A3XX_MAX_RENDER_TARGETS
; i
++) {
339 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
340 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
341 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS
) |
342 COND(buffers
& (PIPE_CLEAR_COLOR0
<< i
),
343 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
345 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
346 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
347 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
348 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
349 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
350 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
351 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
354 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
355 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
357 fd3_emit_vertex_bufs(ring
, &emit
);
359 fd3_emit_const(ring
, SHADER_FRAGMENT
, 0, 0, 4, color
->ui
, NULL
);
361 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
362 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
363 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
364 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
365 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
366 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
367 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
368 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
369 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
370 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
371 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
372 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
374 fd_event_write(ctx
, ring
, PERFCOUNTER_STOP
);
376 fd_draw(ctx
->batch
, ring
, DI_PT_RECTLIST
, USE_VISIBILITY
,
377 DI_SRC_SEL_AUTO_INDEX
, 2, 0, INDEX_SIZE_IGN
, 0, 0, NULL
);
381 fd3_draw_init(struct pipe_context
*pctx
)
383 struct fd_context
*ctx
= fd_context(pctx
);
384 ctx
->draw_vbo
= fd3_draw_vbo
;
385 ctx
->clear
= fd3_clear
;