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gallium: change pipe_sampler_view::first_element/last_element -> offset/size
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd3_emit.h"
39 #include "fd3_blend.h"
40 #include "fd3_context.h"
41 #include "fd3_program.h"
42 #include "fd3_rasterizer.h"
43 #include "fd3_texture.h"
44 #include "fd3_format.h"
45 #include "fd3_zsa.h"
46
47 static const enum adreno_state_block sb[] = {
48 [SHADER_VERTEX] = SB_VERT_SHADER,
49 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
50 };
51
52 /* regid: base const register
53 * prsc or dwords: buffer containing constant values
54 * sizedwords: size of const value buffer
55 */
56 void
57 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
58 uint32_t regid, uint32_t offset, uint32_t sizedwords,
59 const uint32_t *dwords, struct pipe_resource *prsc)
60 {
61 uint32_t i, sz;
62 enum adreno_state_src src;
63
64 debug_assert((regid % 4) == 0);
65 debug_assert((sizedwords % 4) == 0);
66
67 if (prsc) {
68 sz = 0;
69 src = SS_INDIRECT;
70 } else {
71 sz = sizedwords;
72 src = SS_DIRECT;
73 }
74
75 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
76 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
77 CP_LOAD_STATE_0_STATE_SRC(src) |
78 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
79 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
80 if (prsc) {
81 struct fd_bo *bo = fd_resource(prsc)->bo;
82 OUT_RELOC(ring, bo, offset,
83 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
84 } else {
85 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
96 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
97 {
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101 debug_assert((num % 4) == 0);
102
103 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num/2));
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
110
111 for (i = 0; i < num; i++) {
112 if (prscs[i]) {
113 if (write) {
114 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
115 } else {
116 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
117 }
118 } else {
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122 }
123
124 #define VERT_TEX_OFF 0
125 #define FRAG_TEX_OFF 16
126 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
127
128 static void
129 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
130 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
131 {
132 static const unsigned tex_off[] = {
133 [SB_VERT_TEX] = VERT_TEX_OFF,
134 [SB_FRAG_TEX] = FRAG_TEX_OFF,
135 };
136 static const enum adreno_state_block mipaddr[] = {
137 [SB_VERT_TEX] = SB_VERT_MIPADDR,
138 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
139 };
140 static const uint32_t bcolor_reg[] = {
141 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
142 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
143 };
144 struct fd3_context *fd3_ctx = fd3_context(ctx);
145 bool needs_border = false;
146 unsigned i, j;
147
148 if (tex->num_samplers > 0) {
149 /* output sampler state: */
150 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
151 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
152 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
153 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
154 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
155 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
156 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
157 for (i = 0; i < tex->num_samplers; i++) {
158 static const struct fd3_sampler_stateobj dummy_sampler = {};
159 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
160 fd3_sampler_stateobj(tex->samplers[i]) :
161 &dummy_sampler;
162
163 OUT_RING(ring, sampler->texsamp0);
164 OUT_RING(ring, sampler->texsamp1);
165
166 needs_border |= sampler->needs_border;
167 }
168 }
169
170 if (tex->num_textures > 0) {
171 /* emit texture state: */
172 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
173 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
174 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
175 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
176 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
177 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
178 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
179 for (i = 0; i < tex->num_textures; i++) {
180 static const struct fd3_pipe_sampler_view dummy_view = {};
181 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
182 fd3_pipe_sampler_view(tex->textures[i]) :
183 &dummy_view;
184 OUT_RING(ring, view->texconst0);
185 OUT_RING(ring, view->texconst1);
186 OUT_RING(ring, view->texconst2 |
187 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
188 OUT_RING(ring, view->texconst3);
189 }
190
191 /* emit mipaddrs: */
192 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
193 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
194 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
195 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
196 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
197 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
198 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
199 for (i = 0; i < tex->num_textures; i++) {
200 static const struct fd3_pipe_sampler_view dummy_view = {
201 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
202 .base.u.tex.first_level = 1,
203 };
204 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
205 fd3_pipe_sampler_view(tex->textures[i]) :
206 &dummy_view;
207 struct fd_resource *rsc = fd_resource(view->base.texture);
208 if (rsc && rsc->base.b.target == PIPE_BUFFER) {
209 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
210 j = 1;
211 } else {
212 unsigned start = fd_sampler_first_level(&view->base);
213 unsigned end = fd_sampler_last_level(&view->base);
214
215 for (j = 0; j < (end - start + 1); j++) {
216 struct fd_resource_slice *slice =
217 fd_resource_slice(rsc, j + start);
218 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
219 }
220 }
221
222 /* pad the remaining entries w/ null: */
223 for (; j < BASETABLE_SZ; j++) {
224 OUT_RING(ring, 0x00000000);
225 }
226 }
227 }
228
229 if (needs_border) {
230 unsigned off;
231 void *ptr;
232
233 u_upload_alloc(fd3_ctx->border_color_uploader,
234 0, BORDER_COLOR_UPLOAD_SIZE,
235 BORDER_COLOR_UPLOAD_SIZE, &off,
236 &fd3_ctx->border_color_buf,
237 &ptr);
238
239 fd_setup_border_colors(tex, ptr, tex_off[sb]);
240
241 OUT_PKT0(ring, bcolor_reg[sb], 1);
242 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
243
244 u_upload_unmap(fd3_ctx->border_color_uploader);
245 }
246 }
247
248 /* emit texture state for mem->gmem restore operation.. eventually it would
249 * be good to get rid of this and use normal CSO/etc state for more of these
250 * special cases, but for now the compiler is not sufficient..
251 *
252 * Also, for using normal state, not quite sure how to handle the special
253 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
254 */
255 void
256 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
257 struct pipe_surface **psurf,
258 int bufs)
259 {
260 int i, j;
261
262 /* output sampler state: */
263 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
264 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
265 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
266 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
267 CP_LOAD_STATE_0_NUM_UNIT(bufs));
268 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
269 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
270 for (i = 0; i < bufs; i++) {
271 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
272 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
273 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
274 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
275 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
276 OUT_RING(ring, 0x00000000);
277 }
278
279 /* emit texture state: */
280 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
281 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
282 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
283 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
284 CP_LOAD_STATE_0_NUM_UNIT(bufs));
285 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
286 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
287 for (i = 0; i < bufs; i++) {
288 if (!psurf[i]) {
289 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
290 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
291 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
292 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
293 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
294 OUT_RING(ring, 0x00000000);
295 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
296 OUT_RING(ring, 0x00000000);
297 continue;
298 }
299
300 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
301 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
302 /* The restore blit_zs shader expects stencil in sampler 0, and depth
303 * in sampler 1
304 */
305 if (rsc->stencil && i == 0) {
306 rsc = rsc->stencil;
307 format = fd3_gmem_restore_format(rsc->base.b.format);
308 }
309
310 /* note: PIPE_BUFFER disallowed for surfaces */
311 unsigned lvl = psurf[i]->u.tex.level;
312 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
313
314 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
315
316 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
317 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
318 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
319 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
320 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
321 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
322 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
323 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
324 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
325 OUT_RING(ring, 0x00000000);
326 }
327
328 /* emit mipaddrs: */
329 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
330 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
331 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
332 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
333 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
334 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
335 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
336 for (i = 0; i < bufs; i++) {
337 if (psurf[i]) {
338 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
339 /* Matches above logic for blit_zs shader */
340 if (rsc->stencil && i == 0)
341 rsc = rsc->stencil;
342 unsigned lvl = psurf[i]->u.tex.level;
343 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
344 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
345 } else {
346 OUT_RING(ring, 0x00000000);
347 }
348
349 /* pad the remaining entries w/ null: */
350 for (j = 1; j < BASETABLE_SZ; j++) {
351 OUT_RING(ring, 0x00000000);
352 }
353 }
354 }
355
356 void
357 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
358 {
359 int32_t i, j, last = -1;
360 uint32_t total_in = 0;
361 const struct fd_vertex_state *vtx = emit->vtx;
362 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
363 unsigned vertex_regid = regid(63, 0);
364 unsigned instance_regid = regid(63, 0);
365 unsigned vtxcnt_regid = regid(63, 0);
366
367 /* Note that sysvals come *after* normal inputs: */
368 for (i = 0; i < vp->inputs_count; i++) {
369 if (!vp->inputs[i].compmask)
370 continue;
371 if (vp->inputs[i].sysval) {
372 switch(vp->inputs[i].slot) {
373 case SYSTEM_VALUE_BASE_VERTEX:
374 /* handled elsewhere */
375 break;
376 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
377 vertex_regid = vp->inputs[i].regid;
378 break;
379 case SYSTEM_VALUE_INSTANCE_ID:
380 instance_regid = vp->inputs[i].regid;
381 break;
382 case SYSTEM_VALUE_VERTEX_CNT:
383 vtxcnt_regid = vp->inputs[i].regid;
384 break;
385 default:
386 unreachable("invalid system value");
387 break;
388 }
389 } else if (i < vtx->vtx->num_elements) {
390 last = i;
391 }
392 }
393
394 for (i = 0, j = 0; i <= last; i++) {
395 assert(!vp->inputs[i].sysval);
396 if (vp->inputs[i].compmask) {
397 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
398 const struct pipe_vertex_buffer *vb =
399 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
400 struct fd_resource *rsc = fd_resource(vb->buffer);
401 enum pipe_format pfmt = elem->src_format;
402 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
403 bool switchnext = (i != last) ||
404 (vertex_regid != regid(63, 0)) ||
405 (instance_regid != regid(63, 0)) ||
406 (vtxcnt_regid != regid(63, 0));
407 bool isint = util_format_is_pure_integer(pfmt);
408 uint32_t fs = util_format_get_blocksize(pfmt);
409
410 debug_assert(fmt != ~0);
411
412 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
413 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
414 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
415 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
416 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
417 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
418 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
419 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
420
421 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
422 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
423 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
424 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
425 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
426 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
427 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
428 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
429 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
430 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
431
432 total_in += vp->inputs[i].ncomp;
433 j++;
434 }
435 }
436
437 /* hw doesn't like to be configured for zero vbo's, it seems: */
438 if (last < 0) {
439 /* just recycle the shader bo, we just need to point to *something*
440 * valid:
441 */
442 struct fd_bo *dummy_vbo = vp->bo;
443 bool switchnext = (vertex_regid != regid(63, 0)) ||
444 (instance_regid != regid(63, 0)) ||
445 (vtxcnt_regid != regid(63, 0));
446
447 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
448 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
449 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
450 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
451 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
452 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
453 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
454
455 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
456 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
457 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
458 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
459 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
460 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
461 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
462 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
463 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
464
465 total_in = 1;
466 j = 1;
467 }
468
469 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
470 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
471 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
472 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
473 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
474 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
475 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
476 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
477
478 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
479 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
480 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
481 }
482
483 void
484 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
485 struct fd3_emit *emit)
486 {
487 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
488 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
489 uint32_t dirty = emit->dirty;
490
491 emit_marker(ring, 5);
492
493 if (dirty & FD_DIRTY_SAMPLE_MASK) {
494 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
495 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
496 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
497 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
498 }
499
500 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
501 !emit->key.binning_pass) {
502 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
503 fd3_blend_stateobj(ctx->blend)->rb_render_control;
504
505 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
506 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
507 A3XX_RB_RENDER_CONTROL_YCOORD |
508 A3XX_RB_RENDER_CONTROL_ZCOORD |
509 A3XX_RB_RENDER_CONTROL_WCOORD);
510
511 /* I suppose if we needed to (which I don't *think* we need
512 * to), we could emit this for binning pass too. But we
513 * would need to keep a different patch-list for binning
514 * vs render pass.
515 */
516
517 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
518 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
519 }
520
521 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
522 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
523 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
524
525 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
526 OUT_RING(ring, zsa->rb_alpha_ref);
527
528 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
529 OUT_RING(ring, zsa->rb_stencil_control);
530
531 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
532 OUT_RING(ring, zsa->rb_stencilrefmask |
533 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
534 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
535 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
536 }
537
538 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
539 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
540 if (fp->writes_pos) {
541 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
542 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
543 }
544 if (fp->has_kill) {
545 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
546 }
547 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
548 OUT_RING(ring, val);
549 }
550
551 if (dirty & FD_DIRTY_RASTERIZER) {
552 struct fd3_rasterizer_stateobj *rasterizer =
553 fd3_rasterizer_stateobj(ctx->rasterizer);
554
555 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
556 OUT_RING(ring, rasterizer->gras_su_mode_control);
557
558 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
559 OUT_RING(ring, rasterizer->gras_su_point_minmax);
560 OUT_RING(ring, rasterizer->gras_su_point_size);
561
562 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
563 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
564 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
565 }
566
567 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
568 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
569 ->gras_cl_clip_cntl;
570 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
571 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
572 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
573 /* TODO only use if prog doesn't use clipvertex/clipdist */
574 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
575 MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
576 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
577 OUT_RING(ring, val);
578 }
579
580 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
581 uint32_t planes = ctx->rasterizer->clip_plane_enable;
582 int count = 0;
583
584 while (planes && count < 6) {
585 int i = ffs(planes) - 1;
586
587 planes &= ~(1U << i);
588 fd_wfi(ctx->batch, ring);
589 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
590 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
591 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
592 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
593 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
594 }
595 }
596
597 /* NOTE: since primitive_restart is not actually part of any
598 * state object, we need to make sure that we always emit
599 * PRIM_VTX_CNTL.. either that or be more clever and detect
600 * when it changes.
601 */
602 if (emit->info) {
603 const struct pipe_draw_info *info = emit->info;
604 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
605 ->pc_prim_vtx_cntl;
606
607 if (!emit->key.binning_pass) {
608 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
609 if (stride_in_vpc > 0)
610 stride_in_vpc = MAX2(stride_in_vpc, 2);
611 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
612 }
613
614 if (info->indexed && info->primitive_restart) {
615 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
616 }
617
618 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
619
620 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
621 OUT_RING(ring, val);
622 }
623
624 if (dirty & FD_DIRTY_SCISSOR) {
625 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
626
627 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
628 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
629 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
630 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
631 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
632
633 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
634 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
635 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
636 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
637 }
638
639 if (dirty & FD_DIRTY_VIEWPORT) {
640 fd_wfi(ctx->batch, ring);
641 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
642 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
643 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
644 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
645 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
646 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
647 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
648 }
649
650 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
651 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
652 int nr_cbufs = pfb->nr_cbufs;
653 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
654 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
655 nr_cbufs++;
656 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
657 }
658
659 /* TODO we should not need this or fd_wfi() before emit_constants():
660 */
661 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
662 OUT_RING(ring, HLSQ_FLUSH);
663
664 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
665 ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
666 if (!emit->key.binning_pass)
667 ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
668 }
669
670 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
671 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
672 uint32_t i;
673
674 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
675 enum pipe_format format =
676 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
677 const struct util_format_description *desc =
678 util_format_description(format);
679 bool is_float = util_format_is_float(format);
680 bool is_int = util_format_is_pure_integer(format);
681 bool has_alpha = util_format_has_alpha(format);
682 uint32_t control = blend->rb_mrt[i].control;
683 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
684
685 if (is_int) {
686 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
687 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
688 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
689 }
690
691 if (format == PIPE_FORMAT_NONE)
692 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
693
694 if (has_alpha) {
695 blend_control |= blend->rb_mrt[i].blend_control_rgb;
696 } else {
697 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
698 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
699 }
700
701 if (format && util_format_get_component_bits(
702 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
703 const struct pipe_rt_blend_state *rt;
704 if (ctx->blend->independent_blend_enable)
705 rt = &ctx->blend->rt[i];
706 else
707 rt = &ctx->blend->rt[0];
708
709 if (!util_format_colormask_full(desc, rt->colormask))
710 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
711 }
712
713 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
714 OUT_RING(ring, control);
715
716 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
717 OUT_RING(ring, blend_control |
718 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
719 }
720 }
721
722 if (dirty & FD_DIRTY_BLEND_COLOR) {
723 struct pipe_blend_color *bcolor = &ctx->blend_color;
724 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
725 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
726 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
727 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
728 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
729 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
730 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
731 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
732 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
733 }
734
735 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
736 fd_wfi(ctx->batch, ring);
737
738 if (dirty & FD_DIRTY_VERTTEX) {
739 if (vp->has_samp)
740 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
741 else
742 dirty &= ~FD_DIRTY_VERTTEX;
743 }
744
745 if (dirty & FD_DIRTY_FRAGTEX) {
746 if (fp->has_samp)
747 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
748 else
749 dirty &= ~FD_DIRTY_FRAGTEX;
750 }
751
752 ctx->dirty &= ~dirty;
753 }
754
755 /* emit setup at begin of new cmdstream buffer (don't rely on previous
756 * state, there could have been a context switch between ioctls):
757 */
758 void
759 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
760 {
761 struct fd_context *ctx = batch->ctx;
762 struct fd3_context *fd3_ctx = fd3_context(ctx);
763 int i;
764
765 if (ctx->screen->gpu_id == 320) {
766 OUT_PKT3(ring, CP_REG_RMW, 3);
767 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
768 OUT_RING(ring, 0xfffcffff);
769 OUT_RING(ring, 0x00000000);
770 }
771
772 fd_wfi(batch, ring);
773 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
774 OUT_RING(ring, 0x00007fff);
775
776 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
777 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
778 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
779 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
780
781 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
782 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
783 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
784 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
785
786 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
787 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
788
789 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
790 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
791 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
792 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
793
794 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
795 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
796 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
797 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
798 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
799
800 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
801 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
802 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
803
804 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
805 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
806
807 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
808 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
809 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
810 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
811
812 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
813 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
814 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
815 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
816
817 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
818 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
819 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
820
821 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
822 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
823
824 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
825 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
826
827 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
828 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
829
830 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
831 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
832
833 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
834 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
835
836 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
837 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
838 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
839 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
840 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
841
842 fd3_emit_cache_flush(batch, ring);
843
844 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
845 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
846
847 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
848 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
849 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
850
851 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
852 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
853
854 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
855 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
856 A3XX_RB_WINDOW_OFFSET_Y(0));
857
858 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
859 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
860 A3XX_RB_BLEND_RED_FLOAT(0.0));
861 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
862 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
863 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
864 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
865 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
866 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
867
868 for (i = 0; i < 6; i++) {
869 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
870 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
871 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
872 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
873 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
874 }
875
876 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
877 OUT_RING(ring, 0x00000000);
878
879 fd_event_write(batch, ring, CACHE_FLUSH);
880
881 if (is_a3xx_p0(ctx->screen)) {
882 OUT_PKT3(ring, CP_DRAW_INDX, 3);
883 OUT_RING(ring, 0x00000000);
884 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
885 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
886 OUT_RING(ring, 0); /* NumIndices */
887 }
888
889 OUT_PKT3(ring, CP_NOP, 4);
890 OUT_RING(ring, 0x00000000);
891 OUT_RING(ring, 0x00000000);
892 OUT_RING(ring, 0x00000000);
893 OUT_RING(ring, 0x00000000);
894
895 fd_wfi(batch, ring);
896
897 fd_hw_query_enable(batch, ring);
898 }
899
900 static void
901 fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
902 {
903 __OUT_IB(ring, true, target);
904 }
905
906 void
907 fd3_emit_init(struct pipe_context *pctx)
908 {
909 struct fd_context *ctx = fd_context(pctx);
910 ctx->emit_const = fd3_emit_const;
911 ctx->emit_const_bo = fd3_emit_const_bo;
912 ctx->emit_ib = fd3_emit_ib;
913 }