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[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_util.h"
44 #include "fd3_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 void
51 fd3_emit_constant(struct fd_ringbuffer *ring,
52 enum adreno_state_block sb,
53 uint32_t regid, uint32_t offset, uint32_t sizedwords,
54 const uint32_t *dwords, struct pipe_resource *prsc)
55 {
56 uint32_t i, sz;
57 enum adreno_state_src src;
58
59 if (prsc) {
60 sz = 0;
61 src = SS_INDIRECT;
62 } else {
63 sz = sizedwords;
64 src = SS_DIRECT;
65 }
66
67 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
68 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
69 CP_LOAD_STATE_0_STATE_SRC(src) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
72 if (prsc) {
73 struct fd_bo *bo = fd_resource(prsc)->bo;
74 OUT_RELOC(ring, bo, offset,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
76 } else {
77 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
79 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
80 }
81 for (i = 0; i < sz; i++) {
82 OUT_RING(ring, dwords[i]);
83 }
84 }
85
86 static void
87 emit_constants(struct fd_ringbuffer *ring,
88 enum adreno_state_block sb,
89 struct fd_constbuf_stateobj *constbuf,
90 struct ir3_shader_variant *shader)
91 {
92 uint32_t enabled_mask = constbuf->enabled_mask;
93 uint32_t first_immediate;
94 uint32_t base = 0;
95
96 /* in particular, with binning shader we may end up with unused
97 * consts, ie. we could end up w/ constlen that is smaller
98 * than first_immediate. In that case truncate the user consts
99 * early to avoid HLSQ lockup caused by writing too many consts
100 */
101 first_immediate = MIN2(shader->first_immediate, shader->constlen);
102
103 /* emit user constants: */
104 while (enabled_mask) {
105 unsigned index = ffs(enabled_mask) - 1;
106 struct pipe_constant_buffer *cb = &constbuf->cb[index];
107 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
108
109 // I expect that size should be a multiple of vec4's:
110 assert(size == align(size, 4));
111
112 /* gallium could leave const buffers bound above what the
113 * current shader uses.. don't let that confuse us.
114 */
115 if (base >= (4 * first_immediate))
116 break;
117
118 if (constbuf->dirty_mask & (1 << index)) {
119 /* and even if the start of the const buffer is before
120 * first_immediate, the end may not be:
121 */
122 size = MIN2(size, (4 * first_immediate) - base);
123 fd3_emit_constant(ring, sb, base,
124 cb->buffer_offset, size,
125 cb->user_buffer, cb->buffer);
126 constbuf->dirty_mask &= ~(1 << index);
127 }
128
129 base += size;
130 enabled_mask &= ~(1 << index);
131 }
132
133 /* emit shader immediates: */
134 if (shader) {
135 int size = shader->immediates_count;
136 base = shader->first_immediate;
137
138 /* truncate size to avoid writing constants that shader
139 * does not use:
140 */
141 size = MIN2(size + base, shader->constlen) - base;
142
143 /* convert out of vec4: */
144 base *= 4;
145 size *= 4;
146
147 if (size > 0) {
148 fd3_emit_constant(ring, sb, base,
149 0, size, shader->immediates[0].val, NULL);
150 }
151 }
152 }
153
154 #define VERT_TEX_OFF 0
155 #define FRAG_TEX_OFF 16
156 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
157
158 static void
159 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
160 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
161 {
162 static const unsigned tex_off[] = {
163 [SB_VERT_TEX] = VERT_TEX_OFF,
164 [SB_FRAG_TEX] = FRAG_TEX_OFF,
165 };
166 static const enum adreno_state_block mipaddr[] = {
167 [SB_VERT_TEX] = SB_VERT_MIPADDR,
168 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
169 };
170 static const uint32_t bcolor_reg[] = {
171 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
172 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
173 };
174 struct fd3_context *fd3_ctx = fd3_context(ctx);
175 unsigned i, j, off;
176 void *ptr;
177
178 u_upload_alloc(fd3_ctx->border_color_uploader,
179 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
180 &fd3_ctx->border_color_buf,
181 &ptr);
182
183 if (tex->num_samplers > 0) {
184 /* output sampler state: */
185 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
186 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
187 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
188 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
189 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
190 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
191 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
192 for (i = 0; i < tex->num_samplers; i++) {
193 static const struct fd3_sampler_stateobj dummy_sampler = {};
194 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
195 fd3_sampler_stateobj(tex->samplers[i]) :
196 &dummy_sampler;
197 uint16_t *bcolor = (uint16_t *)((uint8_t *)ptr +
198 (BORDERCOLOR_SIZE * tex_off[sb]) +
199 (BORDERCOLOR_SIZE * i));
200
201 bcolor[0] = util_float_to_half(sampler->base.border_color.f[2]);
202 bcolor[1] = util_float_to_half(sampler->base.border_color.f[1]);
203 bcolor[2] = util_float_to_half(sampler->base.border_color.f[0]);
204 bcolor[3] = util_float_to_half(sampler->base.border_color.f[3]);
205
206 OUT_RING(ring, sampler->texsamp0);
207 OUT_RING(ring, sampler->texsamp1);
208 }
209 }
210
211 if (tex->num_textures > 0) {
212 /* emit texture state: */
213 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
214 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
215 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
216 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
217 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
218 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
219 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
220 for (i = 0; i < tex->num_textures; i++) {
221 static const struct fd3_pipe_sampler_view dummy_view = {};
222 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
223 fd3_pipe_sampler_view(tex->textures[i]) :
224 &dummy_view;
225 OUT_RING(ring, view->texconst0);
226 OUT_RING(ring, view->texconst1);
227 OUT_RING(ring, view->texconst2 |
228 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
229 OUT_RING(ring, view->texconst3);
230 }
231
232 /* emit mipaddrs: */
233 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
234 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
235 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
236 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
237 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
238 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
239 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
240 for (i = 0; i < tex->num_textures; i++) {
241 static const struct fd3_pipe_sampler_view dummy_view = {
242 .base.u.tex.first_level = 1,
243 };
244 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
245 fd3_pipe_sampler_view(tex->textures[i]) :
246 &dummy_view;
247 struct fd_resource *rsc = view->tex_resource;
248 unsigned start = view->base.u.tex.first_level;
249 unsigned end = view->base.u.tex.last_level;
250
251 for (j = 0; j < (end - start + 1); j++) {
252 struct fd_resource_slice *slice =
253 fd_resource_slice(rsc, j + start);
254 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
255 }
256
257 /* pad the remaining entries w/ null: */
258 for (; j < BASETABLE_SZ; j++) {
259 OUT_RING(ring, 0x00000000);
260 }
261 }
262 }
263
264 OUT_PKT0(ring, bcolor_reg[sb], 1);
265 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
266
267 u_upload_unmap(fd3_ctx->border_color_uploader);
268 }
269
270 /* emit texture state for mem->gmem restore operation.. eventually it would
271 * be good to get rid of this and use normal CSO/etc state for more of these
272 * special cases, but for now the compiler is not sufficient..
273 *
274 * Also, for using normal state, not quite sure how to handle the special
275 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
276 */
277 void
278 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
279 {
280 struct fd_resource *rsc = fd_resource(psurf->texture);
281 unsigned lvl = psurf->u.tex.level;
282 struct fd_resource_slice *slice = &rsc->slices[lvl];
283 uint32_t layer_offset = slice->size0 * psurf->u.tex.first_layer;
284 enum pipe_format format = fd3_gmem_restore_format(psurf->format);
285
286 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
287
288 /* output sampler state: */
289 OUT_PKT3(ring, CP_LOAD_STATE, 4);
290 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
291 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
292 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
293 CP_LOAD_STATE_0_NUM_UNIT(1));
294 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
295 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
296 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
297 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
298 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
299 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
300 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
301 OUT_RING(ring, 0x00000000);
302
303 /* emit texture state: */
304 OUT_PKT3(ring, CP_LOAD_STATE, 6);
305 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
306 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
307 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
308 CP_LOAD_STATE_0_NUM_UNIT(1));
309 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
310 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
311 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
312 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
313 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
314 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
315 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
316 A3XX_TEX_CONST_1_WIDTH(psurf->width) |
317 A3XX_TEX_CONST_1_HEIGHT(psurf->height));
318 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
319 A3XX_TEX_CONST_2_INDX(0));
320 OUT_RING(ring, 0x00000000);
321
322 /* emit mipaddrs: */
323 OUT_PKT3(ring, CP_LOAD_STATE, 3);
324 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
325 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
326 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
327 CP_LOAD_STATE_0_NUM_UNIT(1));
328 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
329 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
330 OUT_RELOC(ring, rsc->bo, layer_offset, 0, 0);
331 }
332
333 void
334 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
335 {
336 uint32_t i, j, last = 0;
337 uint32_t total_in = 0;
338 const struct fd_vertex_state *vtx = emit->vtx;
339 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
340 unsigned n = MIN2(vtx->vtx->num_elements, vp->inputs_count);
341
342 /* hw doesn't like to be configured for zero vbo's, it seems: */
343 if (vtx->vtx->num_elements == 0)
344 return;
345
346 for (i = 0; i < n; i++)
347 if (vp->inputs[i].compmask)
348 last = i;
349
350 for (i = 0, j = 0; i <= last; i++) {
351 if (vp->inputs[i].compmask) {
352 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
353 const struct pipe_vertex_buffer *vb =
354 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
355 struct fd_resource *rsc = fd_resource(vb->buffer);
356 enum pipe_format pfmt = elem->src_format;
357 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
358 bool switchnext = (i != last);
359 bool isint = util_format_is_pure_integer(pfmt);
360 uint32_t fs = util_format_get_blocksize(pfmt);
361
362 debug_assert(fmt != ~0);
363
364 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
365 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
366 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
367 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
368 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
369 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
370 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
371
372 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
373 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
374 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
375 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
376 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
377 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
378 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
379 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
380 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
381 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
382
383 total_in += vp->inputs[i].ncomp;
384 j++;
385 }
386 }
387
388 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
389 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
390 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
391 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
392 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
393 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
394 A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
395 A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
396 }
397
398 void
399 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
400 struct fd3_emit *emit)
401 {
402 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
403 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
404 uint32_t dirty = emit->dirty;
405
406 emit_marker(ring, 5);
407
408 if (dirty & FD_DIRTY_SAMPLE_MASK) {
409 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
410 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
411 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
412 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
413 }
414
415 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
416 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control;
417
418 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
419 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
420 A3XX_RB_RENDER_CONTROL_YCOORD |
421 A3XX_RB_RENDER_CONTROL_ZCOORD |
422 A3XX_RB_RENDER_CONTROL_WCOORD);
423
424 /* I suppose if we needed to (which I don't *think* we need
425 * to), we could emit this for binning pass too. But we
426 * would need to keep a different patch-list for binning
427 * vs render pass.
428 */
429
430 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
431 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
432 }
433
434 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
435 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
436 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
437
438 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
439 OUT_RING(ring, zsa->rb_alpha_ref);
440
441 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
442 OUT_RING(ring, zsa->rb_stencil_control);
443
444 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
445 OUT_RING(ring, zsa->rb_stencilrefmask |
446 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
447 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
448 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
449 }
450
451 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
452 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
453 if (fp->writes_pos) {
454 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
455 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
456 }
457 if (fp->has_kill) {
458 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
459 }
460 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
461 OUT_RING(ring, val);
462 }
463
464 if (dirty & FD_DIRTY_RASTERIZER) {
465 struct fd3_rasterizer_stateobj *rasterizer =
466 fd3_rasterizer_stateobj(ctx->rasterizer);
467
468 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
469 OUT_RING(ring, rasterizer->gras_su_mode_control);
470
471 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
472 OUT_RING(ring, rasterizer->gras_su_point_minmax);
473 OUT_RING(ring, rasterizer->gras_su_point_size);
474
475 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
476 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
477 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
478 }
479
480 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
481 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
482 ->gras_cl_clip_cntl;
483 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
484 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
485 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
486 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
487 OUT_RING(ring, val);
488 }
489
490 /* NOTE: since primitive_restart is not actually part of any
491 * state object, we need to make sure that we always emit
492 * PRIM_VTX_CNTL.. either that or be more clever and detect
493 * when it changes.
494 */
495 if (emit->info) {
496 const struct pipe_draw_info *info = emit->info;
497 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
498 ->pc_prim_vtx_cntl;
499
500 if (!emit->key.binning_pass) {
501 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
502 if (stride_in_vpc > 0)
503 stride_in_vpc = MAX2(stride_in_vpc, 2);
504 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
505 }
506
507 if (info->indexed && info->primitive_restart) {
508 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
509 }
510
511 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
512
513 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
514 OUT_RING(ring, val);
515 }
516
517 if (dirty & FD_DIRTY_SCISSOR) {
518 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
519
520 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
521 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
522 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
523 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
524 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
525
526 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
527 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
528 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
529 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
530 }
531
532 if (dirty & FD_DIRTY_VIEWPORT) {
533 fd_wfi(ctx, ring);
534 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
535 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
536 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
537 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
538 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
539 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
540 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
541 }
542
543 if (dirty & FD_DIRTY_PROG)
544 fd3_program_emit(ring, emit);
545
546 /* TODO we should not need this or fd_wfi() before emit_constants():
547 */
548 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
549 OUT_RING(ring, HLSQ_FLUSH);
550
551 if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
552 /* evil hack to deal sanely with clear path: */
553 (emit->prog == &ctx->prog)) {
554 fd_wfi(ctx, ring);
555 emit_constants(ring, SB_VERT_SHADER,
556 &ctx->constbuf[PIPE_SHADER_VERTEX],
557 (emit->prog->dirty & FD_SHADER_DIRTY_VP) ? vp : NULL);
558 if (!emit->key.binning_pass) {
559 emit_constants(ring, SB_FRAG_SHADER,
560 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
561 (emit->prog->dirty & FD_SHADER_DIRTY_FP) ? fp : NULL);
562 }
563 }
564
565 if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
566 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
567 uint32_t i;
568
569 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
570 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
571 OUT_RING(ring, blend->rb_mrt[i].control);
572
573 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
574 OUT_RING(ring, blend->rb_mrt[i].blend_control);
575 }
576 }
577
578 if (dirty & FD_DIRTY_BLEND_COLOR) {
579 struct pipe_blend_color *bcolor = &ctx->blend_color;
580 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
581 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
582 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
583 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
584 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
585 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
586 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
587 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
588 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
589 }
590
591 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
592 fd_wfi(ctx, ring);
593
594 if (dirty & FD_DIRTY_VERTTEX) {
595 if (vp->has_samp)
596 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
597 else
598 dirty &= ~FD_DIRTY_VERTTEX;
599 }
600
601 if (dirty & FD_DIRTY_FRAGTEX) {
602 if (fp->has_samp)
603 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
604 else
605 dirty &= ~FD_DIRTY_FRAGTEX;
606 }
607
608 ctx->dirty &= ~dirty;
609 }
610
611 /* emit setup at begin of new cmdstream buffer (don't rely on previous
612 * state, there could have been a context switch between ioctls):
613 */
614 void
615 fd3_emit_restore(struct fd_context *ctx)
616 {
617 struct fd3_context *fd3_ctx = fd3_context(ctx);
618 struct fd_ringbuffer *ring = ctx->ring;
619 int i;
620
621 if (ctx->screen->gpu_id == 320) {
622 OUT_PKT3(ring, CP_REG_RMW, 3);
623 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
624 OUT_RING(ring, 0xfffcffff);
625 OUT_RING(ring, 0x00000000);
626 }
627
628 fd_wfi(ctx, ring);
629 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
630 OUT_RING(ring, 0x00007fff);
631
632 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
633 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
634 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
635 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
636
637 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
638 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
639 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
640 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
641
642 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
643 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
644
645 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
646 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
647 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
648 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
649
650 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
651 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
652 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
653 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
654 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
655
656 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
657 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
658 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
659
660 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
661 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
662
663 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
664 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
665 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
666 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
667
668 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
669 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
670 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
671 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
672
673 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
674 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
675 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
676
677 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
678 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
679
680 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
681 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
682
683 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
684 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
685
686 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
687 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
688
689 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
690 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
691
692 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
693 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
694 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
695 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
696 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
697
698 OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
699 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
700 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
701 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
702 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
703
704 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
705 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
706
707 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
708 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
709 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
710
711 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
712 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
713
714 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
715 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
716 A3XX_RB_WINDOW_OFFSET_Y(0));
717
718 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
719 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
720 A3XX_RB_BLEND_RED_FLOAT(0.0));
721 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
722 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
723 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
724 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
725 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
726 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
727
728 for (i = 0; i < 6; i++) {
729 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
730 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
731 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
732 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
733 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
734 }
735
736 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
737 OUT_RING(ring, 0x00000000);
738
739 fd_event_write(ctx, ring, CACHE_FLUSH);
740
741 if (is_a3xx_p0(ctx->screen)) {
742 OUT_PKT3(ring, CP_DRAW_INDX, 3);
743 OUT_RING(ring, 0x00000000);
744 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
745 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
746 OUT_RING(ring, 0); /* NumIndices */
747 }
748
749 OUT_PKT3(ring, CP_NOP, 4);
750 OUT_RING(ring, 0x00000000);
751 OUT_RING(ring, 0x00000000);
752 OUT_RING(ring, 0x00000000);
753 OUT_RING(ring, 0x00000000);
754
755 fd_wfi(ctx, ring);
756
757 ctx->needs_rb_fbd = true;
758 }