1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd3_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
88 for (i
= 0; i
< sz
; i
++) {
89 OUT_RING(ring
, dwords
[i
]);
94 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
95 uint32_t regid
, uint32_t num
, struct fd_bo
**bos
, uint32_t *offsets
)
99 debug_assert((regid
% 4) == 0);
100 debug_assert((num
% 4) == 0);
102 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
103 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num
/2));
107 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 for (i
= 0; i
< num
; i
++) {
113 OUT_RELOCW(ring
, bos
[i
], offsets
[i
], 0, 0);
115 OUT_RELOC(ring
, bos
[i
], offsets
[i
], 0, 0);
118 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
128 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
129 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
131 static const unsigned tex_off
[] = {
132 [SB_VERT_TEX
] = VERT_TEX_OFF
,
133 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
135 static const enum adreno_state_block mipaddr
[] = {
136 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
137 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
139 static const uint32_t bcolor_reg
[] = {
140 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
141 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
143 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
147 u_upload_alloc(fd3_ctx
->border_color_uploader
,
148 0, 2 * PIPE_MAX_SAMPLERS
* BORDERCOLOR_SIZE
, &off
,
149 &fd3_ctx
->border_color_buf
,
152 if (tex
->num_samplers
> 0) {
153 /* output sampler state: */
154 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
155 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
156 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
157 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
158 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
159 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
160 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
161 for (i
= 0; i
< tex
->num_samplers
; i
++) {
162 static const struct fd3_sampler_stateobj dummy_sampler
= {};
163 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
164 fd3_sampler_stateobj(tex
->samplers
[i
]) :
166 uint16_t *bcolor
= (uint16_t *)((uint8_t *)ptr
+
167 (BORDERCOLOR_SIZE
* tex_off
[sb
]) +
168 (BORDERCOLOR_SIZE
* i
));
169 uint32_t *bcolor32
= (uint32_t *)&bcolor
[16];
174 * The border colors need to be swizzled in a particular
175 * format-dependent order. Even though samplers don't know about
176 * formats, we can assume that with a GL state tracker, there's a
177 * 1:1 correspondence between sampler and texture. Take advantage
180 if (i
< tex
->num_textures
&& tex
->textures
[i
]) {
181 const struct util_format_description
*desc
=
182 util_format_description(tex
->textures
[i
]->format
);
183 for (j
= 0; j
< 4; j
++) {
184 if (desc
->swizzle
[j
] >= 4)
187 const struct util_format_channel_description
*chan
=
188 &desc
->channel
[desc
->swizzle
[j
]];
189 int size
= chan
->size
;
191 /* The Z16 texture format we use seems to look in the
192 * 32-bit border color slots
194 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
197 /* Formats like R11G11B10 or RGB9_E5 don't specify
198 * per-channel sizes properly.
200 if (desc
->layout
== UTIL_FORMAT_LAYOUT_OTHER
)
203 if (chan
->pure_integer
&& size
> 16)
204 bcolor32
[desc
->swizzle
[j
] + 4] =
205 sampler
->base
.border_color
.i
[j
];
207 bcolor32
[desc
->swizzle
[j
]] =
208 fui(sampler
->base
.border_color
.f
[j
]);
209 else if (chan
->pure_integer
)
210 bcolor
[desc
->swizzle
[j
] + 8] =
211 sampler
->base
.border_color
.i
[j
];
213 bcolor
[desc
->swizzle
[j
]] =
214 util_float_to_half(sampler
->base
.border_color
.f
[j
]);
218 OUT_RING(ring
, sampler
->texsamp0
);
219 OUT_RING(ring
, sampler
->texsamp1
);
223 if (tex
->num_textures
> 0) {
224 /* emit texture state: */
225 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
226 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
227 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
228 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
229 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
230 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
231 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
232 for (i
= 0; i
< tex
->num_textures
; i
++) {
233 static const struct fd3_pipe_sampler_view dummy_view
= {};
234 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
235 fd3_pipe_sampler_view(tex
->textures
[i
]) :
237 OUT_RING(ring
, view
->texconst0
);
238 OUT_RING(ring
, view
->texconst1
);
239 OUT_RING(ring
, view
->texconst2
|
240 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
241 OUT_RING(ring
, view
->texconst3
);
245 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
246 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
247 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
248 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
249 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
250 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
251 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
252 for (i
= 0; i
< tex
->num_textures
; i
++) {
253 static const struct fd3_pipe_sampler_view dummy_view
= {
254 .base
.target
= PIPE_TEXTURE_1D
, /* anything !PIPE_BUFFER */
255 .base
.u
.tex
.first_level
= 1,
257 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
258 fd3_pipe_sampler_view(tex
->textures
[i
]) :
260 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
261 unsigned start
= fd_sampler_first_level(&view
->base
);
262 unsigned end
= fd_sampler_last_level(&view
->base
);;
264 for (j
= 0; j
< (end
- start
+ 1); j
++) {
265 struct fd_resource_slice
*slice
=
266 fd_resource_slice(rsc
, j
+ start
);
267 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
270 /* pad the remaining entries w/ null: */
271 for (; j
< BASETABLE_SZ
; j
++) {
272 OUT_RING(ring
, 0x00000000);
277 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
278 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
280 u_upload_unmap(fd3_ctx
->border_color_uploader
);
283 /* emit texture state for mem->gmem restore operation.. eventually it would
284 * be good to get rid of this and use normal CSO/etc state for more of these
285 * special cases, but for now the compiler is not sufficient..
287 * Also, for using normal state, not quite sure how to handle the special
288 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
291 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
292 struct pipe_surface
**psurf
,
297 /* output sampler state: */
298 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
299 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
300 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
301 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
302 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
303 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
304 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
305 for (i
= 0; i
< bufs
; i
++) {
306 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
307 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
308 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
309 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
310 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
311 OUT_RING(ring
, 0x00000000);
314 /* emit texture state: */
315 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
316 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
317 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
318 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
319 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
320 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
321 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
322 for (i
= 0; i
< bufs
; i
++) {
324 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
325 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
326 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
327 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
328 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
329 OUT_RING(ring
, 0x00000000);
330 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
331 OUT_RING(ring
, 0x00000000);
335 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
336 enum pipe_format format
= fd3_gmem_restore_format(psurf
[i
]->format
);
337 /* The restore blit_zs shader expects stencil in sampler 0, and depth
340 if (rsc
->stencil
&& i
== 0) {
342 format
= fd3_gmem_restore_format(rsc
->base
.b
.format
);
345 /* note: PIPE_BUFFER disallowed for surfaces */
346 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
347 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
349 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
351 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
352 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
353 fd3_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
354 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
355 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
356 A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
357 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
358 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
359 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
360 OUT_RING(ring
, 0x00000000);
364 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
365 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
366 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
367 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
368 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
369 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
370 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
371 for (i
= 0; i
< bufs
; i
++) {
373 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
374 /* Matches above logic for blit_zs shader */
375 if (rsc
->stencil
&& i
== 0)
377 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
378 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
379 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
381 OUT_RING(ring
, 0x00000000);
384 /* pad the remaining entries w/ null: */
385 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
386 OUT_RING(ring
, 0x00000000);
392 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
394 int32_t i
, j
, last
= -1;
395 uint32_t total_in
= 0;
396 const struct fd_vertex_state
*vtx
= emit
->vtx
;
397 struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
398 unsigned vertex_regid
= regid(63, 0);
399 unsigned instance_regid
= regid(63, 0);
400 unsigned vtxcnt_regid
= regid(63, 0);
402 for (i
= 0; i
< vp
->inputs_count
; i
++) {
403 uint8_t semantic
= sem2name(vp
->inputs
[i
].semantic
);
404 if (semantic
== TGSI_SEMANTIC_VERTEXID_NOBASE
)
405 vertex_regid
= vp
->inputs
[i
].regid
;
406 else if (semantic
== TGSI_SEMANTIC_INSTANCEID
)
407 instance_regid
= vp
->inputs
[i
].regid
;
408 else if (semantic
== IR3_SEMANTIC_VTXCNT
)
409 vtxcnt_regid
= vp
->inputs
[i
].regid
;
410 else if (i
< vtx
->vtx
->num_elements
&& vp
->inputs
[i
].compmask
)
414 /* hw doesn't like to be configured for zero vbo's, it seems: */
415 if ((vtx
->vtx
->num_elements
== 0) &&
416 (vertex_regid
== regid(63, 0)) &&
417 (instance_regid
== regid(63, 0)) &&
418 (vtxcnt_regid
== regid(63, 0)))
421 for (i
= 0, j
= 0; i
<= last
; i
++) {
422 assert(sem2name(vp
->inputs
[i
].semantic
) == 0);
423 if (vp
->inputs
[i
].compmask
) {
424 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
425 const struct pipe_vertex_buffer
*vb
=
426 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
427 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
428 enum pipe_format pfmt
= elem
->src_format
;
429 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
430 bool switchnext
= (i
!= last
) ||
431 (vertex_regid
!= regid(63, 0)) ||
432 (instance_regid
!= regid(63, 0)) ||
433 (vtxcnt_regid
!= regid(63, 0));
434 bool isint
= util_format_is_pure_integer(pfmt
);
435 uint32_t fs
= util_format_get_blocksize(pfmt
);
437 debug_assert(fmt
!= ~0);
439 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
440 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
441 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
442 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
443 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
444 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
445 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
446 OUT_RELOC(ring
, rsc
->bo
, vb
->buffer_offset
+ elem
->src_offset
, 0, 0);
448 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
449 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
450 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
451 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
452 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
453 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
454 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
455 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
456 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
457 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
459 total_in
+= vp
->inputs
[i
].ncomp
;
464 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
465 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
466 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
467 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
468 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
469 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
470 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
471 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
473 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
474 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
475 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
479 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
480 struct fd3_emit
*emit
)
482 struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
483 struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
484 uint32_t dirty
= emit
->dirty
;
486 emit_marker(ring
, 5);
488 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
489 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
490 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
491 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
492 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
495 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) && !emit
->key
.binning_pass
) {
496 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
;
498 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
499 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
500 A3XX_RB_RENDER_CONTROL_YCOORD
|
501 A3XX_RB_RENDER_CONTROL_ZCOORD
|
502 A3XX_RB_RENDER_CONTROL_WCOORD
);
504 /* I suppose if we needed to (which I don't *think* we need
505 * to), we could emit this for binning pass too. But we
506 * would need to keep a different patch-list for binning
510 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
511 OUT_RINGP(ring
, val
, &fd3_context(ctx
)->rbrc_patches
);
514 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
515 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
516 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
518 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
519 OUT_RING(ring
, zsa
->rb_alpha_ref
);
521 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
522 OUT_RING(ring
, zsa
->rb_stencil_control
);
524 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
525 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
526 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
527 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
528 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
531 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
532 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
533 if (fp
->writes_pos
) {
534 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
535 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
538 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
540 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
544 if (dirty
& FD_DIRTY_RASTERIZER
) {
545 struct fd3_rasterizer_stateobj
*rasterizer
=
546 fd3_rasterizer_stateobj(ctx
->rasterizer
);
548 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
549 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
551 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
552 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
553 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
555 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
556 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
557 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
560 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
561 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
563 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
564 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
565 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
566 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
570 /* NOTE: since primitive_restart is not actually part of any
571 * state object, we need to make sure that we always emit
572 * PRIM_VTX_CNTL.. either that or be more clever and detect
576 const struct pipe_draw_info
*info
= emit
->info
;
577 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
580 if (!emit
->key
.binning_pass
) {
581 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
582 if (stride_in_vpc
> 0)
583 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
584 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
587 if (info
->indexed
&& info
->primitive_restart
) {
588 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
591 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
593 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
597 if (dirty
& FD_DIRTY_SCISSOR
) {
598 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
600 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
601 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
602 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
603 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
604 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
606 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
607 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
608 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
609 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
612 if (dirty
& FD_DIRTY_VIEWPORT
) {
614 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
615 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
616 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
617 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
618 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
619 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
620 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
623 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
624 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
625 fd3_program_emit(ring
, emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
628 /* TODO we should not need this or fd_wfi() before emit_constants():
630 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
631 OUT_RING(ring
, HLSQ_FLUSH
);
633 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
634 ir3_emit_consts(vp
, ring
, emit
->info
, dirty
);
635 if (!emit
->key
.binning_pass
)
636 ir3_emit_consts(fp
, ring
, emit
->info
, dirty
);
637 /* mark clean after emitting consts: */
641 if ((dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) && ctx
->blend
) {
642 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
645 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
646 enum pipe_format format
= pipe_surface_format(ctx
->framebuffer
.cbufs
[i
]);
647 const struct util_format_description
*desc
=
648 util_format_description(format
);
649 bool is_float
= util_format_is_float(format
);
650 bool is_int
= util_format_is_pure_integer(format
);
651 bool has_alpha
= util_format_has_alpha(format
);
652 uint32_t control
= blend
->rb_mrt
[i
].control
;
653 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
656 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
657 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
658 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
661 if (format
== PIPE_FORMAT_NONE
)
662 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
665 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
667 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
668 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
671 if (format
&& util_format_get_component_bits(
672 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
673 const struct pipe_rt_blend_state
*rt
;
674 if (ctx
->blend
->independent_blend_enable
)
675 rt
= &ctx
->blend
->rt
[i
];
677 rt
= &ctx
->blend
->rt
[0];
679 if (!util_format_colormask_full(desc
, rt
->colormask
))
680 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
683 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
684 OUT_RING(ring
, control
);
686 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
687 OUT_RING(ring
, blend_control
|
688 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
692 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
693 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
694 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
695 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
696 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
697 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
698 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
699 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
700 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
701 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
702 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
705 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
))
708 if (dirty
& FD_DIRTY_VERTTEX
) {
710 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
712 dirty
&= ~FD_DIRTY_VERTTEX
;
715 if (dirty
& FD_DIRTY_FRAGTEX
) {
717 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
719 dirty
&= ~FD_DIRTY_FRAGTEX
;
722 ctx
->dirty
&= ~dirty
;
725 /* emit setup at begin of new cmdstream buffer (don't rely on previous
726 * state, there could have been a context switch between ioctls):
729 fd3_emit_restore(struct fd_context
*ctx
)
731 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
732 struct fd_ringbuffer
*ring
= ctx
->ring
;
735 if (ctx
->screen
->gpu_id
== 320) {
736 OUT_PKT3(ring
, CP_REG_RMW
, 3);
737 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
738 OUT_RING(ring
, 0xfffcffff);
739 OUT_RING(ring
, 0x00000000);
743 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
744 OUT_RING(ring
, 0x00007fff);
746 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
747 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
748 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
749 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
751 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
752 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
753 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
754 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
756 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
757 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
759 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
760 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
761 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
762 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
764 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
765 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
766 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
767 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
768 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
770 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
771 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
772 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
774 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
775 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
777 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
778 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
779 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
780 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
782 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
783 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
784 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
785 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
787 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
788 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
789 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
791 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
792 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
794 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
795 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
797 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
798 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
800 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
801 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
803 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
804 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
806 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
807 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
808 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
809 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
810 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
812 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
813 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
814 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
815 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
816 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
818 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
819 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
821 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
822 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
823 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
825 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
826 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
828 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
829 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
830 A3XX_RB_WINDOW_OFFSET_Y(0));
832 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
833 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
834 A3XX_RB_BLEND_RED_FLOAT(0.0));
835 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
836 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
837 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
838 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
839 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
840 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
842 for (i
= 0; i
< 6; i
++) {
843 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
844 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
845 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
846 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
847 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
850 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
851 OUT_RING(ring
, 0x00000000);
853 fd_event_write(ctx
, ring
, CACHE_FLUSH
);
855 if (is_a3xx_p0(ctx
->screen
)) {
856 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
857 OUT_RING(ring
, 0x00000000);
858 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
859 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
860 OUT_RING(ring
, 0); /* NumIndices */
863 OUT_PKT3(ring
, CP_NOP
, 4);
864 OUT_RING(ring
, 0x00000000);
865 OUT_RING(ring
, 0x00000000);
866 OUT_RING(ring
, 0x00000000);
867 OUT_RING(ring
, 0x00000000);
871 ctx
->needs_rb_fbd
= true;
875 fd3_emit_init(struct pipe_context
*pctx
)
877 struct fd_context
*ctx
= fd_context(pctx
);
878 ctx
->emit_const
= fd3_emit_const
;
879 ctx
->emit_const_bo
= fd3_emit_const_bo
;