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freedreno/query: add optional enable hook
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd3_emit.h"
39 #include "fd3_blend.h"
40 #include "fd3_context.h"
41 #include "fd3_program.h"
42 #include "fd3_rasterizer.h"
43 #include "fd3_texture.h"
44 #include "fd3_format.h"
45 #include "fd3_zsa.h"
46
47 static const enum adreno_state_block sb[] = {
48 [SHADER_VERTEX] = SB_VERT_SHADER,
49 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
50 };
51
52 /* regid: base const register
53 * prsc or dwords: buffer containing constant values
54 * sizedwords: size of const value buffer
55 */
56 void
57 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
58 uint32_t regid, uint32_t offset, uint32_t sizedwords,
59 const uint32_t *dwords, struct pipe_resource *prsc)
60 {
61 uint32_t i, sz;
62 enum adreno_state_src src;
63
64 debug_assert((regid % 4) == 0);
65 debug_assert((sizedwords % 4) == 0);
66
67 if (prsc) {
68 sz = 0;
69 src = SS_INDIRECT;
70 } else {
71 sz = sizedwords;
72 src = SS_DIRECT;
73 }
74
75 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
76 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
77 CP_LOAD_STATE_0_STATE_SRC(src) |
78 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
79 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
80 if (prsc) {
81 struct fd_bo *bo = fd_resource(prsc)->bo;
82 OUT_RELOC(ring, bo, offset,
83 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
84 } else {
85 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
96 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
97 {
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101 debug_assert((num % 4) == 0);
102
103 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num/2));
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
110
111 for (i = 0; i < num; i++) {
112 if (bos[i]) {
113 if (write) {
114 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
115 } else {
116 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
117 }
118 } else {
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122 }
123
124 #define VERT_TEX_OFF 0
125 #define FRAG_TEX_OFF 16
126 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
127
128 static void
129 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
130 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
131 {
132 static const unsigned tex_off[] = {
133 [SB_VERT_TEX] = VERT_TEX_OFF,
134 [SB_FRAG_TEX] = FRAG_TEX_OFF,
135 };
136 static const enum adreno_state_block mipaddr[] = {
137 [SB_VERT_TEX] = SB_VERT_MIPADDR,
138 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
139 };
140 static const uint32_t bcolor_reg[] = {
141 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
142 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
143 };
144 struct fd3_context *fd3_ctx = fd3_context(ctx);
145 unsigned i, j, off;
146 void *ptr;
147
148 u_upload_alloc(fd3_ctx->border_color_uploader,
149 0, BORDER_COLOR_UPLOAD_SIZE,
150 BORDER_COLOR_UPLOAD_SIZE, &off,
151 &fd3_ctx->border_color_buf,
152 &ptr);
153
154 fd_setup_border_colors(tex, ptr, tex_off[sb]);
155
156 if (tex->num_samplers > 0) {
157 /* output sampler state: */
158 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
159 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
160 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
161 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
162 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
163 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
164 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
165 for (i = 0; i < tex->num_samplers; i++) {
166 static const struct fd3_sampler_stateobj dummy_sampler = {};
167 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
168 fd3_sampler_stateobj(tex->samplers[i]) :
169 &dummy_sampler;
170
171 OUT_RING(ring, sampler->texsamp0);
172 OUT_RING(ring, sampler->texsamp1);
173 }
174 }
175
176 if (tex->num_textures > 0) {
177 /* emit texture state: */
178 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
179 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
180 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
181 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
182 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
183 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
184 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
185 for (i = 0; i < tex->num_textures; i++) {
186 static const struct fd3_pipe_sampler_view dummy_view = {};
187 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
188 fd3_pipe_sampler_view(tex->textures[i]) :
189 &dummy_view;
190 OUT_RING(ring, view->texconst0);
191 OUT_RING(ring, view->texconst1);
192 OUT_RING(ring, view->texconst2 |
193 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
194 OUT_RING(ring, view->texconst3);
195 }
196
197 /* emit mipaddrs: */
198 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
199 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
200 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
201 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
202 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
203 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
204 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
205 for (i = 0; i < tex->num_textures; i++) {
206 static const struct fd3_pipe_sampler_view dummy_view = {
207 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
208 .base.u.tex.first_level = 1,
209 };
210 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
211 fd3_pipe_sampler_view(tex->textures[i]) :
212 &dummy_view;
213 struct fd_resource *rsc = fd_resource(view->base.texture);
214 if (rsc && rsc->base.b.target == PIPE_BUFFER) {
215 OUT_RELOC(ring, rsc->bo, view->base.u.buf.first_element *
216 util_format_get_blocksize(view->base.format), 0, 0);
217 j = 1;
218 } else {
219 unsigned start = fd_sampler_first_level(&view->base);
220 unsigned end = fd_sampler_last_level(&view->base);;
221
222 for (j = 0; j < (end - start + 1); j++) {
223 struct fd_resource_slice *slice =
224 fd_resource_slice(rsc, j + start);
225 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
226 }
227 }
228
229 /* pad the remaining entries w/ null: */
230 for (; j < BASETABLE_SZ; j++) {
231 OUT_RING(ring, 0x00000000);
232 }
233 }
234 }
235
236 OUT_PKT0(ring, bcolor_reg[sb], 1);
237 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
238
239 u_upload_unmap(fd3_ctx->border_color_uploader);
240 }
241
242 /* emit texture state for mem->gmem restore operation.. eventually it would
243 * be good to get rid of this and use normal CSO/etc state for more of these
244 * special cases, but for now the compiler is not sufficient..
245 *
246 * Also, for using normal state, not quite sure how to handle the special
247 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
248 */
249 void
250 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
251 struct pipe_surface **psurf,
252 int bufs)
253 {
254 int i, j;
255
256 /* output sampler state: */
257 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
258 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
259 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
260 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
261 CP_LOAD_STATE_0_NUM_UNIT(bufs));
262 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
263 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
264 for (i = 0; i < bufs; i++) {
265 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
266 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
267 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
268 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
269 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
270 OUT_RING(ring, 0x00000000);
271 }
272
273 /* emit texture state: */
274 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
275 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
276 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
277 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
278 CP_LOAD_STATE_0_NUM_UNIT(bufs));
279 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
280 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
281 for (i = 0; i < bufs; i++) {
282 if (!psurf[i]) {
283 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
284 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
285 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
286 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
287 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
288 OUT_RING(ring, 0x00000000);
289 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
290 OUT_RING(ring, 0x00000000);
291 continue;
292 }
293
294 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
295 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
296 /* The restore blit_zs shader expects stencil in sampler 0, and depth
297 * in sampler 1
298 */
299 if (rsc->stencil && i == 0) {
300 rsc = rsc->stencil;
301 format = fd3_gmem_restore_format(rsc->base.b.format);
302 }
303
304 /* note: PIPE_BUFFER disallowed for surfaces */
305 unsigned lvl = psurf[i]->u.tex.level;
306 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
307
308 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
309
310 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
311 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
312 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
313 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
314 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
315 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
316 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
317 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
318 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
319 OUT_RING(ring, 0x00000000);
320 }
321
322 /* emit mipaddrs: */
323 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
324 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
325 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
326 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
327 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
328 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
329 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
330 for (i = 0; i < bufs; i++) {
331 if (psurf[i]) {
332 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
333 /* Matches above logic for blit_zs shader */
334 if (rsc->stencil && i == 0)
335 rsc = rsc->stencil;
336 unsigned lvl = psurf[i]->u.tex.level;
337 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
338 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
339 } else {
340 OUT_RING(ring, 0x00000000);
341 }
342
343 /* pad the remaining entries w/ null: */
344 for (j = 1; j < BASETABLE_SZ; j++) {
345 OUT_RING(ring, 0x00000000);
346 }
347 }
348 }
349
350 void
351 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
352 {
353 int32_t i, j, last = -1;
354 uint32_t total_in = 0;
355 const struct fd_vertex_state *vtx = emit->vtx;
356 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
357 unsigned vertex_regid = regid(63, 0);
358 unsigned instance_regid = regid(63, 0);
359 unsigned vtxcnt_regid = regid(63, 0);
360
361 /* Note that sysvals come *after* normal inputs: */
362 for (i = 0; i < vp->inputs_count; i++) {
363 if (!vp->inputs[i].compmask)
364 continue;
365 if (vp->inputs[i].sysval) {
366 switch(vp->inputs[i].slot) {
367 case SYSTEM_VALUE_BASE_VERTEX:
368 /* handled elsewhere */
369 break;
370 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
371 vertex_regid = vp->inputs[i].regid;
372 break;
373 case SYSTEM_VALUE_INSTANCE_ID:
374 instance_regid = vp->inputs[i].regid;
375 break;
376 case SYSTEM_VALUE_VERTEX_CNT:
377 vtxcnt_regid = vp->inputs[i].regid;
378 break;
379 default:
380 unreachable("invalid system value");
381 break;
382 }
383 } else if (i < vtx->vtx->num_elements) {
384 last = i;
385 }
386 }
387
388 for (i = 0, j = 0; i <= last; i++) {
389 assert(!vp->inputs[i].sysval);
390 if (vp->inputs[i].compmask) {
391 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
392 const struct pipe_vertex_buffer *vb =
393 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
394 struct fd_resource *rsc = fd_resource(vb->buffer);
395 enum pipe_format pfmt = elem->src_format;
396 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
397 bool switchnext = (i != last) ||
398 (vertex_regid != regid(63, 0)) ||
399 (instance_regid != regid(63, 0)) ||
400 (vtxcnt_regid != regid(63, 0));
401 bool isint = util_format_is_pure_integer(pfmt);
402 uint32_t fs = util_format_get_blocksize(pfmt);
403
404 debug_assert(fmt != ~0);
405
406 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
407 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
408 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
409 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
410 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
411 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
412 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
413 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
414
415 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
416 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
417 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
418 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
419 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
420 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
421 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
422 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
423 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
424 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
425
426 total_in += vp->inputs[i].ncomp;
427 j++;
428 }
429 }
430
431 /* hw doesn't like to be configured for zero vbo's, it seems: */
432 if (last < 0) {
433 /* just recycle the shader bo, we just need to point to *something*
434 * valid:
435 */
436 struct fd_bo *dummy_vbo = vp->bo;
437 bool switchnext = (vertex_regid != regid(63, 0)) ||
438 (instance_regid != regid(63, 0)) ||
439 (vtxcnt_regid != regid(63, 0));
440
441 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
442 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
443 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
444 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
445 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
446 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
447 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
448
449 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
450 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
451 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
452 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
453 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
454 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
455 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
456 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
457 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
458
459 total_in = 1;
460 j = 1;
461 }
462
463 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
464 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
465 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
466 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
467 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
468 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
469 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
470 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
471
472 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
473 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
474 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
475 }
476
477 void
478 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
479 struct fd3_emit *emit)
480 {
481 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
482 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
483 uint32_t dirty = emit->dirty;
484
485 emit_marker(ring, 5);
486
487 if (dirty & FD_DIRTY_SAMPLE_MASK) {
488 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
489 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
490 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
491 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
492 }
493
494 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
495 !emit->key.binning_pass) {
496 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
497 fd3_blend_stateobj(ctx->blend)->rb_render_control;
498
499 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
500 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
501 A3XX_RB_RENDER_CONTROL_YCOORD |
502 A3XX_RB_RENDER_CONTROL_ZCOORD |
503 A3XX_RB_RENDER_CONTROL_WCOORD);
504
505 /* I suppose if we needed to (which I don't *think* we need
506 * to), we could emit this for binning pass too. But we
507 * would need to keep a different patch-list for binning
508 * vs render pass.
509 */
510
511 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
512 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
513 }
514
515 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
516 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
517 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
518
519 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
520 OUT_RING(ring, zsa->rb_alpha_ref);
521
522 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
523 OUT_RING(ring, zsa->rb_stencil_control);
524
525 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
526 OUT_RING(ring, zsa->rb_stencilrefmask |
527 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
528 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
529 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
530 }
531
532 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
533 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
534 if (fp->writes_pos) {
535 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
536 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
537 }
538 if (fp->has_kill) {
539 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
540 }
541 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
542 OUT_RING(ring, val);
543 }
544
545 if (dirty & FD_DIRTY_RASTERIZER) {
546 struct fd3_rasterizer_stateobj *rasterizer =
547 fd3_rasterizer_stateobj(ctx->rasterizer);
548
549 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
550 OUT_RING(ring, rasterizer->gras_su_mode_control);
551
552 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
553 OUT_RING(ring, rasterizer->gras_su_point_minmax);
554 OUT_RING(ring, rasterizer->gras_su_point_size);
555
556 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
557 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
558 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
559 }
560
561 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
562 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
563 ->gras_cl_clip_cntl;
564 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
565 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
566 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
567 /* TODO only use if prog doesn't use clipvertex/clipdist */
568 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
569 MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
570 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
571 OUT_RING(ring, val);
572 }
573
574 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
575 uint32_t planes = ctx->rasterizer->clip_plane_enable;
576 int count = 0;
577
578 while (planes && count < 6) {
579 int i = ffs(planes) - 1;
580
581 planes &= ~(1U << i);
582 fd_wfi(ctx, ring);
583 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
584 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
585 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
586 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
587 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
588 }
589 }
590
591 /* NOTE: since primitive_restart is not actually part of any
592 * state object, we need to make sure that we always emit
593 * PRIM_VTX_CNTL.. either that or be more clever and detect
594 * when it changes.
595 */
596 if (emit->info) {
597 const struct pipe_draw_info *info = emit->info;
598 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
599 ->pc_prim_vtx_cntl;
600
601 if (!emit->key.binning_pass) {
602 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
603 if (stride_in_vpc > 0)
604 stride_in_vpc = MAX2(stride_in_vpc, 2);
605 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
606 }
607
608 if (info->indexed && info->primitive_restart) {
609 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
610 }
611
612 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
613
614 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
615 OUT_RING(ring, val);
616 }
617
618 if (dirty & FD_DIRTY_SCISSOR) {
619 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
620
621 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
622 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
623 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
624 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
625 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
626
627 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
628 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
629 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
630 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
631 }
632
633 if (dirty & FD_DIRTY_VIEWPORT) {
634 fd_wfi(ctx, ring);
635 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
636 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
637 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
638 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
639 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
640 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
641 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
642 }
643
644 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
645 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
646 int nr_cbufs = pfb->nr_cbufs;
647 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
648 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
649 nr_cbufs++;
650 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
651 }
652
653 /* TODO we should not need this or fd_wfi() before emit_constants():
654 */
655 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
656 OUT_RING(ring, HLSQ_FLUSH);
657
658 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
659 ir3_emit_consts(vp, ring, emit->info, dirty);
660 if (!emit->key.binning_pass)
661 ir3_emit_consts(fp, ring, emit->info, dirty);
662 /* mark clean after emitting consts: */
663 ctx->prog.dirty = 0;
664 }
665
666 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
667 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
668 uint32_t i;
669
670 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
671 enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
672 const struct util_format_description *desc =
673 util_format_description(format);
674 bool is_float = util_format_is_float(format);
675 bool is_int = util_format_is_pure_integer(format);
676 bool has_alpha = util_format_has_alpha(format);
677 uint32_t control = blend->rb_mrt[i].control;
678 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
679
680 if (is_int) {
681 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
682 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
683 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
684 }
685
686 if (format == PIPE_FORMAT_NONE)
687 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
688
689 if (has_alpha) {
690 blend_control |= blend->rb_mrt[i].blend_control_rgb;
691 } else {
692 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
693 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
694 }
695
696 if (format && util_format_get_component_bits(
697 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
698 const struct pipe_rt_blend_state *rt;
699 if (ctx->blend->independent_blend_enable)
700 rt = &ctx->blend->rt[i];
701 else
702 rt = &ctx->blend->rt[0];
703
704 if (!util_format_colormask_full(desc, rt->colormask))
705 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
706 }
707
708 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
709 OUT_RING(ring, control);
710
711 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
712 OUT_RING(ring, blend_control |
713 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
714 }
715 }
716
717 if (dirty & FD_DIRTY_BLEND_COLOR) {
718 struct pipe_blend_color *bcolor = &ctx->blend_color;
719 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
720 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
721 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
722 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
723 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
724 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
725 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
726 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
727 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
728 }
729
730 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
731 fd_wfi(ctx, ring);
732
733 if (dirty & FD_DIRTY_VERTTEX) {
734 if (vp->has_samp)
735 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
736 else
737 dirty &= ~FD_DIRTY_VERTTEX;
738 }
739
740 if (dirty & FD_DIRTY_FRAGTEX) {
741 if (fp->has_samp)
742 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
743 else
744 dirty &= ~FD_DIRTY_FRAGTEX;
745 }
746
747 ctx->dirty &= ~dirty;
748 }
749
750 /* emit setup at begin of new cmdstream buffer (don't rely on previous
751 * state, there could have been a context switch between ioctls):
752 */
753 void
754 fd3_emit_restore(struct fd_context *ctx)
755 {
756 struct fd3_context *fd3_ctx = fd3_context(ctx);
757 struct fd_ringbuffer *ring = ctx->ring;
758 int i;
759
760 if (ctx->screen->gpu_id == 320) {
761 OUT_PKT3(ring, CP_REG_RMW, 3);
762 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
763 OUT_RING(ring, 0xfffcffff);
764 OUT_RING(ring, 0x00000000);
765 }
766
767 fd_wfi(ctx, ring);
768 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
769 OUT_RING(ring, 0x00007fff);
770
771 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
772 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
773 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
774 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
775
776 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
777 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
778 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
779 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
780
781 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
782 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
783
784 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
785 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
786 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
787 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
788
789 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
790 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
791 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
792 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
793 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
794
795 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
796 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
797 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
798
799 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
800 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
801
802 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
803 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
804 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
805 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
806
807 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
808 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
809 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
810 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
811
812 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
813 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
814 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
815
816 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
817 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
818
819 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
820 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
821
822 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
823 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
824
825 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
826 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
827
828 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
829 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
830
831 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
832 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
833 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
834 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
835 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
836
837 fd3_emit_cache_flush(ctx, ring);
838
839 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
840 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
841
842 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
843 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
844 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
845
846 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
847 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
848
849 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
850 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
851 A3XX_RB_WINDOW_OFFSET_Y(0));
852
853 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
854 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
855 A3XX_RB_BLEND_RED_FLOAT(0.0));
856 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
857 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
858 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
859 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
860 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
861 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
862
863 for (i = 0; i < 6; i++) {
864 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
865 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
866 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
867 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
868 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
869 }
870
871 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
872 OUT_RING(ring, 0x00000000);
873
874 fd_event_write(ctx, ring, CACHE_FLUSH);
875
876 if (is_a3xx_p0(ctx->screen)) {
877 OUT_PKT3(ring, CP_DRAW_INDX, 3);
878 OUT_RING(ring, 0x00000000);
879 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
880 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
881 OUT_RING(ring, 0); /* NumIndices */
882 }
883
884 OUT_PKT3(ring, CP_NOP, 4);
885 OUT_RING(ring, 0x00000000);
886 OUT_RING(ring, 0x00000000);
887 OUT_RING(ring, 0x00000000);
888 OUT_RING(ring, 0x00000000);
889
890 fd_wfi(ctx, ring);
891
892 fd_hw_query_enable(ctx, ring);
893
894 ctx->needs_rb_fbd = true;
895 }
896
897 static void
898 fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
899 struct fd_ringmarker *end)
900 {
901 __OUT_IB(ring, true, start, end);
902 }
903
904 void
905 fd3_emit_init(struct pipe_context *pctx)
906 {
907 struct fd_context *ctx = fd_context(pctx);
908 ctx->emit_const = fd3_emit_const;
909 ctx->emit_const_bo = fd3_emit_const_bo;
910 ctx->emit_ib = fd3_emit_ib;
911 }