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freedreno: remove unnecessary null checks
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = SS_INDIRECT;
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/2));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
126
127 static void
128 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
129 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
130 {
131 static const unsigned tex_off[] = {
132 [SB_VERT_TEX] = VERT_TEX_OFF,
133 [SB_FRAG_TEX] = FRAG_TEX_OFF,
134 };
135 static const enum adreno_state_block mipaddr[] = {
136 [SB_VERT_TEX] = SB_VERT_MIPADDR,
137 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
138 };
139 static const uint32_t bcolor_reg[] = {
140 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
141 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
142 };
143 struct fd3_context *fd3_ctx = fd3_context(ctx);
144 unsigned i, j, off;
145 void *ptr;
146
147 u_upload_alloc(fd3_ctx->border_color_uploader,
148 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
149 &fd3_ctx->border_color_buf,
150 &ptr);
151
152 fd_setup_border_colors(tex, ptr, tex_off[sb]);
153
154 if (tex->num_samplers > 0) {
155 /* output sampler state: */
156 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
158 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
159 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
160 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
161 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
162 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
163 for (i = 0; i < tex->num_samplers; i++) {
164 static const struct fd3_sampler_stateobj dummy_sampler = {};
165 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
166 fd3_sampler_stateobj(tex->samplers[i]) :
167 &dummy_sampler;
168
169 OUT_RING(ring, sampler->texsamp0);
170 OUT_RING(ring, sampler->texsamp1);
171 }
172 }
173
174 if (tex->num_textures > 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
177 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
181 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i = 0; i < tex->num_textures; i++) {
184 static const struct fd3_pipe_sampler_view dummy_view = {};
185 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
186 fd3_pipe_sampler_view(tex->textures[i]) :
187 &dummy_view;
188 OUT_RING(ring, view->texconst0);
189 OUT_RING(ring, view->texconst1);
190 OUT_RING(ring, view->texconst2 |
191 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
192 OUT_RING(ring, view->texconst3);
193 }
194
195 /* emit mipaddrs: */
196 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
197 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
198 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
199 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
200 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
201 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
202 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
203 for (i = 0; i < tex->num_textures; i++) {
204 static const struct fd3_pipe_sampler_view dummy_view = {
205 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
206 .base.u.tex.first_level = 1,
207 };
208 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
209 fd3_pipe_sampler_view(tex->textures[i]) :
210 &dummy_view;
211 struct fd_resource *rsc = fd_resource(view->base.texture);
212 unsigned start = fd_sampler_first_level(&view->base);
213 unsigned end = fd_sampler_last_level(&view->base);;
214
215 for (j = 0; j < (end - start + 1); j++) {
216 struct fd_resource_slice *slice =
217 fd_resource_slice(rsc, j + start);
218 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
219 }
220
221 /* pad the remaining entries w/ null: */
222 for (; j < BASETABLE_SZ; j++) {
223 OUT_RING(ring, 0x00000000);
224 }
225 }
226 }
227
228 OUT_PKT0(ring, bcolor_reg[sb], 1);
229 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
230
231 u_upload_unmap(fd3_ctx->border_color_uploader);
232 }
233
234 /* emit texture state for mem->gmem restore operation.. eventually it would
235 * be good to get rid of this and use normal CSO/etc state for more of these
236 * special cases, but for now the compiler is not sufficient..
237 *
238 * Also, for using normal state, not quite sure how to handle the special
239 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
240 */
241 void
242 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
243 struct pipe_surface **psurf,
244 int bufs)
245 {
246 int i, j;
247
248 /* output sampler state: */
249 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
250 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
251 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
252 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
253 CP_LOAD_STATE_0_NUM_UNIT(bufs));
254 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
255 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
256 for (i = 0; i < bufs; i++) {
257 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
258 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
259 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
260 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
261 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
262 OUT_RING(ring, 0x00000000);
263 }
264
265 /* emit texture state: */
266 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
267 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
268 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
269 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
270 CP_LOAD_STATE_0_NUM_UNIT(bufs));
271 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
272 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
273 for (i = 0; i < bufs; i++) {
274 if (!psurf[i]) {
275 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
276 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
277 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
278 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
279 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
280 OUT_RING(ring, 0x00000000);
281 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
282 OUT_RING(ring, 0x00000000);
283 continue;
284 }
285
286 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
287 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
288 /* The restore blit_zs shader expects stencil in sampler 0, and depth
289 * in sampler 1
290 */
291 if (rsc->stencil && i == 0) {
292 rsc = rsc->stencil;
293 format = fd3_gmem_restore_format(rsc->base.b.format);
294 }
295
296 /* note: PIPE_BUFFER disallowed for surfaces */
297 unsigned lvl = psurf[i]->u.tex.level;
298 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
299
300 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
301
302 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
303 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
304 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
305 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
306 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
307 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
308 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
309 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
310 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
311 OUT_RING(ring, 0x00000000);
312 }
313
314 /* emit mipaddrs: */
315 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
316 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
317 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
318 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
319 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
320 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
321 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
322 for (i = 0; i < bufs; i++) {
323 if (psurf[i]) {
324 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
325 /* Matches above logic for blit_zs shader */
326 if (rsc->stencil && i == 0)
327 rsc = rsc->stencil;
328 unsigned lvl = psurf[i]->u.tex.level;
329 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
330 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
331 } else {
332 OUT_RING(ring, 0x00000000);
333 }
334
335 /* pad the remaining entries w/ null: */
336 for (j = 1; j < BASETABLE_SZ; j++) {
337 OUT_RING(ring, 0x00000000);
338 }
339 }
340 }
341
342 void
343 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
344 {
345 int32_t i, j, last = -1;
346 uint32_t total_in = 0;
347 const struct fd_vertex_state *vtx = emit->vtx;
348 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
349 unsigned vertex_regid = regid(63, 0);
350 unsigned instance_regid = regid(63, 0);
351 unsigned vtxcnt_regid = regid(63, 0);
352
353 for (i = 0; i < vp->inputs_count; i++) {
354 if (vp->inputs[i].sysval) {
355 switch(vp->inputs[i].slot) {
356 case SYSTEM_VALUE_BASE_VERTEX:
357 /* handled elsewhere */
358 break;
359 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
360 vertex_regid = vp->inputs[i].regid;
361 break;
362 case SYSTEM_VALUE_INSTANCE_ID:
363 instance_regid = vp->inputs[i].regid;
364 break;
365 case SYSTEM_VALUE_VERTEX_CNT:
366 vtxcnt_regid = vp->inputs[i].regid;
367 break;
368 default:
369 unreachable("invalid system value");
370 break;
371 }
372 } else if (i < vtx->vtx->num_elements && vp->inputs[i].compmask) {
373 last = i;
374 }
375 }
376
377 /* hw doesn't like to be configured for zero vbo's, it seems: */
378 if ((vtx->vtx->num_elements == 0) &&
379 (vertex_regid == regid(63, 0)) &&
380 (instance_regid == regid(63, 0)) &&
381 (vtxcnt_regid == regid(63, 0)))
382 return;
383
384 for (i = 0, j = 0; i <= last; i++) {
385 assert(!vp->inputs[i].sysval);
386 if (vp->inputs[i].compmask) {
387 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
388 const struct pipe_vertex_buffer *vb =
389 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
390 struct fd_resource *rsc = fd_resource(vb->buffer);
391 enum pipe_format pfmt = elem->src_format;
392 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
393 bool switchnext = (i != last) ||
394 (vertex_regid != regid(63, 0)) ||
395 (instance_regid != regid(63, 0)) ||
396 (vtxcnt_regid != regid(63, 0));
397 bool isint = util_format_is_pure_integer(pfmt);
398 uint32_t fs = util_format_get_blocksize(pfmt);
399
400 debug_assert(fmt != ~0);
401
402 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
403 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
404 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
405 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
406 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
407 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
408 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
409 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
410
411 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
412 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
413 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
414 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
415 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
416 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
417 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
418 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
419 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
420 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
421
422 total_in += vp->inputs[i].ncomp;
423 j++;
424 }
425 }
426
427 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
428 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
429 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
430 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
431 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
432 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
433 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
434 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
435
436 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
437 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
438 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
439 }
440
441 void
442 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
443 struct fd3_emit *emit)
444 {
445 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
446 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
447 uint32_t dirty = emit->dirty;
448
449 emit_marker(ring, 5);
450
451 if (dirty & FD_DIRTY_SAMPLE_MASK) {
452 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
453 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
454 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
455 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
456 }
457
458 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
459 !emit->key.binning_pass) {
460 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
461 fd3_blend_stateobj(ctx->blend)->rb_render_control;
462
463 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
464 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
465 A3XX_RB_RENDER_CONTROL_YCOORD |
466 A3XX_RB_RENDER_CONTROL_ZCOORD |
467 A3XX_RB_RENDER_CONTROL_WCOORD);
468
469 /* I suppose if we needed to (which I don't *think* we need
470 * to), we could emit this for binning pass too. But we
471 * would need to keep a different patch-list for binning
472 * vs render pass.
473 */
474
475 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
476 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
477 }
478
479 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
480 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
481 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
482
483 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
484 OUT_RING(ring, zsa->rb_alpha_ref);
485
486 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
487 OUT_RING(ring, zsa->rb_stencil_control);
488
489 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
490 OUT_RING(ring, zsa->rb_stencilrefmask |
491 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
492 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
493 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
494 }
495
496 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
497 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
498 if (fp->writes_pos) {
499 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
500 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
501 }
502 if (fp->has_kill) {
503 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
504 }
505 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
506 OUT_RING(ring, val);
507 }
508
509 if (dirty & FD_DIRTY_RASTERIZER) {
510 struct fd3_rasterizer_stateobj *rasterizer =
511 fd3_rasterizer_stateobj(ctx->rasterizer);
512
513 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
514 OUT_RING(ring, rasterizer->gras_su_mode_control);
515
516 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
517 OUT_RING(ring, rasterizer->gras_su_point_minmax);
518 OUT_RING(ring, rasterizer->gras_su_point_size);
519
520 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
521 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
522 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
523 }
524
525 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
526 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
527 ->gras_cl_clip_cntl;
528 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
529 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
530 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
531 /* TODO only use if prog doesn't use clipvertex/clipdist */
532 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
533 MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
534 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
535 OUT_RING(ring, val);
536 }
537
538 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
539 uint32_t planes = ctx->rasterizer->clip_plane_enable;
540 int count = 0;
541
542 while (planes && count < 6) {
543 int i = ffs(planes) - 1;
544
545 planes &= ~(1U << i);
546 fd_wfi(ctx, ring);
547 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
548 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
549 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
550 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
551 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
552 }
553 }
554
555 /* NOTE: since primitive_restart is not actually part of any
556 * state object, we need to make sure that we always emit
557 * PRIM_VTX_CNTL.. either that or be more clever and detect
558 * when it changes.
559 */
560 if (emit->info) {
561 const struct pipe_draw_info *info = emit->info;
562 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
563 ->pc_prim_vtx_cntl;
564
565 if (!emit->key.binning_pass) {
566 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
567 if (stride_in_vpc > 0)
568 stride_in_vpc = MAX2(stride_in_vpc, 2);
569 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
570 }
571
572 if (info->indexed && info->primitive_restart) {
573 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
574 }
575
576 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
577
578 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
579 OUT_RING(ring, val);
580 }
581
582 if (dirty & FD_DIRTY_SCISSOR) {
583 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
584
585 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
586 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
587 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
588 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
589 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
590
591 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
592 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
593 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
594 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
595 }
596
597 if (dirty & FD_DIRTY_VIEWPORT) {
598 fd_wfi(ctx, ring);
599 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
600 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
601 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
602 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
603 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
604 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
605 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
606 }
607
608 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
609 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
610 int nr_cbufs = pfb->nr_cbufs;
611 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
612 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
613 nr_cbufs++;
614 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
615 }
616
617 /* TODO we should not need this or fd_wfi() before emit_constants():
618 */
619 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
620 OUT_RING(ring, HLSQ_FLUSH);
621
622 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
623 ir3_emit_consts(vp, ring, emit->info, dirty);
624 if (!emit->key.binning_pass)
625 ir3_emit_consts(fp, ring, emit->info, dirty);
626 /* mark clean after emitting consts: */
627 ctx->prog.dirty = 0;
628 }
629
630 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
631 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
632 uint32_t i;
633
634 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
635 enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
636 const struct util_format_description *desc =
637 util_format_description(format);
638 bool is_float = util_format_is_float(format);
639 bool is_int = util_format_is_pure_integer(format);
640 bool has_alpha = util_format_has_alpha(format);
641 uint32_t control = blend->rb_mrt[i].control;
642 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
643
644 if (is_int) {
645 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
646 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
647 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
648 }
649
650 if (format == PIPE_FORMAT_NONE)
651 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
652
653 if (has_alpha) {
654 blend_control |= blend->rb_mrt[i].blend_control_rgb;
655 } else {
656 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
657 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
658 }
659
660 if (format && util_format_get_component_bits(
661 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
662 const struct pipe_rt_blend_state *rt;
663 if (ctx->blend->independent_blend_enable)
664 rt = &ctx->blend->rt[i];
665 else
666 rt = &ctx->blend->rt[0];
667
668 if (!util_format_colormask_full(desc, rt->colormask))
669 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
670 }
671
672 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
673 OUT_RING(ring, control);
674
675 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
676 OUT_RING(ring, blend_control |
677 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
678 }
679 }
680
681 if (dirty & FD_DIRTY_BLEND_COLOR) {
682 struct pipe_blend_color *bcolor = &ctx->blend_color;
683 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
684 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
685 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
686 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
687 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
688 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
689 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
690 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
691 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
692 }
693
694 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
695 fd_wfi(ctx, ring);
696
697 if (dirty & FD_DIRTY_VERTTEX) {
698 if (vp->has_samp)
699 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
700 else
701 dirty &= ~FD_DIRTY_VERTTEX;
702 }
703
704 if (dirty & FD_DIRTY_FRAGTEX) {
705 if (fp->has_samp)
706 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
707 else
708 dirty &= ~FD_DIRTY_FRAGTEX;
709 }
710
711 ctx->dirty &= ~dirty;
712 }
713
714 /* emit setup at begin of new cmdstream buffer (don't rely on previous
715 * state, there could have been a context switch between ioctls):
716 */
717 void
718 fd3_emit_restore(struct fd_context *ctx)
719 {
720 struct fd3_context *fd3_ctx = fd3_context(ctx);
721 struct fd_ringbuffer *ring = ctx->ring;
722 int i;
723
724 if (ctx->screen->gpu_id == 320) {
725 OUT_PKT3(ring, CP_REG_RMW, 3);
726 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
727 OUT_RING(ring, 0xfffcffff);
728 OUT_RING(ring, 0x00000000);
729 }
730
731 fd_wfi(ctx, ring);
732 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
733 OUT_RING(ring, 0x00007fff);
734
735 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
736 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
737 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
738 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
739
740 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
741 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
742 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
743 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
744
745 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
746 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
747
748 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
749 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
750 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
751 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
752
753 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
754 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
755 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
756 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
757 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
758
759 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
760 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
761 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
762
763 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
764 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
765
766 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
767 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
768 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
769 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
770
771 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
772 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
773 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
774 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
775
776 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
777 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
778 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
779
780 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
781 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
782
783 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
784 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
785
786 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
787 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
788
789 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
790 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
791
792 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
793 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
794
795 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
796 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
797 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
798 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
799 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
800
801 fd3_emit_cache_flush(ctx, ring);
802
803 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
804 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
805
806 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
807 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
808 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
809
810 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
811 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
812
813 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
814 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
815 A3XX_RB_WINDOW_OFFSET_Y(0));
816
817 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
818 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
819 A3XX_RB_BLEND_RED_FLOAT(0.0));
820 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
821 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
822 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
823 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
824 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
825 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
826
827 for (i = 0; i < 6; i++) {
828 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
829 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
830 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
831 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
832 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
833 }
834
835 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
836 OUT_RING(ring, 0x00000000);
837
838 fd_event_write(ctx, ring, CACHE_FLUSH);
839
840 if (is_a3xx_p0(ctx->screen)) {
841 OUT_PKT3(ring, CP_DRAW_INDX, 3);
842 OUT_RING(ring, 0x00000000);
843 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
844 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
845 OUT_RING(ring, 0); /* NumIndices */
846 }
847
848 OUT_PKT3(ring, CP_NOP, 4);
849 OUT_RING(ring, 0x00000000);
850 OUT_RING(ring, 0x00000000);
851 OUT_RING(ring, 0x00000000);
852 OUT_RING(ring, 0x00000000);
853
854 fd_wfi(ctx, ring);
855
856 ctx->needs_rb_fbd = true;
857 }
858
859 void
860 fd3_emit_init(struct pipe_context *pctx)
861 {
862 struct fd_context *ctx = fd_context(pctx);
863 ctx->emit_const = fd3_emit_const;
864 ctx->emit_const_bo = fd3_emit_const_bo;
865 }