1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34 #include "util/u_viewport.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
40 #include "fd3_blend.h"
41 #include "fd3_context.h"
42 #include "fd3_program.h"
43 #include "fd3_rasterizer.h"
44 #include "fd3_texture.h"
45 #include "fd3_format.h"
48 static const enum adreno_state_block sb
[] = {
49 [SHADER_VERTEX
] = SB_VERT_SHADER
,
50 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
58 fd3_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
59 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
60 const uint32_t *dwords
, struct pipe_resource
*prsc
)
63 enum adreno_state_src src
;
65 debug_assert((regid
% 4) == 0);
66 debug_assert((sizedwords
% 4) == 0);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
97 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
101 debug_assert((regid
% 4) == 0);
102 debug_assert((num
% 4) == 0);
104 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
105 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
108 CP_LOAD_STATE_0_NUM_UNIT(num
/2));
109 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
112 for (i
= 0; i
< num
; i
++) {
115 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
117 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
120 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
125 #define VERT_TEX_OFF 0
126 #define FRAG_TEX_OFF 16
127 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
130 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
131 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
133 static const unsigned tex_off
[] = {
134 [SB_VERT_TEX
] = VERT_TEX_OFF
,
135 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
137 static const enum adreno_state_block mipaddr
[] = {
138 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
139 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
141 static const uint32_t bcolor_reg
[] = {
142 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
143 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
145 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
146 bool needs_border
= false;
149 if (tex
->num_samplers
> 0) {
150 /* output sampler state: */
151 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
152 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
153 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
154 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
155 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
156 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
157 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
158 for (i
= 0; i
< tex
->num_samplers
; i
++) {
159 static const struct fd3_sampler_stateobj dummy_sampler
= {};
160 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
161 fd3_sampler_stateobj(tex
->samplers
[i
]) :
164 OUT_RING(ring
, sampler
->texsamp0
);
165 OUT_RING(ring
, sampler
->texsamp1
);
167 needs_border
|= sampler
->needs_border
;
171 if (tex
->num_textures
> 0) {
172 /* emit texture state: */
173 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
174 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
175 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
176 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
177 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
178 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
179 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
180 for (i
= 0; i
< tex
->num_textures
; i
++) {
181 static const struct fd3_pipe_sampler_view dummy_view
= {};
182 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
183 fd3_pipe_sampler_view(tex
->textures
[i
]) :
185 OUT_RING(ring
, view
->texconst0
);
186 OUT_RING(ring
, view
->texconst1
);
187 OUT_RING(ring
, view
->texconst2
|
188 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
189 OUT_RING(ring
, view
->texconst3
);
193 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
194 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
195 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
196 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
197 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
198 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
199 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
200 for (i
= 0; i
< tex
->num_textures
; i
++) {
201 static const struct fd3_pipe_sampler_view dummy_view
= {
202 .base
.target
= PIPE_TEXTURE_1D
, /* anything !PIPE_BUFFER */
203 .base
.u
.tex
.first_level
= 1,
205 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
206 fd3_pipe_sampler_view(tex
->textures
[i
]) :
208 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
209 if (rsc
&& rsc
->base
.b
.target
== PIPE_BUFFER
) {
210 OUT_RELOC(ring
, rsc
->bo
, view
->base
.u
.buf
.offset
, 0, 0);
213 unsigned start
= fd_sampler_first_level(&view
->base
);
214 unsigned end
= fd_sampler_last_level(&view
->base
);
216 for (j
= 0; j
< (end
- start
+ 1); j
++) {
217 struct fd_resource_slice
*slice
=
218 fd_resource_slice(rsc
, j
+ start
);
219 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
223 /* pad the remaining entries w/ null: */
224 for (; j
< BASETABLE_SZ
; j
++) {
225 OUT_RING(ring
, 0x00000000);
234 u_upload_alloc(fd3_ctx
->border_color_uploader
,
235 0, BORDER_COLOR_UPLOAD_SIZE
,
236 BORDER_COLOR_UPLOAD_SIZE
, &off
,
237 &fd3_ctx
->border_color_buf
,
240 fd_setup_border_colors(tex
, ptr
, tex_off
[sb
]);
242 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
243 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
245 u_upload_unmap(fd3_ctx
->border_color_uploader
);
249 /* emit texture state for mem->gmem restore operation.. eventually it would
250 * be good to get rid of this and use normal CSO/etc state for more of these
251 * special cases, but for now the compiler is not sufficient..
253 * Also, for using normal state, not quite sure how to handle the special
254 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
257 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
258 struct pipe_surface
**psurf
,
263 /* output sampler state: */
264 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
265 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
266 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
267 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
268 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
269 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
270 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
271 for (i
= 0; i
< bufs
; i
++) {
272 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
273 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
274 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
275 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
276 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
277 OUT_RING(ring
, 0x00000000);
280 /* emit texture state: */
281 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
282 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
283 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
284 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
285 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
286 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
287 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
288 for (i
= 0; i
< bufs
; i
++) {
290 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
291 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
292 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
293 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
294 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
295 OUT_RING(ring
, 0x00000000);
296 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
297 OUT_RING(ring
, 0x00000000);
301 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
302 enum pipe_format format
= fd_gmem_restore_format(psurf
[i
]->format
);
303 /* The restore blit_zs shader expects stencil in sampler 0, and depth
306 if (rsc
->stencil
&& i
== 0) {
308 format
= fd_gmem_restore_format(rsc
->base
.b
.format
);
311 /* note: PIPE_BUFFER disallowed for surfaces */
312 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
313 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
315 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
317 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
318 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
319 fd3_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
320 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
321 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
322 A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
323 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
324 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
325 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
326 OUT_RING(ring
, 0x00000000);
330 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
331 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
332 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
333 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
334 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
335 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
336 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
337 for (i
= 0; i
< bufs
; i
++) {
339 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
340 /* Matches above logic for blit_zs shader */
341 if (rsc
->stencil
&& i
== 0)
343 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
344 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
345 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
347 OUT_RING(ring
, 0x00000000);
350 /* pad the remaining entries w/ null: */
351 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
352 OUT_RING(ring
, 0x00000000);
358 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
360 int32_t i
, j
, last
= -1;
361 uint32_t total_in
= 0;
362 const struct fd_vertex_state
*vtx
= emit
->vtx
;
363 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
364 unsigned vertex_regid
= regid(63, 0);
365 unsigned instance_regid
= regid(63, 0);
366 unsigned vtxcnt_regid
= regid(63, 0);
368 /* Note that sysvals come *after* normal inputs: */
369 for (i
= 0; i
< vp
->inputs_count
; i
++) {
370 if (!vp
->inputs
[i
].compmask
)
372 if (vp
->inputs
[i
].sysval
) {
373 switch(vp
->inputs
[i
].slot
) {
374 case SYSTEM_VALUE_BASE_VERTEX
:
375 /* handled elsewhere */
377 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
378 vertex_regid
= vp
->inputs
[i
].regid
;
380 case SYSTEM_VALUE_INSTANCE_ID
:
381 instance_regid
= vp
->inputs
[i
].regid
;
383 case SYSTEM_VALUE_VERTEX_CNT
:
384 vtxcnt_regid
= vp
->inputs
[i
].regid
;
387 unreachable("invalid system value");
390 } else if (i
< vtx
->vtx
->num_elements
) {
395 for (i
= 0, j
= 0; i
<= last
; i
++) {
396 assert(!vp
->inputs
[i
].sysval
);
397 if (vp
->inputs
[i
].compmask
) {
398 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
399 const struct pipe_vertex_buffer
*vb
=
400 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
401 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
402 enum pipe_format pfmt
= elem
->src_format
;
403 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
404 bool switchnext
= (i
!= last
) ||
405 (vertex_regid
!= regid(63, 0)) ||
406 (instance_regid
!= regid(63, 0)) ||
407 (vtxcnt_regid
!= regid(63, 0));
408 bool isint
= util_format_is_pure_integer(pfmt
);
409 uint32_t fs
= util_format_get_blocksize(pfmt
);
411 debug_assert(fmt
!= ~0);
413 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
414 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
415 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
416 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
417 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
418 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
419 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
420 OUT_RELOC(ring
, rsc
->bo
, vb
->buffer_offset
+ elem
->src_offset
, 0, 0);
422 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
423 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
424 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
425 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
426 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
427 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
428 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
429 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
430 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
431 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
433 total_in
+= vp
->inputs
[i
].ncomp
;
438 /* hw doesn't like to be configured for zero vbo's, it seems: */
440 /* just recycle the shader bo, we just need to point to *something*
443 struct fd_bo
*dummy_vbo
= vp
->bo
;
444 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
445 (instance_regid
!= regid(63, 0)) ||
446 (vtxcnt_regid
!= regid(63, 0));
448 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(0), 2);
449 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
450 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
451 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
452 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
453 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
454 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
456 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(0), 1);
457 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
458 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
459 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM
) |
460 A3XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
461 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
462 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
463 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
464 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
470 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
471 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
472 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
473 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
474 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
475 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
476 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
477 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
479 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
480 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
481 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
485 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
486 struct fd3_emit
*emit
)
488 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
489 const struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
490 uint32_t dirty
= emit
->dirty
;
492 emit_marker(ring
, 5);
494 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
495 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
496 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
497 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
498 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
501 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
| FD_DIRTY_BLEND_DUAL
)) &&
502 !emit
->key
.binning_pass
) {
503 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
|
504 fd3_blend_stateobj(ctx
->blend
)->rb_render_control
;
506 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
507 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
508 A3XX_RB_RENDER_CONTROL_YCOORD
|
509 A3XX_RB_RENDER_CONTROL_ZCOORD
|
510 A3XX_RB_RENDER_CONTROL_WCOORD
);
512 /* I suppose if we needed to (which I don't *think* we need
513 * to), we could emit this for binning pass too. But we
514 * would need to keep a different patch-list for binning
518 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
519 OUT_RINGP(ring
, val
, &ctx
->batch
->rbrc_patches
);
522 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
523 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
524 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
526 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
527 OUT_RING(ring
, zsa
->rb_alpha_ref
);
529 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
530 OUT_RING(ring
, zsa
->rb_stencil_control
);
532 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
533 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
534 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
535 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
536 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
539 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
540 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
541 if (fp
->writes_pos
) {
542 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
543 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
546 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
548 if (!ctx
->rasterizer
->depth_clip
) {
549 val
|= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
;
551 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
555 if (dirty
& FD_DIRTY_RASTERIZER
) {
556 struct fd3_rasterizer_stateobj
*rasterizer
=
557 fd3_rasterizer_stateobj(ctx
->rasterizer
);
559 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
560 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
562 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
563 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
564 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
566 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
567 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
568 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
571 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
572 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
574 uint8_t planes
= ctx
->rasterizer
->clip_plane_enable
;
575 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
576 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
577 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
578 if (!emit
->key
.ucp_enables
)
579 val
|= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
580 MIN2(util_bitcount(planes
), 6));
581 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
585 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
| FD_DIRTY_UCP
)) {
586 uint32_t planes
= ctx
->rasterizer
->clip_plane_enable
;
589 if (emit
->key
.ucp_enables
)
592 while (planes
&& count
< 6) {
593 int i
= ffs(planes
) - 1;
595 planes
&= ~(1U << i
);
596 fd_wfi(ctx
->batch
, ring
);
597 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(count
++), 4);
598 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][0]));
599 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][1]));
600 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][2]));
601 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][3]));
605 /* NOTE: since primitive_restart is not actually part of any
606 * state object, we need to make sure that we always emit
607 * PRIM_VTX_CNTL.. either that or be more clever and detect
611 const struct pipe_draw_info
*info
= emit
->info
;
612 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
615 if (!emit
->key
.binning_pass
) {
616 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
617 if (stride_in_vpc
> 0)
618 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
619 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
622 if (info
->indexed
&& info
->primitive_restart
) {
623 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
626 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
628 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
632 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
| FD_DIRTY_VIEWPORT
)) {
633 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
634 int minx
= scissor
->minx
;
635 int miny
= scissor
->miny
;
636 int maxx
= scissor
->maxx
;
637 int maxy
= scissor
->maxy
;
639 /* Unfortunately there is no separate depth clip disable, only an all
640 * or nothing deal. So when we disable clipping, we must handle the
641 * viewport clip via scissors.
643 if (!ctx
->rasterizer
->depth_clip
) {
644 struct pipe_viewport_state
*vp
= &ctx
->viewport
;
645 minx
= MAX2(minx
, (int)floorf(vp
->translate
[0] - fabsf(vp
->scale
[0])));
646 miny
= MAX2(miny
, (int)floorf(vp
->translate
[1] - fabsf(vp
->scale
[1])));
647 maxx
= MIN2(maxx
, (int)ceilf(vp
->translate
[0] + fabsf(vp
->scale
[0])));
648 maxy
= MIN2(maxy
, (int)ceilf(vp
->translate
[1] + fabsf(vp
->scale
[1])));
651 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
652 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx
) |
653 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny
));
654 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx
- 1) |
655 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy
- 1));
657 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, minx
);
658 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, miny
);
659 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, maxx
);
660 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, maxy
);
663 if (dirty
& FD_DIRTY_VIEWPORT
) {
664 fd_wfi(ctx
->batch
, ring
);
665 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
666 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
667 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
668 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
669 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
670 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
671 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
674 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
677 if (ctx
->batch
->framebuffer
.zsbuf
) {
678 depth
= util_format_get_component_bits(
679 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
680 UTIL_FORMAT_COLORSPACE_ZS
, 0);
682 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
685 OUT_PKT0(ring
, REG_A3XX_RB_Z_CLAMP_MIN
, 2);
687 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffffff));
688 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffffff));
689 } else if (depth
== 16) {
690 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
691 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
693 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
694 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
698 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_BLEND_DUAL
)) {
699 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
700 int nr_cbufs
= pfb
->nr_cbufs
;
701 if (fd3_blend_stateobj(ctx
->blend
)->rb_render_control
&
702 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE
)
704 fd3_program_emit(ring
, emit
, nr_cbufs
, pfb
->cbufs
);
707 /* TODO we should not need this or fd_wfi() before emit_constants():
709 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
710 OUT_RING(ring
, HLSQ_FLUSH
);
712 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
713 ir3_emit_consts(vp
, ring
, ctx
, emit
->info
, dirty
);
714 if (!emit
->key
.binning_pass
)
715 ir3_emit_consts(fp
, ring
, ctx
, emit
->info
, dirty
);
718 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) {
719 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
722 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
723 enum pipe_format format
=
724 pipe_surface_format(ctx
->batch
->framebuffer
.cbufs
[i
]);
725 const struct util_format_description
*desc
=
726 util_format_description(format
);
727 bool is_float
= util_format_is_float(format
);
728 bool is_int
= util_format_is_pure_integer(format
);
729 bool has_alpha
= util_format_has_alpha(format
);
730 uint32_t control
= blend
->rb_mrt
[i
].control
;
731 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
734 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
735 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
736 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
739 if (format
== PIPE_FORMAT_NONE
)
740 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
743 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
745 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
746 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
749 if (format
&& util_format_get_component_bits(
750 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
751 const struct pipe_rt_blend_state
*rt
;
752 if (ctx
->blend
->independent_blend_enable
)
753 rt
= &ctx
->blend
->rt
[i
];
755 rt
= &ctx
->blend
->rt
[0];
757 if (!util_format_colormask_full(desc
, rt
->colormask
))
758 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
761 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
762 OUT_RING(ring
, control
);
764 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
765 OUT_RING(ring
, blend_control
|
766 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
770 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
771 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
772 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
773 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
774 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
775 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
776 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
777 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
778 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
779 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
780 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
783 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
))
784 fd_wfi(ctx
->batch
, ring
);
786 if (dirty
& FD_DIRTY_VERTTEX
) {
788 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
790 dirty
&= ~FD_DIRTY_VERTTEX
;
793 if (dirty
& FD_DIRTY_FRAGTEX
) {
795 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
797 dirty
&= ~FD_DIRTY_FRAGTEX
;
800 ctx
->dirty
&= ~dirty
;
803 /* emit setup at begin of new cmdstream buffer (don't rely on previous
804 * state, there could have been a context switch between ioctls):
807 fd3_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
809 struct fd_context
*ctx
= batch
->ctx
;
810 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
813 if (ctx
->screen
->gpu_id
== 320) {
814 OUT_PKT3(ring
, CP_REG_RMW
, 3);
815 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
816 OUT_RING(ring
, 0xfffcffff);
817 OUT_RING(ring
, 0x00000000);
821 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
822 OUT_RING(ring
, 0x00007fff);
824 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
825 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
826 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
827 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
829 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
830 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
831 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
832 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
834 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
835 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
837 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
838 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
839 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
840 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
842 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
843 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
844 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
845 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
846 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
848 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
849 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
850 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
852 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
853 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
855 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
856 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
857 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
858 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
860 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
861 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
862 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
863 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
865 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
866 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
867 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
869 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
870 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
872 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
873 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
875 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
876 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
878 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
879 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
881 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
882 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
884 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
885 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
886 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
887 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
888 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
890 fd3_emit_cache_flush(batch
, ring
);
892 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
893 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
895 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
896 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
897 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
899 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
900 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
902 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
903 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
904 A3XX_RB_WINDOW_OFFSET_Y(0));
906 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
907 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
908 A3XX_RB_BLEND_RED_FLOAT(0.0));
909 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
910 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
911 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
912 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
913 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
914 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
916 for (i
= 0; i
< 6; i
++) {
917 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
918 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
919 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
920 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
921 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
924 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
925 OUT_RING(ring
, 0x00000000);
927 fd_event_write(batch
, ring
, CACHE_FLUSH
);
929 if (is_a3xx_p0(ctx
->screen
)) {
930 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
931 OUT_RING(ring
, 0x00000000);
932 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
933 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
934 OUT_RING(ring
, 0); /* NumIndices */
937 OUT_PKT3(ring
, CP_NOP
, 4);
938 OUT_RING(ring
, 0x00000000);
939 OUT_RING(ring
, 0x00000000);
940 OUT_RING(ring
, 0x00000000);
941 OUT_RING(ring
, 0x00000000);
945 fd_hw_query_enable(batch
, ring
);
949 fd3_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
951 __OUT_IB(ring
, true, target
);
955 fd3_emit_init(struct pipe_context
*pctx
)
957 struct fd_context
*ctx
= fd_context(pctx
);
958 ctx
->emit_const
= fd3_emit_const
;
959 ctx
->emit_const_bo
= fd3_emit_const_bo
;
960 ctx
->emit_ib
= fd3_emit_ib
;