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freedreno: helper for a3xx/a4xx border-colors
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = SS_INDIRECT;
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/2));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
126
127 static void
128 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
129 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
130 {
131 static const unsigned tex_off[] = {
132 [SB_VERT_TEX] = VERT_TEX_OFF,
133 [SB_FRAG_TEX] = FRAG_TEX_OFF,
134 };
135 static const enum adreno_state_block mipaddr[] = {
136 [SB_VERT_TEX] = SB_VERT_MIPADDR,
137 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
138 };
139 static const uint32_t bcolor_reg[] = {
140 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
141 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
142 };
143 struct fd3_context *fd3_ctx = fd3_context(ctx);
144 unsigned i, j, off;
145 void *ptr;
146
147 u_upload_alloc(fd3_ctx->border_color_uploader,
148 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
149 &fd3_ctx->border_color_buf,
150 &ptr);
151
152 fd_setup_border_colors(tex, ptr, tex_off[sb]);
153
154 if (tex->num_samplers > 0) {
155 /* output sampler state: */
156 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
158 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
159 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
160 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
161 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
162 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
163 for (i = 0; i < tex->num_samplers; i++) {
164 static const struct fd3_sampler_stateobj dummy_sampler = {};
165 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
166 fd3_sampler_stateobj(tex->samplers[i]) :
167 &dummy_sampler;
168
169 OUT_RING(ring, sampler->texsamp0);
170 OUT_RING(ring, sampler->texsamp1);
171 }
172 }
173
174 if (tex->num_textures > 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
177 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
181 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i = 0; i < tex->num_textures; i++) {
184 static const struct fd3_pipe_sampler_view dummy_view = {};
185 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
186 fd3_pipe_sampler_view(tex->textures[i]) :
187 &dummy_view;
188 OUT_RING(ring, view->texconst0);
189 OUT_RING(ring, view->texconst1);
190 OUT_RING(ring, view->texconst2 |
191 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
192 OUT_RING(ring, view->texconst3);
193 }
194
195 /* emit mipaddrs: */
196 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
197 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
198 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
199 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
200 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
201 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
202 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
203 for (i = 0; i < tex->num_textures; i++) {
204 static const struct fd3_pipe_sampler_view dummy_view = {
205 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
206 .base.u.tex.first_level = 1,
207 };
208 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
209 fd3_pipe_sampler_view(tex->textures[i]) :
210 &dummy_view;
211 struct fd_resource *rsc = fd_resource(view->base.texture);
212 unsigned start = fd_sampler_first_level(&view->base);
213 unsigned end = fd_sampler_last_level(&view->base);;
214
215 for (j = 0; j < (end - start + 1); j++) {
216 struct fd_resource_slice *slice =
217 fd_resource_slice(rsc, j + start);
218 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
219 }
220
221 /* pad the remaining entries w/ null: */
222 for (; j < BASETABLE_SZ; j++) {
223 OUT_RING(ring, 0x00000000);
224 }
225 }
226 }
227
228 OUT_PKT0(ring, bcolor_reg[sb], 1);
229 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
230
231 u_upload_unmap(fd3_ctx->border_color_uploader);
232 }
233
234 /* emit texture state for mem->gmem restore operation.. eventually it would
235 * be good to get rid of this and use normal CSO/etc state for more of these
236 * special cases, but for now the compiler is not sufficient..
237 *
238 * Also, for using normal state, not quite sure how to handle the special
239 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
240 */
241 void
242 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
243 struct pipe_surface **psurf,
244 int bufs)
245 {
246 int i, j;
247
248 /* output sampler state: */
249 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
250 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
251 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
252 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
253 CP_LOAD_STATE_0_NUM_UNIT(bufs));
254 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
255 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
256 for (i = 0; i < bufs; i++) {
257 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
258 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
259 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
260 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
261 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
262 OUT_RING(ring, 0x00000000);
263 }
264
265 /* emit texture state: */
266 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
267 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
268 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
269 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
270 CP_LOAD_STATE_0_NUM_UNIT(bufs));
271 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
272 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
273 for (i = 0; i < bufs; i++) {
274 if (!psurf[i]) {
275 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
276 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
277 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
278 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
279 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
280 OUT_RING(ring, 0x00000000);
281 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
282 OUT_RING(ring, 0x00000000);
283 continue;
284 }
285
286 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
287 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
288 /* The restore blit_zs shader expects stencil in sampler 0, and depth
289 * in sampler 1
290 */
291 if (rsc->stencil && i == 0) {
292 rsc = rsc->stencil;
293 format = fd3_gmem_restore_format(rsc->base.b.format);
294 }
295
296 /* note: PIPE_BUFFER disallowed for surfaces */
297 unsigned lvl = psurf[i]->u.tex.level;
298 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
299
300 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
301
302 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
303 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
304 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
305 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
306 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
307 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
308 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
309 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
310 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
311 OUT_RING(ring, 0x00000000);
312 }
313
314 /* emit mipaddrs: */
315 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
316 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
317 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
318 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
319 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
320 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
321 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
322 for (i = 0; i < bufs; i++) {
323 if (psurf[i]) {
324 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
325 /* Matches above logic for blit_zs shader */
326 if (rsc->stencil && i == 0)
327 rsc = rsc->stencil;
328 unsigned lvl = psurf[i]->u.tex.level;
329 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
330 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
331 } else {
332 OUT_RING(ring, 0x00000000);
333 }
334
335 /* pad the remaining entries w/ null: */
336 for (j = 1; j < BASETABLE_SZ; j++) {
337 OUT_RING(ring, 0x00000000);
338 }
339 }
340 }
341
342 void
343 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
344 {
345 int32_t i, j, last = -1;
346 uint32_t total_in = 0;
347 const struct fd_vertex_state *vtx = emit->vtx;
348 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
349 unsigned vertex_regid = regid(63, 0);
350 unsigned instance_regid = regid(63, 0);
351 unsigned vtxcnt_regid = regid(63, 0);
352
353 for (i = 0; i < vp->inputs_count; i++) {
354 uint8_t semantic = sem2name(vp->inputs[i].semantic);
355 if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
356 vertex_regid = vp->inputs[i].regid;
357 else if (semantic == TGSI_SEMANTIC_INSTANCEID)
358 instance_regid = vp->inputs[i].regid;
359 else if (semantic == IR3_SEMANTIC_VTXCNT)
360 vtxcnt_regid = vp->inputs[i].regid;
361 else if (i < vtx->vtx->num_elements && vp->inputs[i].compmask)
362 last = i;
363 }
364
365 /* hw doesn't like to be configured for zero vbo's, it seems: */
366 if ((vtx->vtx->num_elements == 0) &&
367 (vertex_regid == regid(63, 0)) &&
368 (instance_regid == regid(63, 0)) &&
369 (vtxcnt_regid == regid(63, 0)))
370 return;
371
372 for (i = 0, j = 0; i <= last; i++) {
373 assert(sem2name(vp->inputs[i].semantic) == 0);
374 if (vp->inputs[i].compmask) {
375 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
376 const struct pipe_vertex_buffer *vb =
377 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
378 struct fd_resource *rsc = fd_resource(vb->buffer);
379 enum pipe_format pfmt = elem->src_format;
380 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
381 bool switchnext = (i != last) ||
382 (vertex_regid != regid(63, 0)) ||
383 (instance_regid != regid(63, 0)) ||
384 (vtxcnt_regid != regid(63, 0));
385 bool isint = util_format_is_pure_integer(pfmt);
386 uint32_t fs = util_format_get_blocksize(pfmt);
387
388 debug_assert(fmt != ~0);
389
390 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
391 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
392 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
393 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
394 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
395 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
396 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
397 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
398
399 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
400 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
401 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
402 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
403 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
404 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
405 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
406 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
407 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
408 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
409
410 total_in += vp->inputs[i].ncomp;
411 j++;
412 }
413 }
414
415 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
416 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
417 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
418 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
419 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
420 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
421 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
422 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
423
424 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
425 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
426 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
427 }
428
429 void
430 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
431 struct fd3_emit *emit)
432 {
433 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
434 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
435 uint32_t dirty = emit->dirty;
436
437 emit_marker(ring, 5);
438
439 if (dirty & FD_DIRTY_SAMPLE_MASK) {
440 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
441 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
442 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
443 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
444 }
445
446 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
447 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control;
448
449 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
450 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
451 A3XX_RB_RENDER_CONTROL_YCOORD |
452 A3XX_RB_RENDER_CONTROL_ZCOORD |
453 A3XX_RB_RENDER_CONTROL_WCOORD);
454
455 /* I suppose if we needed to (which I don't *think* we need
456 * to), we could emit this for binning pass too. But we
457 * would need to keep a different patch-list for binning
458 * vs render pass.
459 */
460
461 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
462 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
463 }
464
465 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
466 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
467 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
468
469 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
470 OUT_RING(ring, zsa->rb_alpha_ref);
471
472 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
473 OUT_RING(ring, zsa->rb_stencil_control);
474
475 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
476 OUT_RING(ring, zsa->rb_stencilrefmask |
477 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
478 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
479 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
480 }
481
482 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
483 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
484 if (fp->writes_pos) {
485 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
486 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
487 }
488 if (fp->has_kill) {
489 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
490 }
491 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
492 OUT_RING(ring, val);
493 }
494
495 if (dirty & FD_DIRTY_RASTERIZER) {
496 struct fd3_rasterizer_stateobj *rasterizer =
497 fd3_rasterizer_stateobj(ctx->rasterizer);
498
499 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
500 OUT_RING(ring, rasterizer->gras_su_mode_control);
501
502 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
503 OUT_RING(ring, rasterizer->gras_su_point_minmax);
504 OUT_RING(ring, rasterizer->gras_su_point_size);
505
506 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
507 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
508 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
509 }
510
511 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
512 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
513 ->gras_cl_clip_cntl;
514 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
515 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
516 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
517 /* TODO only use if prog doesn't use clipvertex/clipdist */
518 val |= MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6) << 26;
519 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
520 OUT_RING(ring, val);
521 }
522
523 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
524 uint32_t planes = ctx->rasterizer->clip_plane_enable;
525 int count = 0;
526
527 while (planes && count < 6) {
528 int i = ffs(planes) - 1;
529
530 planes &= ~(1U << i);
531 fd_wfi(ctx, ring);
532 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
533 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
534 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
535 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
536 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
537 }
538 }
539
540 /* NOTE: since primitive_restart is not actually part of any
541 * state object, we need to make sure that we always emit
542 * PRIM_VTX_CNTL.. either that or be more clever and detect
543 * when it changes.
544 */
545 if (emit->info) {
546 const struct pipe_draw_info *info = emit->info;
547 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
548 ->pc_prim_vtx_cntl;
549
550 if (!emit->key.binning_pass) {
551 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
552 if (stride_in_vpc > 0)
553 stride_in_vpc = MAX2(stride_in_vpc, 2);
554 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
555 }
556
557 if (info->indexed && info->primitive_restart) {
558 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
559 }
560
561 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
562
563 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
564 OUT_RING(ring, val);
565 }
566
567 if (dirty & FD_DIRTY_SCISSOR) {
568 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
569
570 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
571 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
572 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
573 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
574 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
575
576 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
577 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
578 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
579 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
580 }
581
582 if (dirty & FD_DIRTY_VIEWPORT) {
583 fd_wfi(ctx, ring);
584 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
585 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
586 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
587 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
588 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
589 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
590 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
591 }
592
593 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
594 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
595 fd3_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
596 }
597
598 /* TODO we should not need this or fd_wfi() before emit_constants():
599 */
600 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
601 OUT_RING(ring, HLSQ_FLUSH);
602
603 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
604 ir3_emit_consts(vp, ring, emit->info, dirty);
605 if (!emit->key.binning_pass)
606 ir3_emit_consts(fp, ring, emit->info, dirty);
607 /* mark clean after emitting consts: */
608 ctx->prog.dirty = 0;
609 }
610
611 if ((dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) && ctx->blend) {
612 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
613 uint32_t i;
614
615 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
616 enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
617 const struct util_format_description *desc =
618 util_format_description(format);
619 bool is_float = util_format_is_float(format);
620 bool is_int = util_format_is_pure_integer(format);
621 bool has_alpha = util_format_has_alpha(format);
622 uint32_t control = blend->rb_mrt[i].control;
623 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
624
625 if (is_int) {
626 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
627 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
628 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
629 }
630
631 if (format == PIPE_FORMAT_NONE)
632 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
633
634 if (has_alpha) {
635 blend_control |= blend->rb_mrt[i].blend_control_rgb;
636 } else {
637 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
638 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
639 }
640
641 if (format && util_format_get_component_bits(
642 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
643 const struct pipe_rt_blend_state *rt;
644 if (ctx->blend->independent_blend_enable)
645 rt = &ctx->blend->rt[i];
646 else
647 rt = &ctx->blend->rt[0];
648
649 if (!util_format_colormask_full(desc, rt->colormask))
650 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
651 }
652
653 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
654 OUT_RING(ring, control);
655
656 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
657 OUT_RING(ring, blend_control |
658 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
659 }
660 }
661
662 if (dirty & FD_DIRTY_BLEND_COLOR) {
663 struct pipe_blend_color *bcolor = &ctx->blend_color;
664 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
665 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
666 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
667 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
668 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
669 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
670 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
671 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
672 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
673 }
674
675 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
676 fd_wfi(ctx, ring);
677
678 if (dirty & FD_DIRTY_VERTTEX) {
679 if (vp->has_samp)
680 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
681 else
682 dirty &= ~FD_DIRTY_VERTTEX;
683 }
684
685 if (dirty & FD_DIRTY_FRAGTEX) {
686 if (fp->has_samp)
687 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
688 else
689 dirty &= ~FD_DIRTY_FRAGTEX;
690 }
691
692 ctx->dirty &= ~dirty;
693 }
694
695 /* emit setup at begin of new cmdstream buffer (don't rely on previous
696 * state, there could have been a context switch between ioctls):
697 */
698 void
699 fd3_emit_restore(struct fd_context *ctx)
700 {
701 struct fd3_context *fd3_ctx = fd3_context(ctx);
702 struct fd_ringbuffer *ring = ctx->ring;
703 int i;
704
705 if (ctx->screen->gpu_id == 320) {
706 OUT_PKT3(ring, CP_REG_RMW, 3);
707 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
708 OUT_RING(ring, 0xfffcffff);
709 OUT_RING(ring, 0x00000000);
710 }
711
712 fd_wfi(ctx, ring);
713 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
714 OUT_RING(ring, 0x00007fff);
715
716 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
717 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
718 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
719 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
720
721 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
722 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
723 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
724 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
725
726 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
727 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
728
729 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
730 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
731 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
732 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
733
734 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
735 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
736 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
737 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
738 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
739
740 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
741 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
742 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
743
744 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
745 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
746
747 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
748 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
749 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
750 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
751
752 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
753 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
754 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
755 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
756
757 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
758 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
759 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
760
761 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
762 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
763
764 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
765 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
766
767 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
768 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
769
770 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
771 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
772
773 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
774 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
775
776 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
777 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
778 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
779 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
780 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
781
782 OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
783 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
784 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
785 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
786 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
787
788 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
789 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
790
791 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
792 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
793 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
794
795 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
796 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
797
798 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
799 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
800 A3XX_RB_WINDOW_OFFSET_Y(0));
801
802 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
803 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
804 A3XX_RB_BLEND_RED_FLOAT(0.0));
805 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
806 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
807 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
808 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
809 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
810 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
811
812 for (i = 0; i < 6; i++) {
813 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
814 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
815 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
816 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
817 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
818 }
819
820 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
821 OUT_RING(ring, 0x00000000);
822
823 fd_event_write(ctx, ring, CACHE_FLUSH);
824
825 if (is_a3xx_p0(ctx->screen)) {
826 OUT_PKT3(ring, CP_DRAW_INDX, 3);
827 OUT_RING(ring, 0x00000000);
828 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
829 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
830 OUT_RING(ring, 0); /* NumIndices */
831 }
832
833 OUT_PKT3(ring, CP_NOP, 4);
834 OUT_RING(ring, 0x00000000);
835 OUT_RING(ring, 0x00000000);
836 OUT_RING(ring, 0x00000000);
837 OUT_RING(ring, 0x00000000);
838
839 fd_wfi(ctx, ring);
840
841 ctx->needs_rb_fbd = true;
842 }
843
844 void
845 fd3_emit_init(struct pipe_context *pctx)
846 {
847 struct fd_context *ctx = fd_context(pctx);
848 ctx->emit_const = fd3_emit_const;
849 ctx->emit_const_bo = fd3_emit_const_bo;
850 }