1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34 #include "util/u_viewport.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
40 #include "fd3_blend.h"
41 #include "fd3_context.h"
42 #include "fd3_program.h"
43 #include "fd3_rasterizer.h"
44 #include "fd3_texture.h"
45 #include "fd3_format.h"
48 static const enum adreno_state_block sb
[] = {
49 [SHADER_VERTEX
] = SB_VERT_SHADER
,
50 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
58 fd3_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
59 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
60 const uint32_t *dwords
, struct pipe_resource
*prsc
)
63 enum adreno_state_src src
;
65 debug_assert((regid
% 4) == 0);
66 debug_assert((sizedwords
% 4) == 0);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
97 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
99 uint32_t anum
= align(num
, 4);
102 debug_assert((regid
% 4) == 0);
104 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + anum
);
105 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
108 CP_LOAD_STATE_0_NUM_UNIT(anum
/2));
109 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
112 for (i
= 0; i
< num
; i
++) {
115 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
117 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
120 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
124 for (; i
< anum
; i
++)
125 OUT_RING(ring
, 0xffffffff);
128 #define VERT_TEX_OFF 0
129 #define FRAG_TEX_OFF 16
130 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
133 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
134 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
136 static const unsigned tex_off
[] = {
137 [SB_VERT_TEX
] = VERT_TEX_OFF
,
138 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
140 static const enum adreno_state_block mipaddr
[] = {
141 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
142 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
144 static const uint32_t bcolor_reg
[] = {
145 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
146 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
148 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
149 bool needs_border
= false;
152 if (tex
->num_samplers
> 0) {
153 /* output sampler state: */
154 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
155 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
156 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
157 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
158 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
159 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
160 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
161 for (i
= 0; i
< tex
->num_samplers
; i
++) {
162 static const struct fd3_sampler_stateobj dummy_sampler
= {};
163 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
164 fd3_sampler_stateobj(tex
->samplers
[i
]) :
167 OUT_RING(ring
, sampler
->texsamp0
);
168 OUT_RING(ring
, sampler
->texsamp1
);
170 needs_border
|= sampler
->needs_border
;
174 if (tex
->num_textures
> 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
177 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
181 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i
= 0; i
< tex
->num_textures
; i
++) {
184 static const struct fd3_pipe_sampler_view dummy_view
= {};
185 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
186 fd3_pipe_sampler_view(tex
->textures
[i
]) :
188 OUT_RING(ring
, view
->texconst0
);
189 OUT_RING(ring
, view
->texconst1
);
190 OUT_RING(ring
, view
->texconst2
|
191 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
192 OUT_RING(ring
, view
->texconst3
);
196 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
197 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
198 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
199 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
200 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
201 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
202 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
203 for (i
= 0; i
< tex
->num_textures
; i
++) {
204 static const struct fd3_pipe_sampler_view dummy_view
= {
205 .base
.target
= PIPE_TEXTURE_1D
, /* anything !PIPE_BUFFER */
206 .base
.u
.tex
.first_level
= 1,
208 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
209 fd3_pipe_sampler_view(tex
->textures
[i
]) :
211 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
212 if (rsc
&& rsc
->base
.target
== PIPE_BUFFER
) {
213 OUT_RELOC(ring
, rsc
->bo
, view
->base
.u
.buf
.offset
, 0, 0);
216 unsigned start
= fd_sampler_first_level(&view
->base
);
217 unsigned end
= fd_sampler_last_level(&view
->base
);
219 for (j
= 0; j
< (end
- start
+ 1); j
++) {
220 struct fd_resource_slice
*slice
=
221 fd_resource_slice(rsc
, j
+ start
);
222 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
226 /* pad the remaining entries w/ null: */
227 for (; j
< BASETABLE_SZ
; j
++) {
228 OUT_RING(ring
, 0x00000000);
237 u_upload_alloc(fd3_ctx
->border_color_uploader
,
238 0, BORDER_COLOR_UPLOAD_SIZE
,
239 BORDER_COLOR_UPLOAD_SIZE
, &off
,
240 &fd3_ctx
->border_color_buf
,
243 fd_setup_border_colors(tex
, ptr
, tex_off
[sb
]);
245 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
246 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
248 u_upload_unmap(fd3_ctx
->border_color_uploader
);
252 /* emit texture state for mem->gmem restore operation.. eventually it would
253 * be good to get rid of this and use normal CSO/etc state for more of these
254 * special cases, but for now the compiler is not sufficient..
256 * Also, for using normal state, not quite sure how to handle the special
257 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
260 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
261 struct pipe_surface
**psurf
,
266 /* output sampler state: */
267 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
268 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
269 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
270 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
271 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
272 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
273 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
274 for (i
= 0; i
< bufs
; i
++) {
275 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
276 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
277 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
278 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
279 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
280 OUT_RING(ring
, 0x00000000);
283 /* emit texture state: */
284 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
285 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
286 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
287 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
288 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
289 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
290 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
291 for (i
= 0; i
< bufs
; i
++) {
293 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
294 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
295 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
296 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
297 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
298 OUT_RING(ring
, 0x00000000);
299 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
300 OUT_RING(ring
, 0x00000000);
304 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
305 enum pipe_format format
= fd_gmem_restore_format(psurf
[i
]->format
);
306 /* The restore blit_zs shader expects stencil in sampler 0, and depth
309 if (rsc
->stencil
&& i
== 0) {
311 format
= fd_gmem_restore_format(rsc
->base
.format
);
314 /* note: PIPE_BUFFER disallowed for surfaces */
315 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
316 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
318 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
320 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
321 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
322 fd3_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
323 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
324 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
325 A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
326 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
327 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
328 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
329 OUT_RING(ring
, 0x00000000);
333 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
334 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
335 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
336 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
337 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
338 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
339 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
340 for (i
= 0; i
< bufs
; i
++) {
342 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
343 /* Matches above logic for blit_zs shader */
344 if (rsc
->stencil
&& i
== 0)
346 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
347 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
348 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
350 OUT_RING(ring
, 0x00000000);
353 /* pad the remaining entries w/ null: */
354 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
355 OUT_RING(ring
, 0x00000000);
361 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
363 int32_t i
, j
, last
= -1;
364 uint32_t total_in
= 0;
365 const struct fd_vertex_state
*vtx
= emit
->vtx
;
366 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
367 unsigned vertex_regid
= regid(63, 0);
368 unsigned instance_regid
= regid(63, 0);
369 unsigned vtxcnt_regid
= regid(63, 0);
371 /* Note that sysvals come *after* normal inputs: */
372 for (i
= 0; i
< vp
->inputs_count
; i
++) {
373 if (!vp
->inputs
[i
].compmask
)
375 if (vp
->inputs
[i
].sysval
) {
376 switch(vp
->inputs
[i
].slot
) {
377 case SYSTEM_VALUE_FIRST_VERTEX
:
378 /* handled elsewhere */
380 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
381 vertex_regid
= vp
->inputs
[i
].regid
;
383 case SYSTEM_VALUE_INSTANCE_ID
:
384 instance_regid
= vp
->inputs
[i
].regid
;
386 case SYSTEM_VALUE_VERTEX_CNT
:
387 vtxcnt_regid
= vp
->inputs
[i
].regid
;
390 unreachable("invalid system value");
393 } else if (i
< vtx
->vtx
->num_elements
) {
398 for (i
= 0, j
= 0; i
<= last
; i
++) {
399 assert(!vp
->inputs
[i
].sysval
);
400 if (vp
->inputs
[i
].compmask
) {
401 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
402 const struct pipe_vertex_buffer
*vb
=
403 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
404 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
405 enum pipe_format pfmt
= elem
->src_format
;
406 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
407 bool switchnext
= (i
!= last
) ||
408 (vertex_regid
!= regid(63, 0)) ||
409 (instance_regid
!= regid(63, 0)) ||
410 (vtxcnt_regid
!= regid(63, 0));
411 bool isint
= util_format_is_pure_integer(pfmt
);
412 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
413 uint32_t fs
= util_format_get_blocksize(pfmt
);
416 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
417 * should mesa/st be protecting us from this?
419 if (off
> fd_bo_size(rsc
->bo
))
423 debug_assert(fmt
!= ~0);
425 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
426 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
427 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
428 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
429 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
430 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
431 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
432 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
434 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
435 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
436 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
437 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
438 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
439 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
440 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
441 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
442 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
443 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
445 total_in
+= vp
->inputs
[i
].ncomp
;
450 /* hw doesn't like to be configured for zero vbo's, it seems: */
452 /* just recycle the shader bo, we just need to point to *something*
455 struct fd_bo
*dummy_vbo
= vp
->bo
;
456 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
457 (instance_regid
!= regid(63, 0)) ||
458 (vtxcnt_regid
!= regid(63, 0));
460 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(0), 2);
461 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
462 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
463 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
464 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
465 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
466 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
468 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(0), 1);
469 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
470 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
471 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM
) |
472 A3XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
473 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
474 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
475 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
476 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
482 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
483 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
484 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
485 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
486 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
487 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
488 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
489 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
491 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
492 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
493 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
497 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
498 struct fd3_emit
*emit
)
500 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
501 const struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
502 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
504 emit_marker(ring
, 5);
506 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
507 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
508 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
509 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
510 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
513 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
| FD_DIRTY_BLEND_DUAL
)) &&
514 !emit
->key
.binning_pass
) {
515 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
|
516 fd3_blend_stateobj(ctx
->blend
)->rb_render_control
;
518 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
519 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
520 A3XX_RB_RENDER_CONTROL_YCOORD
|
521 A3XX_RB_RENDER_CONTROL_ZCOORD
|
522 A3XX_RB_RENDER_CONTROL_WCOORD
);
524 /* I suppose if we needed to (which I don't *think* we need
525 * to), we could emit this for binning pass too. But we
526 * would need to keep a different patch-list for binning
530 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
531 OUT_RINGP(ring
, val
, &ctx
->batch
->rbrc_patches
);
534 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
535 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
536 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
538 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
539 OUT_RING(ring
, zsa
->rb_alpha_ref
);
541 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
542 OUT_RING(ring
, zsa
->rb_stencil_control
);
544 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
545 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
546 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
547 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
548 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
551 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
552 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
553 if (fp
->writes_pos
) {
554 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
555 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
558 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
560 if (!ctx
->rasterizer
->depth_clip_near
) {
561 val
|= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
;
563 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
567 if (dirty
& FD_DIRTY_RASTERIZER
) {
568 struct fd3_rasterizer_stateobj
*rasterizer
=
569 fd3_rasterizer_stateobj(ctx
->rasterizer
);
571 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
572 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
574 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
575 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
576 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
578 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
579 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
580 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
583 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
584 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
586 uint8_t planes
= ctx
->rasterizer
->clip_plane_enable
;
587 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
588 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
589 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
590 if (!emit
->key
.ucp_enables
)
591 val
|= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
592 MIN2(util_bitcount(planes
), 6));
593 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
597 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
| FD_DIRTY_UCP
)) {
598 uint32_t planes
= ctx
->rasterizer
->clip_plane_enable
;
601 if (emit
->key
.ucp_enables
)
604 while (planes
&& count
< 6) {
605 int i
= ffs(planes
) - 1;
607 planes
&= ~(1U << i
);
608 fd_wfi(ctx
->batch
, ring
);
609 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(count
++), 4);
610 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][0]));
611 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][1]));
612 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][2]));
613 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][3]));
617 /* NOTE: since primitive_restart is not actually part of any
618 * state object, we need to make sure that we always emit
619 * PRIM_VTX_CNTL.. either that or be more clever and detect
623 const struct pipe_draw_info
*info
= emit
->info
;
624 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
627 if (!emit
->key
.binning_pass
) {
628 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
629 if (stride_in_vpc
> 0)
630 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
631 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
634 if (info
->index_size
&& info
->primitive_restart
) {
635 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
638 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
640 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
644 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
| FD_DIRTY_VIEWPORT
)) {
645 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
646 int minx
= scissor
->minx
;
647 int miny
= scissor
->miny
;
648 int maxx
= scissor
->maxx
;
649 int maxy
= scissor
->maxy
;
651 /* Unfortunately there is no separate depth clip disable, only an all
652 * or nothing deal. So when we disable clipping, we must handle the
653 * viewport clip via scissors.
655 if (!ctx
->rasterizer
->depth_clip_near
) {
656 struct pipe_viewport_state
*vp
= &ctx
->viewport
;
657 minx
= MAX2(minx
, (int)floorf(vp
->translate
[0] - fabsf(vp
->scale
[0])));
658 miny
= MAX2(miny
, (int)floorf(vp
->translate
[1] - fabsf(vp
->scale
[1])));
659 maxx
= MIN2(maxx
, (int)ceilf(vp
->translate
[0] + fabsf(vp
->scale
[0])));
660 maxy
= MIN2(maxy
, (int)ceilf(vp
->translate
[1] + fabsf(vp
->scale
[1])));
663 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
664 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx
) |
665 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny
));
666 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx
- 1) |
667 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy
- 1));
669 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, minx
);
670 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, miny
);
671 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, maxx
);
672 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, maxy
);
675 if (dirty
& FD_DIRTY_VIEWPORT
) {
676 fd_wfi(ctx
->batch
, ring
);
677 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
678 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
679 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
680 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
681 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
682 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
683 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
686 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
689 if (ctx
->batch
->framebuffer
.zsbuf
) {
690 depth
= util_format_get_component_bits(
691 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
692 UTIL_FORMAT_COLORSPACE_ZS
, 0);
694 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
697 OUT_PKT0(ring
, REG_A3XX_RB_Z_CLAMP_MIN
, 2);
699 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffffff));
700 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffffff));
701 } else if (depth
== 16) {
702 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
703 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
705 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
706 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
710 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_BLEND_DUAL
)) {
711 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
712 int nr_cbufs
= pfb
->nr_cbufs
;
713 if (fd3_blend_stateobj(ctx
->blend
)->rb_render_control
&
714 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE
)
716 fd3_program_emit(ring
, emit
, nr_cbufs
, pfb
->cbufs
);
719 /* TODO we should not need this or fd_wfi() before emit_constants():
721 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
722 OUT_RING(ring
, HLSQ_FLUSH
);
724 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
725 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
726 if (!emit
->key
.binning_pass
)
727 ir3_emit_fs_consts(fp
, ring
, ctx
);
730 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) {
731 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
734 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
735 enum pipe_format format
=
736 pipe_surface_format(ctx
->batch
->framebuffer
.cbufs
[i
]);
737 const struct util_format_description
*desc
=
738 util_format_description(format
);
739 bool is_float
= util_format_is_float(format
);
740 bool is_int
= util_format_is_pure_integer(format
);
741 bool has_alpha
= util_format_has_alpha(format
);
742 uint32_t control
= blend
->rb_mrt
[i
].control
;
743 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
746 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
747 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
748 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
751 if (format
== PIPE_FORMAT_NONE
)
752 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
755 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
757 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
758 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
761 if (format
&& util_format_get_component_bits(
762 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
763 const struct pipe_rt_blend_state
*rt
;
764 if (ctx
->blend
->independent_blend_enable
)
765 rt
= &ctx
->blend
->rt
[i
];
767 rt
= &ctx
->blend
->rt
[0];
769 if (!util_format_colormask_full(desc
, rt
->colormask
))
770 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
773 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
774 OUT_RING(ring
, control
);
776 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
777 OUT_RING(ring
, blend_control
|
778 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
782 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
783 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
784 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
785 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
786 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
787 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
788 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
789 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
790 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
791 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
792 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
795 if (dirty
& FD_DIRTY_TEX
)
796 fd_wfi(ctx
->batch
, ring
);
798 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
)
799 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->tex
[PIPE_SHADER_VERTEX
]);
801 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
)
802 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
805 /* emit setup at begin of new cmdstream buffer (don't rely on previous
806 * state, there could have been a context switch between ioctls):
809 fd3_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
811 struct fd_context
*ctx
= batch
->ctx
;
812 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
815 if (ctx
->screen
->gpu_id
== 320) {
816 OUT_PKT3(ring
, CP_REG_RMW
, 3);
817 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
818 OUT_RING(ring
, 0xfffcffff);
819 OUT_RING(ring
, 0x00000000);
823 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
824 OUT_RING(ring
, 0x00007fff);
826 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
827 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
828 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
829 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
831 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
832 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
833 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
834 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
836 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
837 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
839 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
840 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
841 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
842 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
844 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
845 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
846 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
847 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
848 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
850 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
851 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
852 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
854 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
855 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
857 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
858 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
859 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
860 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
862 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
863 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
864 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
865 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
867 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
868 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
869 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
871 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
872 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
874 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
875 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
877 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
878 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
880 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
881 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
883 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
884 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
886 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
887 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
888 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
889 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
890 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
892 fd3_emit_cache_flush(batch
, ring
);
894 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
895 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
897 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
898 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
899 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
901 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
902 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
904 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
905 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
906 A3XX_RB_WINDOW_OFFSET_Y(0));
908 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
909 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
910 A3XX_RB_BLEND_RED_FLOAT(0.0));
911 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
912 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
913 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
914 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
915 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
916 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
918 for (i
= 0; i
< 6; i
++) {
919 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
920 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
921 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
922 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
923 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
926 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
927 OUT_RING(ring
, 0x00000000);
929 fd_event_write(batch
, ring
, CACHE_FLUSH
);
931 if (is_a3xx_p0(ctx
->screen
)) {
932 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
933 OUT_RING(ring
, 0x00000000);
934 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
935 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
936 OUT_RING(ring
, 0); /* NumIndices */
939 OUT_PKT3(ring
, CP_NOP
, 4);
940 OUT_RING(ring
, 0x00000000);
941 OUT_RING(ring
, 0x00000000);
942 OUT_RING(ring
, 0x00000000);
943 OUT_RING(ring
, 0x00000000);
947 fd_hw_query_enable(batch
, ring
);
951 fd3_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
953 __OUT_IB(ring
, true, target
);
957 fd3_emit_init(struct pipe_context
*pctx
)
959 struct fd_context
*ctx
= fd_context(pctx
);
960 ctx
->emit_const
= fd3_emit_const
;
961 ctx
->emit_const_bo
= fd3_emit_const_bo
;
962 ctx
->emit_ib
= fd3_emit_ib
;