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freedreno/a3xx: vtx formats
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_util.h"
44 #include "fd3_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 void
51 fd3_emit_constant(struct fd_ringbuffer *ring,
52 enum adreno_state_block sb,
53 uint32_t regid, uint32_t offset, uint32_t sizedwords,
54 const uint32_t *dwords, struct pipe_resource *prsc)
55 {
56 uint32_t i, sz;
57 enum adreno_state_src src;
58
59 if (prsc) {
60 sz = 0;
61 src = SS_INDIRECT;
62 } else {
63 sz = sizedwords;
64 src = SS_DIRECT;
65 }
66
67 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
68 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
69 CP_LOAD_STATE_0_STATE_SRC(src) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
72 if (prsc) {
73 struct fd_bo *bo = fd_resource(prsc)->bo;
74 OUT_RELOC(ring, bo, offset,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
76 } else {
77 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
79 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
80 }
81 for (i = 0; i < sz; i++) {
82 OUT_RING(ring, dwords[i]);
83 }
84 }
85
86 static void
87 emit_constants(struct fd_ringbuffer *ring,
88 enum adreno_state_block sb,
89 struct fd_constbuf_stateobj *constbuf,
90 struct fd3_shader_variant *shader)
91 {
92 uint32_t enabled_mask = constbuf->enabled_mask;
93 uint32_t first_immediate;
94 uint32_t base = 0;
95 unsigned i;
96
97 // XXX TODO only emit dirty consts.. but we need to keep track if
98 // they are clobbered by a clear, gmem2mem, or mem2gmem..
99 constbuf->dirty_mask = enabled_mask;
100
101 /* in particular, with binning shader and a unneeded consts no
102 * longer referenced, we could end up w/ constlen that is smaller
103 * than first_immediate. In that case truncate the user consts
104 * early to avoid HLSQ lockup caused by writing too many consts
105 */
106 first_immediate = MIN2(shader->first_immediate, shader->constlen);
107
108 /* emit user constants: */
109 while (enabled_mask) {
110 unsigned index = ffs(enabled_mask) - 1;
111 struct pipe_constant_buffer *cb = &constbuf->cb[index];
112 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
113
114 // I expect that size should be a multiple of vec4's:
115 assert(size == align(size, 4));
116
117 /* gallium could leave const buffers bound above what the
118 * current shader uses.. don't let that confuse us.
119 */
120 if (base >= (4 * first_immediate))
121 break;
122
123 if (constbuf->dirty_mask & (1 << index)) {
124 /* and even if the start of the const buffer is before
125 * first_immediate, the end may not be:
126 */
127 size = MIN2(size, (4 * first_immediate) - base);
128 fd3_emit_constant(ring, sb, base,
129 cb->buffer_offset, size,
130 cb->user_buffer, cb->buffer);
131 constbuf->dirty_mask &= ~(1 << index);
132 }
133
134 base += size;
135 enabled_mask &= ~(1 << index);
136 }
137
138 /* emit shader immediates: */
139 if (shader) {
140 for (i = 0; i < shader->immediates_count; i++) {
141 base = 4 * (shader->first_immediate + i);
142 if (base >= (4 * shader->constlen))
143 break;
144 fd3_emit_constant(ring, sb, base,
145 0, 4, shader->immediates[i].val, NULL);
146 }
147 }
148 }
149
150 #define VERT_TEX_OFF 0
151 #define FRAG_TEX_OFF 16
152 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
153
154 static void
155 emit_textures(struct fd_ringbuffer *ring,
156 enum adreno_state_block sb,
157 struct fd_texture_stateobj *tex)
158 {
159 static const unsigned tex_off[] = {
160 [SB_VERT_TEX] = VERT_TEX_OFF,
161 [SB_FRAG_TEX] = FRAG_TEX_OFF,
162 };
163 static const enum adreno_state_block mipaddr[] = {
164 [SB_VERT_TEX] = SB_VERT_MIPADDR,
165 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
166 };
167 unsigned i, j;
168
169 if (tex->num_samplers > 0) {
170 /* output sampler state: */
171 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
172 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
173 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
174 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
175 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
176 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
177 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
178 for (i = 0; i < tex->num_samplers; i++) {
179 static const struct fd3_sampler_stateobj dummy_sampler = {};
180 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
181 fd3_sampler_stateobj(tex->samplers[i]) :
182 &dummy_sampler;
183 OUT_RING(ring, sampler->texsamp0);
184 OUT_RING(ring, sampler->texsamp1);
185 }
186 }
187
188 if (tex->num_textures > 0) {
189 /* emit texture state: */
190 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
191 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
192 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
193 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
194 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
195 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
196 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
197 for (i = 0; i < tex->num_textures; i++) {
198 static const struct fd3_pipe_sampler_view dummy_view = {};
199 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
200 fd3_pipe_sampler_view(tex->textures[i]) :
201 &dummy_view;
202 OUT_RING(ring, view->texconst0);
203 OUT_RING(ring, view->texconst1);
204 OUT_RING(ring, view->texconst2 |
205 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
206 OUT_RING(ring, view->texconst3);
207 }
208
209 /* emit mipaddrs: */
210 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
211 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
212 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
213 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
214 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
215 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
216 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
217 for (i = 0; i < tex->num_textures; i++) {
218 static const struct fd3_pipe_sampler_view dummy_view = {};
219 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
220 fd3_pipe_sampler_view(tex->textures[i]) :
221 &dummy_view;
222 struct fd_resource *rsc = view->tex_resource;
223
224 for (j = 0; j < view->mipaddrs; j++) {
225 struct fd_resource_slice *slice = fd_resource_slice(rsc, j);
226 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
227 }
228
229 /* pad the remaining entries w/ null: */
230 for (; j < BASETABLE_SZ; j++) {
231 OUT_RING(ring, 0x00000000);
232 }
233 }
234 }
235 }
236
237 static void
238 emit_cache_flush(struct fd_ringbuffer *ring)
239 {
240 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
241 OUT_RING(ring, CACHE_FLUSH);
242
243 /* probably only really needed on a320: */
244 OUT_PKT3(ring, CP_DRAW_INDX, 3);
245 OUT_RING(ring, 0x00000000);
246 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
247 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
248 OUT_RING(ring, 0); /* NumIndices */
249
250 OUT_PKT3(ring, CP_NOP, 4);
251 OUT_RING(ring, 0x00000000);
252 OUT_RING(ring, 0x00000000);
253 OUT_RING(ring, 0x00000000);
254 OUT_RING(ring, 0x00000000);
255 }
256
257 /* emit texture state for mem->gmem restore operation.. eventually it would
258 * be good to get rid of this and use normal CSO/etc state for more of these
259 * special cases, but for now the compiler is not sufficient..
260 */
261 void
262 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
263 {
264 struct fd_resource *rsc = fd_resource(psurf->texture);
265 enum pipe_format format = fd3_gmem_restore_format(psurf->format);
266
267 /* output sampler state: */
268 OUT_PKT3(ring, CP_LOAD_STATE, 4);
269 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
270 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
271 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
272 CP_LOAD_STATE_0_NUM_UNIT(1));
273 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
274 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
275 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
276 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
277 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
278 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
279 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
280 OUT_RING(ring, 0x00000000);
281
282 /* emit texture state: */
283 OUT_PKT3(ring, CP_LOAD_STATE, 6);
284 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
285 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
286 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
287 CP_LOAD_STATE_0_NUM_UNIT(1));
288 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
289 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
290 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) |
291 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
292 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
293 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
294 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
295 A3XX_TEX_CONST_1_WIDTH(psurf->width) |
296 A3XX_TEX_CONST_1_HEIGHT(psurf->height));
297 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->slices[0].pitch * rsc->cpp) |
298 A3XX_TEX_CONST_2_INDX(0));
299 OUT_RING(ring, 0x00000000);
300
301 /* emit mipaddrs: */
302 OUT_PKT3(ring, CP_LOAD_STATE, 3);
303 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
304 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
305 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
306 CP_LOAD_STATE_0_NUM_UNIT(1));
307 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
308 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
309 OUT_RELOC(ring, rsc->bo, 0, 0, 0);
310 }
311
312 void
313 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
314 struct fd3_shader_variant *vp,
315 struct fd3_vertex_buf *vbufs, uint32_t n)
316 {
317 uint32_t i, j, last = 0;
318 uint32_t total_in = 0;
319
320 n = MIN2(n, vp->inputs_count);
321
322 for (i = 0; i < n; i++)
323 if (vp->inputs[i].compmask)
324 last = i;
325
326 for (i = 0, j = 0; i <= last; i++) {
327 if (vp->inputs[i].compmask) {
328 struct pipe_resource *prsc = vbufs[i].prsc;
329 struct fd_resource *rsc = fd_resource(prsc);
330 enum pipe_format pfmt = vbufs[i].format;
331 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
332 bool switchnext = (i != last);
333 uint32_t fs = util_format_get_blocksize(pfmt);
334
335 debug_assert(fmt != ~0);
336
337 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
338 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
339 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) |
340 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
341 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
342 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
343 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0);
344
345 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
346 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
347 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
348 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
349 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
350 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
351 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
352 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
353 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
354
355 total_in += vp->inputs[i].ncomp;
356 j++;
357 }
358 }
359
360 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
361 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
362 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
363 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
364 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
365 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
366 A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
367 A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
368 }
369
370 void
371 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
372 struct fd_program_stateobj *prog, uint32_t dirty,
373 struct fd3_shader_key key)
374 {
375 struct fd3_shader_variant *vp;
376 struct fd3_shader_variant *fp;
377
378 fp = fd3_shader_variant(prog->fp, key);
379 vp = fd3_shader_variant(prog->vp, key);
380
381 emit_marker(ring, 5);
382
383 if (dirty & FD_DIRTY_SAMPLE_MASK) {
384 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
385 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
386 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
387 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
388 }
389
390 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !key.binning_pass) {
391 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control;
392
393 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
394 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
395 A3XX_RB_RENDER_CONTROL_YCOORD |
396 A3XX_RB_RENDER_CONTROL_ZCOORD |
397 A3XX_RB_RENDER_CONTROL_WCOORD);
398
399 /* I suppose if we needed to (which I don't *think* we need
400 * to), we could emit this for binning pass too. But we
401 * would need to keep a different patch-list for binning
402 * vs render pass.
403 */
404
405 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
406 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
407 }
408
409 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
410 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
411 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
412
413 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
414 OUT_RING(ring, zsa->rb_alpha_ref);
415
416 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
417 OUT_RING(ring, zsa->rb_stencil_control);
418
419 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
420 OUT_RING(ring, zsa->rb_stencilrefmask |
421 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
422 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
423 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
424 }
425
426 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
427 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
428 if (fp->writes_pos) {
429 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
430 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
431 }
432 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
433 OUT_RING(ring, val);
434 }
435
436 if (dirty & FD_DIRTY_RASTERIZER) {
437 struct fd3_rasterizer_stateobj *rasterizer =
438 fd3_rasterizer_stateobj(ctx->rasterizer);
439
440 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
441 OUT_RING(ring, rasterizer->gras_su_mode_control);
442
443 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
444 OUT_RING(ring, rasterizer->gras_su_point_minmax);
445 OUT_RING(ring, rasterizer->gras_su_point_size);
446
447 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
448 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
449 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
450 }
451
452 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
453 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
454 ->gras_cl_clip_cntl;
455 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
456 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
457 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
458 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
459 OUT_RING(ring, val);
460 }
461
462 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
463 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
464 ->pc_prim_vtx_cntl;
465
466 if (!key.binning_pass) {
467 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
468 if (stride_in_vpc > 0)
469 stride_in_vpc = MAX2(stride_in_vpc, 2);
470 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
471 }
472
473 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
474
475 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
476 OUT_RING(ring, val);
477 }
478
479 if (dirty & FD_DIRTY_SCISSOR) {
480 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
481
482 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
483 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
484 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
485 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
486 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
487
488 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
489 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
490 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
491 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
492 }
493
494 if (dirty & FD_DIRTY_VIEWPORT) {
495 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
496 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
497 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
498 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
499 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
500 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
501 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
502 }
503
504 if (dirty & FD_DIRTY_PROG) {
505 fd_wfi(ctx, ring);
506 fd3_program_emit(ring, prog, key);
507 }
508
509 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
510 OUT_RING(ring, HLSQ_FLUSH);
511
512 if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
513 /* evil hack to deal sanely with clear path: */
514 (prog == &ctx->prog)) {
515 fd_wfi(ctx, ring);
516 emit_constants(ring, SB_VERT_SHADER,
517 &ctx->constbuf[PIPE_SHADER_VERTEX],
518 (prog->dirty & FD_SHADER_DIRTY_VP) ? vp : NULL);
519 if (!key.binning_pass) {
520 emit_constants(ring, SB_FRAG_SHADER,
521 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
522 (prog->dirty & FD_SHADER_DIRTY_FP) ? fp : NULL);
523 }
524 }
525
526 if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
527 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
528 uint32_t i;
529
530 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
531 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
532 OUT_RING(ring, blend->rb_mrt[i].control);
533
534 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
535 OUT_RING(ring, blend->rb_mrt[i].blend_control);
536 }
537 }
538
539 if (dirty & FD_DIRTY_BLEND_COLOR) {
540 struct pipe_blend_color *bcolor = &ctx->blend_color;
541 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
542 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
543 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
544 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
545 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
546 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
547 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
548 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
549 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
550 }
551
552 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
553 fd_wfi(ctx, ring);
554
555 if (dirty & FD_DIRTY_VERTTEX) {
556 if (vp->has_samp)
557 emit_textures(ring, SB_VERT_TEX, &ctx->verttex);
558 else
559 dirty &= ~FD_DIRTY_VERTTEX;
560 }
561
562 if (dirty & FD_DIRTY_FRAGTEX) {
563 if (fp->has_samp)
564 emit_textures(ring, SB_FRAG_TEX, &ctx->fragtex);
565 else
566 dirty &= ~FD_DIRTY_FRAGTEX;
567 }
568
569 ctx->dirty &= ~dirty;
570 }
571
572 /* emit setup at begin of new cmdstream buffer (don't rely on previous
573 * state, there could have been a context switch between ioctls):
574 */
575 void
576 fd3_emit_restore(struct fd_context *ctx)
577 {
578 struct fd3_context *fd3_ctx = fd3_context(ctx);
579 struct fd_ringbuffer *ring = ctx->ring;
580 int i;
581
582 if (ctx->screen->gpu_id == 320) {
583 OUT_PKT3(ring, CP_REG_RMW, 3);
584 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
585 OUT_RING(ring, 0xfffcffff);
586 OUT_RING(ring, 0x00000000);
587 }
588
589 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
590 OUT_RING(ring, 0x00007fff);
591
592 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
593 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
594 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
595 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
596
597 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
598 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
599 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
600 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
601
602 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
603 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
604
605 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
606 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
607 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
608 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
609
610 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
611 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
612 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
613 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
614 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
615
616 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
617 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
618 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
619
620 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
621 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
622
623 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
624 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
625 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
626 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
627
628 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
629 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
630 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
631 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
632
633 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
634 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
635 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
636
637 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
638 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
639
640 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
641 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
642
643 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
644 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
645
646 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
647 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
648
649 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
650 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
651
652 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
653 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
654 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
655 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
656 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
657
658 OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
659 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
660 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
661 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
662 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
663
664 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
665 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
666
667 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
668 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
669 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
670
671 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
672 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
673
674 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
675 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
676 A3XX_RB_WINDOW_OFFSET_Y(0));
677
678 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
679 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
680 A3XX_RB_BLEND_RED_FLOAT(0.0));
681 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
682 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
683 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
684 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
685 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
686 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
687
688 for (i = 0; i < 6; i++) {
689 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
690 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
691 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
692 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
693 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
694 }
695
696 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
697 OUT_RING(ring, 0x00000000);
698
699 emit_cache_flush(ring);
700 fd_wfi(ctx, ring);
701
702 ctx->needs_rb_fbd = true;
703 }