2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [MESA_SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [MESA_SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd3_emit_const(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
88 for (i
= 0; i
< sz
; i
++) {
89 OUT_RING(ring
, dwords
[i
]);
94 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, gl_shader_stage type
, boolean write
,
95 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
97 uint32_t anum
= align(num
, 4);
100 debug_assert((regid
% 4) == 0);
102 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + anum
);
103 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
106 CP_LOAD_STATE_0_NUM_UNIT(anum
/2));
107 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 for (i
= 0; i
< num
; i
++) {
113 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
115 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
118 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
122 for (; i
< anum
; i
++)
123 OUT_RING(ring
, 0xffffffff);
126 #define VERT_TEX_OFF 0
127 #define FRAG_TEX_OFF 16
128 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
131 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
132 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
134 static const unsigned tex_off
[] = {
135 [SB_VERT_TEX
] = VERT_TEX_OFF
,
136 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
138 static const enum adreno_state_block mipaddr
[] = {
139 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
140 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
142 static const uint32_t bcolor_reg
[] = {
143 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
144 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
146 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
147 bool needs_border
= false;
150 if (tex
->num_samplers
> 0) {
151 /* output sampler state: */
152 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
153 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
154 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
155 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
156 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
157 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
158 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
159 for (i
= 0; i
< tex
->num_samplers
; i
++) {
160 static const struct fd3_sampler_stateobj dummy_sampler
= {};
161 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
162 fd3_sampler_stateobj(tex
->samplers
[i
]) :
165 OUT_RING(ring
, sampler
->texsamp0
);
166 OUT_RING(ring
, sampler
->texsamp1
);
168 needs_border
|= sampler
->needs_border
;
172 if (tex
->num_textures
> 0) {
173 /* emit texture state: */
174 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
175 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
176 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
177 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
178 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
179 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
180 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
181 for (i
= 0; i
< tex
->num_textures
; i
++) {
182 static const struct fd3_pipe_sampler_view dummy_view
= {};
183 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
184 fd3_pipe_sampler_view(tex
->textures
[i
]) :
186 OUT_RING(ring
, view
->texconst0
);
187 OUT_RING(ring
, view
->texconst1
);
188 OUT_RING(ring
, view
->texconst2
|
189 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
190 OUT_RING(ring
, view
->texconst3
);
194 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
195 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
196 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
197 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
198 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
199 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
200 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
201 for (i
= 0; i
< tex
->num_textures
; i
++) {
202 static const struct fd3_pipe_sampler_view dummy_view
= {
203 .base
.target
= PIPE_TEXTURE_1D
, /* anything !PIPE_BUFFER */
204 .base
.u
.tex
.first_level
= 1,
206 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
207 fd3_pipe_sampler_view(tex
->textures
[i
]) :
209 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
210 if (rsc
&& rsc
->base
.target
== PIPE_BUFFER
) {
211 OUT_RELOC(ring
, rsc
->bo
, view
->base
.u
.buf
.offset
, 0, 0);
214 unsigned start
= fd_sampler_first_level(&view
->base
);
215 unsigned end
= fd_sampler_last_level(&view
->base
);
217 for (j
= 0; j
< (end
- start
+ 1); j
++) {
218 struct fd_resource_slice
*slice
=
219 fd_resource_slice(rsc
, j
+ start
);
220 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
224 /* pad the remaining entries w/ null: */
225 for (; j
< BASETABLE_SZ
; j
++) {
226 OUT_RING(ring
, 0x00000000);
235 u_upload_alloc(fd3_ctx
->border_color_uploader
,
236 0, BORDER_COLOR_UPLOAD_SIZE
,
237 BORDER_COLOR_UPLOAD_SIZE
, &off
,
238 &fd3_ctx
->border_color_buf
,
241 fd_setup_border_colors(tex
, ptr
, tex_off
[sb
]);
243 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
244 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
246 u_upload_unmap(fd3_ctx
->border_color_uploader
);
250 /* emit texture state for mem->gmem restore operation.. eventually it would
251 * be good to get rid of this and use normal CSO/etc state for more of these
252 * special cases, but for now the compiler is not sufficient..
254 * Also, for using normal state, not quite sure how to handle the special
255 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
258 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
259 struct pipe_surface
**psurf
,
264 /* output sampler state: */
265 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
266 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
267 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
268 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
269 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
270 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
271 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
272 for (i
= 0; i
< bufs
; i
++) {
273 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
274 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
275 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
276 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
277 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
278 OUT_RING(ring
, 0x00000000);
281 /* emit texture state: */
282 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
283 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
284 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
285 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
286 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
287 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
288 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
289 for (i
= 0; i
< bufs
; i
++) {
291 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
292 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
293 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
294 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
295 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
296 OUT_RING(ring
, 0x00000000);
297 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
298 OUT_RING(ring
, 0x00000000);
302 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
303 enum pipe_format format
= fd_gmem_restore_format(psurf
[i
]->format
);
304 /* The restore blit_zs shader expects stencil in sampler 0, and depth
307 if (rsc
->stencil
&& i
== 0) {
309 format
= fd_gmem_restore_format(rsc
->base
.format
);
312 /* note: PIPE_BUFFER disallowed for surfaces */
313 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
314 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
316 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
318 OUT_RING(ring
, A3XX_TEX_CONST_0_TILE_MODE(rsc
->tile_mode
) |
319 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
320 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
321 fd3_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
322 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
323 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
324 A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
325 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
326 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
327 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
328 OUT_RING(ring
, 0x00000000);
332 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
333 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
334 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
335 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
336 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
337 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
338 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
339 for (i
= 0; i
< bufs
; i
++) {
341 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
342 /* Matches above logic for blit_zs shader */
343 if (rsc
->stencil
&& i
== 0)
345 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
346 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
347 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
349 OUT_RING(ring
, 0x00000000);
352 /* pad the remaining entries w/ null: */
353 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
354 OUT_RING(ring
, 0x00000000);
360 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
362 int32_t i
, j
, last
= -1;
363 uint32_t total_in
= 0;
364 const struct fd_vertex_state
*vtx
= emit
->vtx
;
365 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
366 unsigned vertex_regid
= regid(63, 0);
367 unsigned instance_regid
= regid(63, 0);
368 unsigned vtxcnt_regid
= regid(63, 0);
370 /* Note that sysvals come *after* normal inputs: */
371 for (i
= 0; i
< vp
->inputs_count
; i
++) {
372 if (!vp
->inputs
[i
].compmask
)
374 if (vp
->inputs
[i
].sysval
) {
375 switch(vp
->inputs
[i
].slot
) {
376 case SYSTEM_VALUE_FIRST_VERTEX
:
377 /* handled elsewhere */
379 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
380 vertex_regid
= vp
->inputs
[i
].regid
;
382 case SYSTEM_VALUE_INSTANCE_ID
:
383 instance_regid
= vp
->inputs
[i
].regid
;
385 case SYSTEM_VALUE_VERTEX_CNT
:
386 vtxcnt_regid
= vp
->inputs
[i
].regid
;
389 unreachable("invalid system value");
392 } else if (i
< vtx
->vtx
->num_elements
) {
397 for (i
= 0, j
= 0; i
<= last
; i
++) {
398 assert(!vp
->inputs
[i
].sysval
);
399 if (vp
->inputs
[i
].compmask
) {
400 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
401 const struct pipe_vertex_buffer
*vb
=
402 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
403 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
404 enum pipe_format pfmt
= elem
->src_format
;
405 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
406 bool switchnext
= (i
!= last
) ||
407 (vertex_regid
!= regid(63, 0)) ||
408 (instance_regid
!= regid(63, 0)) ||
409 (vtxcnt_regid
!= regid(63, 0));
410 bool isint
= util_format_is_pure_integer(pfmt
);
411 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
412 uint32_t fs
= util_format_get_blocksize(pfmt
);
415 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
416 * should mesa/st be protecting us from this?
418 if (off
> fd_bo_size(rsc
->bo
))
422 debug_assert(fmt
!= ~0);
424 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
425 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
426 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
427 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
428 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
429 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
430 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
431 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
433 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
434 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
435 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
436 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
437 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
438 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
439 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
440 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
441 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
442 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
444 total_in
+= util_bitcount(vp
->inputs
[i
].compmask
);
449 /* hw doesn't like to be configured for zero vbo's, it seems: */
451 /* just recycle the shader bo, we just need to point to *something*
454 struct fd_bo
*dummy_vbo
= vp
->bo
;
455 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
456 (instance_regid
!= regid(63, 0)) ||
457 (vtxcnt_regid
!= regid(63, 0));
459 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(0), 2);
460 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
461 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
462 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
463 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
464 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
465 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
467 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(0), 1);
468 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
469 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
470 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM
) |
471 A3XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
472 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
473 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
474 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
475 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
481 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
482 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
483 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
484 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
485 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
486 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
487 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
488 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
490 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
491 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
492 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
496 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
497 struct fd3_emit
*emit
)
499 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
500 const struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
501 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
503 emit_marker(ring
, 5);
505 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
506 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
507 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
508 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
509 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
512 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
| FD_DIRTY_BLEND_DUAL
)) &&
513 !emit
->binning_pass
) {
514 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
|
515 fd3_blend_stateobj(ctx
->blend
)->rb_render_control
;
517 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
518 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
519 A3XX_RB_RENDER_CONTROL_YCOORD
|
520 A3XX_RB_RENDER_CONTROL_ZCOORD
|
521 A3XX_RB_RENDER_CONTROL_WCOORD
);
523 /* I suppose if we needed to (which I don't *think* we need
524 * to), we could emit this for binning pass too. But we
525 * would need to keep a different patch-list for binning
529 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
530 OUT_RINGP(ring
, val
, &ctx
->batch
->rbrc_patches
);
533 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
534 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
535 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
537 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
538 OUT_RING(ring
, zsa
->rb_alpha_ref
);
540 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
541 OUT_RING(ring
, zsa
->rb_stencil_control
);
543 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
544 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
545 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
546 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
547 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
550 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
551 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
552 if (fp
->writes_pos
) {
553 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
554 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
557 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
559 if (!ctx
->rasterizer
->depth_clip_near
) {
560 val
|= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
;
562 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
566 if (dirty
& FD_DIRTY_RASTERIZER
) {
567 struct fd3_rasterizer_stateobj
*rasterizer
=
568 fd3_rasterizer_stateobj(ctx
->rasterizer
);
570 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
571 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
573 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
574 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
575 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
577 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
578 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
579 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
582 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
583 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
585 uint8_t planes
= ctx
->rasterizer
->clip_plane_enable
;
586 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
587 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
588 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
589 if (!emit
->key
.ucp_enables
)
590 val
|= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
591 MIN2(util_bitcount(planes
), 6));
592 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
596 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
| FD_DIRTY_UCP
)) {
597 uint32_t planes
= ctx
->rasterizer
->clip_plane_enable
;
600 if (emit
->key
.ucp_enables
)
603 while (planes
&& count
< 6) {
604 int i
= ffs(planes
) - 1;
606 planes
&= ~(1U << i
);
607 fd_wfi(ctx
->batch
, ring
);
608 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(count
++), 4);
609 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][0]));
610 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][1]));
611 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][2]));
612 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][3]));
616 /* NOTE: since primitive_restart is not actually part of any
617 * state object, we need to make sure that we always emit
618 * PRIM_VTX_CNTL.. either that or be more clever and detect
622 const struct pipe_draw_info
*info
= emit
->info
;
623 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
626 if (!emit
->binning_pass
) {
627 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
628 if (stride_in_vpc
> 0)
629 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
630 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
633 if (info
->index_size
&& info
->primitive_restart
) {
634 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
637 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
639 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
643 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
| FD_DIRTY_VIEWPORT
)) {
644 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
645 int minx
= scissor
->minx
;
646 int miny
= scissor
->miny
;
647 int maxx
= scissor
->maxx
;
648 int maxy
= scissor
->maxy
;
650 /* Unfortunately there is no separate depth clip disable, only an all
651 * or nothing deal. So when we disable clipping, we must handle the
652 * viewport clip via scissors.
654 if (!ctx
->rasterizer
->depth_clip_near
) {
655 struct pipe_viewport_state
*vp
= &ctx
->viewport
;
656 minx
= MAX2(minx
, (int)floorf(vp
->translate
[0] - fabsf(vp
->scale
[0])));
657 miny
= MAX2(miny
, (int)floorf(vp
->translate
[1] - fabsf(vp
->scale
[1])));
658 maxx
= MIN2(maxx
, (int)ceilf(vp
->translate
[0] + fabsf(vp
->scale
[0])));
659 maxy
= MIN2(maxy
, (int)ceilf(vp
->translate
[1] + fabsf(vp
->scale
[1])));
662 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
663 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx
) |
664 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny
));
665 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx
- 1) |
666 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy
- 1));
668 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, minx
);
669 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, miny
);
670 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, maxx
);
671 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, maxy
);
674 if (dirty
& FD_DIRTY_VIEWPORT
) {
675 fd_wfi(ctx
->batch
, ring
);
676 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
677 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
678 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
679 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
680 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
681 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
682 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
685 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
688 if (ctx
->batch
->framebuffer
.zsbuf
) {
689 depth
= util_format_get_component_bits(
690 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
691 UTIL_FORMAT_COLORSPACE_ZS
, 0);
693 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
696 OUT_PKT0(ring
, REG_A3XX_RB_Z_CLAMP_MIN
, 2);
698 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffffff));
699 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffffff));
700 } else if (depth
== 16) {
701 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
702 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
704 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
705 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
709 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_BLEND_DUAL
)) {
710 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
711 int nr_cbufs
= pfb
->nr_cbufs
;
712 if (fd3_blend_stateobj(ctx
->blend
)->rb_render_control
&
713 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE
)
715 fd3_program_emit(ring
, emit
, nr_cbufs
, pfb
->cbufs
);
718 /* TODO we should not need this or fd_wfi() before emit_constants():
720 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
721 OUT_RING(ring
, HLSQ_FLUSH
);
723 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
724 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
725 if (!emit
->binning_pass
)
726 ir3_emit_fs_consts(fp
, ring
, ctx
);
729 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) {
730 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
733 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
734 enum pipe_format format
=
735 pipe_surface_format(ctx
->batch
->framebuffer
.cbufs
[i
]);
736 const struct util_format_description
*desc
=
737 util_format_description(format
);
738 bool is_float
= util_format_is_float(format
);
739 bool is_int
= util_format_is_pure_integer(format
);
740 bool has_alpha
= util_format_has_alpha(format
);
741 uint32_t control
= blend
->rb_mrt
[i
].control
;
742 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
745 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
746 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
747 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
750 if (format
== PIPE_FORMAT_NONE
)
751 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
754 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
756 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
757 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
760 if (format
&& util_format_get_component_bits(
761 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
762 const struct pipe_rt_blend_state
*rt
;
763 if (ctx
->blend
->independent_blend_enable
)
764 rt
= &ctx
->blend
->rt
[i
];
766 rt
= &ctx
->blend
->rt
[0];
768 if (!util_format_colormask_full(desc
, rt
->colormask
))
769 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
772 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
773 OUT_RING(ring
, control
);
775 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
776 OUT_RING(ring
, blend_control
|
777 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
781 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
782 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
783 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
784 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
785 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
786 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
787 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
788 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
789 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
790 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
791 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
794 if (dirty
& FD_DIRTY_TEX
)
795 fd_wfi(ctx
->batch
, ring
);
797 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
)
798 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->tex
[PIPE_SHADER_VERTEX
]);
800 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
)
801 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
804 /* emit setup at begin of new cmdstream buffer (don't rely on previous
805 * state, there could have been a context switch between ioctls):
808 fd3_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
810 struct fd_context
*ctx
= batch
->ctx
;
811 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
814 if (ctx
->screen
->gpu_id
== 320) {
815 OUT_PKT3(ring
, CP_REG_RMW
, 3);
816 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
817 OUT_RING(ring
, 0xfffcffff);
818 OUT_RING(ring
, 0x00000000);
822 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
823 OUT_RING(ring
, 0x00007fff);
825 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
826 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
827 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
828 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
830 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
831 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
832 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
833 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
835 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
836 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
838 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
839 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
840 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
841 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
843 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
844 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
845 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
846 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
847 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
849 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
850 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
851 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
853 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
854 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
856 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
857 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
858 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
859 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
861 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
862 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
863 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
864 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
866 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
867 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
868 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
870 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
871 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
873 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
874 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
876 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
877 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
879 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
880 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
882 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
883 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
885 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
886 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
887 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
888 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
889 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
891 fd3_emit_cache_flush(batch
, ring
);
893 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
894 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
896 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
897 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
898 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
900 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
901 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
903 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
904 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
905 A3XX_RB_WINDOW_OFFSET_Y(0));
907 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
908 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
909 A3XX_RB_BLEND_RED_FLOAT(0.0));
910 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
911 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
912 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
913 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
914 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
915 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
917 for (i
= 0; i
< 6; i
++) {
918 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
919 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
920 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
921 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
922 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
925 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
926 OUT_RING(ring
, 0x00000000);
928 fd_event_write(batch
, ring
, CACHE_FLUSH
);
930 if (is_a3xx_p0(ctx
->screen
)) {
931 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
932 OUT_RING(ring
, 0x00000000);
933 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
934 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
935 OUT_RING(ring
, 0); /* NumIndices */
938 OUT_PKT3(ring
, CP_NOP
, 4);
939 OUT_RING(ring
, 0x00000000);
940 OUT_RING(ring
, 0x00000000);
941 OUT_RING(ring
, 0x00000000);
942 OUT_RING(ring
, 0x00000000);
946 fd_hw_query_enable(batch
, ring
);
950 fd3_emit_init_screen(struct pipe_screen
*pscreen
)
952 struct fd_screen
*screen
= fd_screen(pscreen
);
953 screen
->emit_const
= fd3_emit_const
;
954 screen
->emit_const_bo
= fd3_emit_const_bo
;
955 screen
->emit_ib
= fd3_emit_ib
;
959 fd3_emit_init(struct pipe_context
*pctx
)