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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = SS_INDIRECT;
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/2));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
126
127 static void
128 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
129 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
130 {
131 static const unsigned tex_off[] = {
132 [SB_VERT_TEX] = VERT_TEX_OFF,
133 [SB_FRAG_TEX] = FRAG_TEX_OFF,
134 };
135 static const enum adreno_state_block mipaddr[] = {
136 [SB_VERT_TEX] = SB_VERT_MIPADDR,
137 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
138 };
139 static const uint32_t bcolor_reg[] = {
140 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
141 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
142 };
143 struct fd3_context *fd3_ctx = fd3_context(ctx);
144 unsigned i, j, off;
145 void *ptr;
146
147 u_upload_alloc(fd3_ctx->border_color_uploader,
148 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
149 &fd3_ctx->border_color_buf,
150 &ptr);
151
152 if (tex->num_samplers > 0) {
153 /* output sampler state: */
154 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
155 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
156 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
157 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
158 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
159 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
160 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
161 for (i = 0; i < tex->num_samplers; i++) {
162 static const struct fd3_sampler_stateobj dummy_sampler = {};
163 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
164 fd3_sampler_stateobj(tex->samplers[i]) :
165 &dummy_sampler;
166 uint16_t *bcolor = (uint16_t *)((uint8_t *)ptr +
167 (BORDERCOLOR_SIZE * tex_off[sb]) +
168 (BORDERCOLOR_SIZE * i));
169 uint32_t *bcolor32 = (uint32_t *)&bcolor[16];
170
171 /*
172 * XXX HACK ALERT XXX
173 *
174 * The border colors need to be swizzled in a particular
175 * format-dependent order. Even though samplers don't know about
176 * formats, we can assume that with a GL state tracker, there's a
177 * 1:1 correspondence between sampler and texture. Take advantage
178 * of that knowledge.
179 */
180 if (i < tex->num_textures && tex->textures[i]) {
181 const struct util_format_description *desc =
182 util_format_description(tex->textures[i]->format);
183 for (j = 0; j < 4; j++) {
184 if (desc->swizzle[j] >= 4)
185 continue;
186
187 const struct util_format_channel_description *chan =
188 &desc->channel[desc->swizzle[j]];
189 int size = chan->size;
190
191 /* The Z16 texture format we use seems to look in the
192 * 32-bit border color slots
193 */
194 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
195 size = 32;
196
197 /* Formats like R11G11B10 or RGB9_E5 don't specify
198 * per-channel sizes properly.
199 */
200 if (desc->layout == UTIL_FORMAT_LAYOUT_OTHER)
201 size = 16;
202
203 if (chan->pure_integer && size > 16)
204 bcolor32[desc->swizzle[j] + 4] =
205 sampler->base.border_color.i[j];
206 else if (size > 16)
207 bcolor32[desc->swizzle[j]] =
208 fui(sampler->base.border_color.f[j]);
209 else if (chan->pure_integer)
210 bcolor[desc->swizzle[j] + 8] =
211 sampler->base.border_color.i[j];
212 else
213 bcolor[desc->swizzle[j]] =
214 util_float_to_half(sampler->base.border_color.f[j]);
215 }
216 }
217
218 OUT_RING(ring, sampler->texsamp0);
219 OUT_RING(ring, sampler->texsamp1);
220 }
221 }
222
223 if (tex->num_textures > 0) {
224 /* emit texture state: */
225 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
226 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
227 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
228 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
229 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
230 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
231 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
232 for (i = 0; i < tex->num_textures; i++) {
233 static const struct fd3_pipe_sampler_view dummy_view = {};
234 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
235 fd3_pipe_sampler_view(tex->textures[i]) :
236 &dummy_view;
237 OUT_RING(ring, view->texconst0);
238 OUT_RING(ring, view->texconst1);
239 OUT_RING(ring, view->texconst2 |
240 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
241 OUT_RING(ring, view->texconst3);
242 }
243
244 /* emit mipaddrs: */
245 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
246 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
247 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
248 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
249 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
250 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
251 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
252 for (i = 0; i < tex->num_textures; i++) {
253 static const struct fd3_pipe_sampler_view dummy_view = {
254 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
255 .base.u.tex.first_level = 1,
256 };
257 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
258 fd3_pipe_sampler_view(tex->textures[i]) :
259 &dummy_view;
260 struct fd_resource *rsc = fd_resource(view->base.texture);
261 unsigned start = fd_sampler_first_level(&view->base);
262 unsigned end = fd_sampler_last_level(&view->base);;
263
264 for (j = 0; j < (end - start + 1); j++) {
265 struct fd_resource_slice *slice =
266 fd_resource_slice(rsc, j + start);
267 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
268 }
269
270 /* pad the remaining entries w/ null: */
271 for (; j < BASETABLE_SZ; j++) {
272 OUT_RING(ring, 0x00000000);
273 }
274 }
275 }
276
277 OUT_PKT0(ring, bcolor_reg[sb], 1);
278 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
279
280 u_upload_unmap(fd3_ctx->border_color_uploader);
281 }
282
283 /* emit texture state for mem->gmem restore operation.. eventually it would
284 * be good to get rid of this and use normal CSO/etc state for more of these
285 * special cases, but for now the compiler is not sufficient..
286 *
287 * Also, for using normal state, not quite sure how to handle the special
288 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
289 */
290 void
291 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
292 struct pipe_surface **psurf,
293 int bufs)
294 {
295 int i, j;
296
297 /* output sampler state: */
298 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
299 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
300 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
301 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
302 CP_LOAD_STATE_0_NUM_UNIT(bufs));
303 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
304 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
305 for (i = 0; i < bufs; i++) {
306 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
307 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
308 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
309 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
310 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
311 OUT_RING(ring, 0x00000000);
312 }
313
314 /* emit texture state: */
315 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
316 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
317 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
318 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
319 CP_LOAD_STATE_0_NUM_UNIT(bufs));
320 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
321 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
322 for (i = 0; i < bufs; i++) {
323 if (!psurf[i]) {
324 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
325 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
326 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
327 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
328 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
329 OUT_RING(ring, 0x00000000);
330 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
331 OUT_RING(ring, 0x00000000);
332 continue;
333 }
334
335 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
336 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
337 /* The restore blit_zs shader expects stencil in sampler 0, and depth
338 * in sampler 1
339 */
340 if (rsc->stencil && i == 0) {
341 rsc = rsc->stencil;
342 format = fd3_gmem_restore_format(rsc->base.b.format);
343 }
344
345 /* note: PIPE_BUFFER disallowed for surfaces */
346 unsigned lvl = psurf[i]->u.tex.level;
347 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
348
349 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
350
351 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
352 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
353 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
354 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
355 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
356 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
357 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
358 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
359 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
360 OUT_RING(ring, 0x00000000);
361 }
362
363 /* emit mipaddrs: */
364 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
365 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
366 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
367 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
368 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
369 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
370 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
371 for (i = 0; i < bufs; i++) {
372 if (psurf[i]) {
373 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
374 /* Matches above logic for blit_zs shader */
375 if (rsc->stencil && i == 0)
376 rsc = rsc->stencil;
377 unsigned lvl = psurf[i]->u.tex.level;
378 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
379 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
380 } else {
381 OUT_RING(ring, 0x00000000);
382 }
383
384 /* pad the remaining entries w/ null: */
385 for (j = 1; j < BASETABLE_SZ; j++) {
386 OUT_RING(ring, 0x00000000);
387 }
388 }
389 }
390
391 void
392 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
393 {
394 int32_t i, j, last = -1;
395 uint32_t total_in = 0;
396 const struct fd_vertex_state *vtx = emit->vtx;
397 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
398 unsigned vertex_regid = regid(63, 0);
399 unsigned instance_regid = regid(63, 0);
400 unsigned vtxcnt_regid = regid(63, 0);
401
402 for (i = 0; i < vp->inputs_count; i++) {
403 uint8_t semantic = sem2name(vp->inputs[i].semantic);
404 if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
405 vertex_regid = vp->inputs[i].regid;
406 else if (semantic == TGSI_SEMANTIC_INSTANCEID)
407 instance_regid = vp->inputs[i].regid;
408 else if (semantic == IR3_SEMANTIC_VTXCNT)
409 vtxcnt_regid = vp->inputs[i].regid;
410 else if (i < vtx->vtx->num_elements && vp->inputs[i].compmask)
411 last = i;
412 }
413
414 /* hw doesn't like to be configured for zero vbo's, it seems: */
415 if ((vtx->vtx->num_elements == 0) &&
416 (vertex_regid == regid(63, 0)) &&
417 (instance_regid == regid(63, 0)) &&
418 (vtxcnt_regid == regid(63, 0)))
419 return;
420
421 for (i = 0, j = 0; i <= last; i++) {
422 assert(sem2name(vp->inputs[i].semantic) == 0);
423 if (vp->inputs[i].compmask) {
424 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
425 const struct pipe_vertex_buffer *vb =
426 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
427 struct fd_resource *rsc = fd_resource(vb->buffer);
428 enum pipe_format pfmt = elem->src_format;
429 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
430 bool switchnext = (i != last) ||
431 (vertex_regid != regid(63, 0)) ||
432 (instance_regid != regid(63, 0)) ||
433 (vtxcnt_regid != regid(63, 0));
434 bool isint = util_format_is_pure_integer(pfmt);
435 uint32_t fs = util_format_get_blocksize(pfmt);
436
437 debug_assert(fmt != ~0);
438
439 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
440 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
441 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
442 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
443 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
444 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
445 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
446 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
447
448 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
449 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
450 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
451 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
452 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
453 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
454 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
455 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
456 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
457 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
458
459 total_in += vp->inputs[i].ncomp;
460 j++;
461 }
462 }
463
464 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
465 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
466 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
467 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
468 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
469 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
470 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
471 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
472
473 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
474 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
475 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
476 }
477
478 void
479 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
480 struct fd3_emit *emit)
481 {
482 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
483 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
484 uint32_t dirty = emit->dirty;
485
486 emit_marker(ring, 5);
487
488 if (dirty & FD_DIRTY_SAMPLE_MASK) {
489 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
490 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
491 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
492 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
493 }
494
495 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
496 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control;
497
498 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
499 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
500 A3XX_RB_RENDER_CONTROL_YCOORD |
501 A3XX_RB_RENDER_CONTROL_ZCOORD |
502 A3XX_RB_RENDER_CONTROL_WCOORD);
503
504 /* I suppose if we needed to (which I don't *think* we need
505 * to), we could emit this for binning pass too. But we
506 * would need to keep a different patch-list for binning
507 * vs render pass.
508 */
509
510 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
511 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
512 }
513
514 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
515 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
516 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
517
518 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
519 OUT_RING(ring, zsa->rb_alpha_ref);
520
521 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
522 OUT_RING(ring, zsa->rb_stencil_control);
523
524 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
525 OUT_RING(ring, zsa->rb_stencilrefmask |
526 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
527 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
528 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
529 }
530
531 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
532 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
533 if (fp->writes_pos) {
534 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
535 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
536 }
537 if (fp->has_kill) {
538 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
539 }
540 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
541 OUT_RING(ring, val);
542 }
543
544 if (dirty & FD_DIRTY_RASTERIZER) {
545 struct fd3_rasterizer_stateobj *rasterizer =
546 fd3_rasterizer_stateobj(ctx->rasterizer);
547
548 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
549 OUT_RING(ring, rasterizer->gras_su_mode_control);
550
551 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
552 OUT_RING(ring, rasterizer->gras_su_point_minmax);
553 OUT_RING(ring, rasterizer->gras_su_point_size);
554
555 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
556 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
557 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
558 }
559
560 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
561 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
562 ->gras_cl_clip_cntl;
563 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
564 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
565 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
566 /* TODO only use if prog doesn't use clipvertex/clipdist */
567 val |= MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6) << 26;
568 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
569 OUT_RING(ring, val);
570 }
571
572 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
573 uint32_t planes = ctx->rasterizer->clip_plane_enable;
574 int count = 0;
575
576 while (planes && count < 6) {
577 int i = ffs(planes) - 1;
578
579 planes &= ~(1U << i);
580 fd_wfi(ctx, ring);
581 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
582 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
583 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
584 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
585 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
586 }
587 }
588
589 /* NOTE: since primitive_restart is not actually part of any
590 * state object, we need to make sure that we always emit
591 * PRIM_VTX_CNTL.. either that or be more clever and detect
592 * when it changes.
593 */
594 if (emit->info) {
595 const struct pipe_draw_info *info = emit->info;
596 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
597 ->pc_prim_vtx_cntl;
598
599 if (!emit->key.binning_pass) {
600 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
601 if (stride_in_vpc > 0)
602 stride_in_vpc = MAX2(stride_in_vpc, 2);
603 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
604 }
605
606 if (info->indexed && info->primitive_restart) {
607 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
608 }
609
610 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
611
612 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
613 OUT_RING(ring, val);
614 }
615
616 if (dirty & FD_DIRTY_SCISSOR) {
617 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
618
619 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
620 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
621 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
622 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
623 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
624
625 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
626 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
627 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
628 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
629 }
630
631 if (dirty & FD_DIRTY_VIEWPORT) {
632 fd_wfi(ctx, ring);
633 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
634 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
635 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
636 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
637 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
638 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
639 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
640 }
641
642 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
643 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
644 fd3_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
645 }
646
647 /* TODO we should not need this or fd_wfi() before emit_constants():
648 */
649 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
650 OUT_RING(ring, HLSQ_FLUSH);
651
652 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
653 ir3_emit_consts(vp, ring, emit->info, dirty);
654 if (!emit->key.binning_pass)
655 ir3_emit_consts(fp, ring, emit->info, dirty);
656 /* mark clean after emitting consts: */
657 ctx->prog.dirty = 0;
658 }
659
660 if ((dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) && ctx->blend) {
661 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
662 uint32_t i;
663
664 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
665 enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
666 const struct util_format_description *desc =
667 util_format_description(format);
668 bool is_float = util_format_is_float(format);
669 bool is_int = util_format_is_pure_integer(format);
670 bool has_alpha = util_format_has_alpha(format);
671 uint32_t control = blend->rb_mrt[i].control;
672 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
673
674 if (is_int) {
675 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
676 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
677 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
678 }
679
680 if (format == PIPE_FORMAT_NONE)
681 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
682
683 if (has_alpha) {
684 blend_control |= blend->rb_mrt[i].blend_control_rgb;
685 } else {
686 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
687 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
688 }
689
690 if (format && util_format_get_component_bits(
691 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
692 const struct pipe_rt_blend_state *rt;
693 if (ctx->blend->independent_blend_enable)
694 rt = &ctx->blend->rt[i];
695 else
696 rt = &ctx->blend->rt[0];
697
698 if (!util_format_colormask_full(desc, rt->colormask))
699 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
700 }
701
702 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
703 OUT_RING(ring, control);
704
705 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
706 OUT_RING(ring, blend_control |
707 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
708 }
709 }
710
711 if (dirty & FD_DIRTY_BLEND_COLOR) {
712 struct pipe_blend_color *bcolor = &ctx->blend_color;
713 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
714 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
715 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
716 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
717 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
718 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
719 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
720 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
721 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
722 }
723
724 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
725 fd_wfi(ctx, ring);
726
727 if (dirty & FD_DIRTY_VERTTEX) {
728 if (vp->has_samp)
729 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
730 else
731 dirty &= ~FD_DIRTY_VERTTEX;
732 }
733
734 if (dirty & FD_DIRTY_FRAGTEX) {
735 if (fp->has_samp)
736 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
737 else
738 dirty &= ~FD_DIRTY_FRAGTEX;
739 }
740
741 ctx->dirty &= ~dirty;
742 }
743
744 /* emit setup at begin of new cmdstream buffer (don't rely on previous
745 * state, there could have been a context switch between ioctls):
746 */
747 void
748 fd3_emit_restore(struct fd_context *ctx)
749 {
750 struct fd3_context *fd3_ctx = fd3_context(ctx);
751 struct fd_ringbuffer *ring = ctx->ring;
752 int i;
753
754 if (ctx->screen->gpu_id == 320) {
755 OUT_PKT3(ring, CP_REG_RMW, 3);
756 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
757 OUT_RING(ring, 0xfffcffff);
758 OUT_RING(ring, 0x00000000);
759 }
760
761 fd_wfi(ctx, ring);
762 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
763 OUT_RING(ring, 0x00007fff);
764
765 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
766 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
767 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
768 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
769
770 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
771 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
772 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
773 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
774
775 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
776 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
777
778 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
779 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
780 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
781 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
782
783 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
784 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
785 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
786 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
787 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
788
789 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
790 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
791 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
792
793 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
794 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
795
796 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
797 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
798 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
799 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
800
801 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
802 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
803 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
804 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
805
806 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
807 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
808 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
809
810 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
811 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
812
813 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
814 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
815
816 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
817 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
818
819 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
820 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
821
822 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
823 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
824
825 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
826 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
827 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
828 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
829 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
830
831 OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
832 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
833 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
834 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
835 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
836
837 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
838 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
839
840 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
841 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
842 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
843
844 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
845 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
846
847 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
848 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
849 A3XX_RB_WINDOW_OFFSET_Y(0));
850
851 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
852 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
853 A3XX_RB_BLEND_RED_FLOAT(0.0));
854 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
855 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
856 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
857 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
858 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
859 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
860
861 for (i = 0; i < 6; i++) {
862 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
863 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
864 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
865 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
866 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
867 }
868
869 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
870 OUT_RING(ring, 0x00000000);
871
872 fd_event_write(ctx, ring, CACHE_FLUSH);
873
874 if (is_a3xx_p0(ctx->screen)) {
875 OUT_PKT3(ring, CP_DRAW_INDX, 3);
876 OUT_RING(ring, 0x00000000);
877 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
878 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
879 OUT_RING(ring, 0); /* NumIndices */
880 }
881
882 OUT_PKT3(ring, CP_NOP, 4);
883 OUT_RING(ring, 0x00000000);
884 OUT_RING(ring, 0x00000000);
885 OUT_RING(ring, 0x00000000);
886 OUT_RING(ring, 0x00000000);
887
888 fd_wfi(ctx, ring);
889
890 ctx->needs_rb_fbd = true;
891 }
892
893 void
894 fd3_emit_init(struct pipe_context *pctx)
895 {
896 struct fd_context *ctx = fd_context(pctx);
897 ctx->emit_const = fd3_emit_const;
898 ctx->emit_const_bo = fd3_emit_const_bo;
899 }