1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd3_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
88 for (i
= 0; i
< sz
; i
++) {
89 OUT_RING(ring
, dwords
[i
]);
94 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
95 uint32_t regid
, uint32_t num
, struct fd_bo
**bos
, uint32_t *offsets
)
99 debug_assert((regid
% 4) == 0);
100 debug_assert((num
% 4) == 0);
102 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
103 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num
/2));
107 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 for (i
= 0; i
< num
; i
++) {
113 OUT_RELOCW(ring
, bos
[i
], offsets
[i
], 0, 0);
115 OUT_RELOC(ring
, bos
[i
], offsets
[i
], 0, 0);
118 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
128 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
129 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
131 static const unsigned tex_off
[] = {
132 [SB_VERT_TEX
] = VERT_TEX_OFF
,
133 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
135 static const enum adreno_state_block mipaddr
[] = {
136 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
137 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
139 static const uint32_t bcolor_reg
[] = {
140 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
141 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
143 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
147 u_upload_alloc(fd3_ctx
->border_color_uploader
,
148 0, 2 * PIPE_MAX_SAMPLERS
* BORDERCOLOR_SIZE
, &off
,
149 &fd3_ctx
->border_color_buf
,
152 fd_setup_border_colors(tex
, ptr
, tex_off
[sb
]);
154 if (tex
->num_samplers
> 0) {
155 /* output sampler state: */
156 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
157 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
158 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
159 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
160 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
161 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
162 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
163 for (i
= 0; i
< tex
->num_samplers
; i
++) {
164 static const struct fd3_sampler_stateobj dummy_sampler
= {};
165 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
166 fd3_sampler_stateobj(tex
->samplers
[i
]) :
169 OUT_RING(ring
, sampler
->texsamp0
);
170 OUT_RING(ring
, sampler
->texsamp1
);
174 if (tex
->num_textures
> 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
177 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
181 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i
= 0; i
< tex
->num_textures
; i
++) {
184 static const struct fd3_pipe_sampler_view dummy_view
= {};
185 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
186 fd3_pipe_sampler_view(tex
->textures
[i
]) :
188 OUT_RING(ring
, view
->texconst0
);
189 OUT_RING(ring
, view
->texconst1
);
190 OUT_RING(ring
, view
->texconst2
|
191 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
192 OUT_RING(ring
, view
->texconst3
);
196 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
197 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
198 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
199 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
200 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
201 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
202 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
203 for (i
= 0; i
< tex
->num_textures
; i
++) {
204 static const struct fd3_pipe_sampler_view dummy_view
= {
205 .base
.target
= PIPE_TEXTURE_1D
, /* anything !PIPE_BUFFER */
206 .base
.u
.tex
.first_level
= 1,
208 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
209 fd3_pipe_sampler_view(tex
->textures
[i
]) :
211 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
212 if (rsc
&& rsc
->base
.b
.target
== PIPE_BUFFER
) {
213 OUT_RELOC(ring
, rsc
->bo
, view
->base
.u
.buf
.first_element
*
214 util_format_get_blocksize(view
->base
.format
), 0, 0);
217 unsigned start
= fd_sampler_first_level(&view
->base
);
218 unsigned end
= fd_sampler_last_level(&view
->base
);;
220 for (j
= 0; j
< (end
- start
+ 1); j
++) {
221 struct fd_resource_slice
*slice
=
222 fd_resource_slice(rsc
, j
+ start
);
223 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
227 /* pad the remaining entries w/ null: */
228 for (; j
< BASETABLE_SZ
; j
++) {
229 OUT_RING(ring
, 0x00000000);
234 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
235 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
237 u_upload_unmap(fd3_ctx
->border_color_uploader
);
240 /* emit texture state for mem->gmem restore operation.. eventually it would
241 * be good to get rid of this and use normal CSO/etc state for more of these
242 * special cases, but for now the compiler is not sufficient..
244 * Also, for using normal state, not quite sure how to handle the special
245 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
248 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
249 struct pipe_surface
**psurf
,
254 /* output sampler state: */
255 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
256 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
257 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
258 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
259 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
260 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
261 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
262 for (i
= 0; i
< bufs
; i
++) {
263 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
264 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
265 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
266 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
267 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
268 OUT_RING(ring
, 0x00000000);
271 /* emit texture state: */
272 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
273 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
274 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
275 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
276 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
277 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
278 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
279 for (i
= 0; i
< bufs
; i
++) {
281 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
282 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
283 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
284 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
285 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
286 OUT_RING(ring
, 0x00000000);
287 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
288 OUT_RING(ring
, 0x00000000);
292 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
293 enum pipe_format format
= fd3_gmem_restore_format(psurf
[i
]->format
);
294 /* The restore blit_zs shader expects stencil in sampler 0, and depth
297 if (rsc
->stencil
&& i
== 0) {
299 format
= fd3_gmem_restore_format(rsc
->base
.b
.format
);
302 /* note: PIPE_BUFFER disallowed for surfaces */
303 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
304 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
306 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
308 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
309 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
310 fd3_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
311 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
312 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
313 A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
314 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
315 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
316 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
317 OUT_RING(ring
, 0x00000000);
321 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
322 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
323 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
324 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
325 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
326 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
327 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
328 for (i
= 0; i
< bufs
; i
++) {
330 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
331 /* Matches above logic for blit_zs shader */
332 if (rsc
->stencil
&& i
== 0)
334 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
335 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
336 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
338 OUT_RING(ring
, 0x00000000);
341 /* pad the remaining entries w/ null: */
342 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
343 OUT_RING(ring
, 0x00000000);
349 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
351 int32_t i
, j
, last
= -1;
352 uint32_t total_in
= 0;
353 const struct fd_vertex_state
*vtx
= emit
->vtx
;
354 struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
355 unsigned vertex_regid
= regid(63, 0);
356 unsigned instance_regid
= regid(63, 0);
357 unsigned vtxcnt_regid
= regid(63, 0);
359 /* Note that sysvals come *after* normal inputs: */
360 for (i
= 0; i
< vp
->inputs_count
; i
++) {
361 if (!vp
->inputs
[i
].compmask
)
363 if (vp
->inputs
[i
].sysval
) {
364 switch(vp
->inputs
[i
].slot
) {
365 case SYSTEM_VALUE_BASE_VERTEX
:
366 /* handled elsewhere */
368 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
369 vertex_regid
= vp
->inputs
[i
].regid
;
371 case SYSTEM_VALUE_INSTANCE_ID
:
372 instance_regid
= vp
->inputs
[i
].regid
;
374 case SYSTEM_VALUE_VERTEX_CNT
:
375 vtxcnt_regid
= vp
->inputs
[i
].regid
;
378 unreachable("invalid system value");
381 } else if (i
< vtx
->vtx
->num_elements
) {
386 for (i
= 0, j
= 0; i
<= last
; i
++) {
387 assert(!vp
->inputs
[i
].sysval
);
388 if (vp
->inputs
[i
].compmask
) {
389 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
390 const struct pipe_vertex_buffer
*vb
=
391 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
392 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
393 enum pipe_format pfmt
= elem
->src_format
;
394 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
395 bool switchnext
= (i
!= last
) ||
396 (vertex_regid
!= regid(63, 0)) ||
397 (instance_regid
!= regid(63, 0)) ||
398 (vtxcnt_regid
!= regid(63, 0));
399 bool isint
= util_format_is_pure_integer(pfmt
);
400 uint32_t fs
= util_format_get_blocksize(pfmt
);
402 debug_assert(fmt
!= ~0);
404 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
405 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
406 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
407 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
408 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
409 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
410 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
411 OUT_RELOC(ring
, rsc
->bo
, vb
->buffer_offset
+ elem
->src_offset
, 0, 0);
413 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
414 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
415 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
416 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
417 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
418 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
419 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
420 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
421 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
422 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
424 total_in
+= vp
->inputs
[i
].ncomp
;
429 /* hw doesn't like to be configured for zero vbo's, it seems: */
431 /* just recycle the shader bo, we just need to point to *something*
434 struct fd_bo
*dummy_vbo
= vp
->bo
;
435 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
436 (instance_regid
!= regid(63, 0)) ||
437 (vtxcnt_regid
!= regid(63, 0));
439 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(0), 2);
440 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
441 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
442 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
443 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
444 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
445 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
447 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(0), 1);
448 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
449 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
450 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM
) |
451 A3XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
452 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
453 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
454 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
455 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
461 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
462 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
463 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
464 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
465 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
466 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
467 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
468 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
470 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
471 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
472 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
476 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
477 struct fd3_emit
*emit
)
479 struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
480 struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
481 uint32_t dirty
= emit
->dirty
;
483 emit_marker(ring
, 5);
485 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
486 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
487 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
488 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
489 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
492 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
| FD_DIRTY_BLEND_DUAL
)) &&
493 !emit
->key
.binning_pass
) {
494 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
|
495 fd3_blend_stateobj(ctx
->blend
)->rb_render_control
;
497 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
498 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
499 A3XX_RB_RENDER_CONTROL_YCOORD
|
500 A3XX_RB_RENDER_CONTROL_ZCOORD
|
501 A3XX_RB_RENDER_CONTROL_WCOORD
);
503 /* I suppose if we needed to (which I don't *think* we need
504 * to), we could emit this for binning pass too. But we
505 * would need to keep a different patch-list for binning
509 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
510 OUT_RINGP(ring
, val
, &fd3_context(ctx
)->rbrc_patches
);
513 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
514 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
515 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
517 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
518 OUT_RING(ring
, zsa
->rb_alpha_ref
);
520 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
521 OUT_RING(ring
, zsa
->rb_stencil_control
);
523 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
524 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
525 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
526 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
527 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
530 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
531 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
532 if (fp
->writes_pos
) {
533 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
534 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
537 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
539 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
543 if (dirty
& FD_DIRTY_RASTERIZER
) {
544 struct fd3_rasterizer_stateobj
*rasterizer
=
545 fd3_rasterizer_stateobj(ctx
->rasterizer
);
547 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
548 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
550 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
551 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
552 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
554 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
555 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
556 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
559 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
560 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
562 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
563 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
564 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
565 /* TODO only use if prog doesn't use clipvertex/clipdist */
566 val
|= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
567 MIN2(util_bitcount(ctx
->rasterizer
->clip_plane_enable
), 6));
568 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
572 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_UCP
)) {
573 uint32_t planes
= ctx
->rasterizer
->clip_plane_enable
;
576 while (planes
&& count
< 6) {
577 int i
= ffs(planes
) - 1;
579 planes
&= ~(1U << i
);
581 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(count
++), 4);
582 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][0]));
583 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][1]));
584 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][2]));
585 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][3]));
589 /* NOTE: since primitive_restart is not actually part of any
590 * state object, we need to make sure that we always emit
591 * PRIM_VTX_CNTL.. either that or be more clever and detect
595 const struct pipe_draw_info
*info
= emit
->info
;
596 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
599 if (!emit
->key
.binning_pass
) {
600 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
601 if (stride_in_vpc
> 0)
602 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
603 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
606 if (info
->indexed
&& info
->primitive_restart
) {
607 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
610 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
612 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
616 if (dirty
& FD_DIRTY_SCISSOR
) {
617 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
619 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
620 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
621 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
622 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
623 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
625 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
626 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
627 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
628 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
631 if (dirty
& FD_DIRTY_VIEWPORT
) {
633 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
634 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
635 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
636 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
637 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
638 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
639 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
642 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_BLEND_DUAL
)) {
643 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
644 int nr_cbufs
= pfb
->nr_cbufs
;
645 if (fd3_blend_stateobj(ctx
->blend
)->rb_render_control
&
646 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE
)
648 fd3_program_emit(ring
, emit
, nr_cbufs
, pfb
->cbufs
);
651 /* TODO we should not need this or fd_wfi() before emit_constants():
653 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
654 OUT_RING(ring
, HLSQ_FLUSH
);
656 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
657 ir3_emit_consts(vp
, ring
, emit
->info
, dirty
);
658 if (!emit
->key
.binning_pass
)
659 ir3_emit_consts(fp
, ring
, emit
->info
, dirty
);
660 /* mark clean after emitting consts: */
664 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) {
665 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
668 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
669 enum pipe_format format
= pipe_surface_format(ctx
->framebuffer
.cbufs
[i
]);
670 const struct util_format_description
*desc
=
671 util_format_description(format
);
672 bool is_float
= util_format_is_float(format
);
673 bool is_int
= util_format_is_pure_integer(format
);
674 bool has_alpha
= util_format_has_alpha(format
);
675 uint32_t control
= blend
->rb_mrt
[i
].control
;
676 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
679 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
680 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
681 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
684 if (format
== PIPE_FORMAT_NONE
)
685 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
688 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
690 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
691 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
694 if (format
&& util_format_get_component_bits(
695 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
696 const struct pipe_rt_blend_state
*rt
;
697 if (ctx
->blend
->independent_blend_enable
)
698 rt
= &ctx
->blend
->rt
[i
];
700 rt
= &ctx
->blend
->rt
[0];
702 if (!util_format_colormask_full(desc
, rt
->colormask
))
703 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
706 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
707 OUT_RING(ring
, control
);
709 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
710 OUT_RING(ring
, blend_control
|
711 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
715 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
716 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
717 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
718 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
719 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
720 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
721 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
722 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
723 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
724 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
725 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
728 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
))
731 if (dirty
& FD_DIRTY_VERTTEX
) {
733 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
735 dirty
&= ~FD_DIRTY_VERTTEX
;
738 if (dirty
& FD_DIRTY_FRAGTEX
) {
740 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
742 dirty
&= ~FD_DIRTY_FRAGTEX
;
745 ctx
->dirty
&= ~dirty
;
748 /* emit setup at begin of new cmdstream buffer (don't rely on previous
749 * state, there could have been a context switch between ioctls):
752 fd3_emit_restore(struct fd_context
*ctx
)
754 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
755 struct fd_ringbuffer
*ring
= ctx
->ring
;
758 if (ctx
->screen
->gpu_id
== 320) {
759 OUT_PKT3(ring
, CP_REG_RMW
, 3);
760 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
761 OUT_RING(ring
, 0xfffcffff);
762 OUT_RING(ring
, 0x00000000);
766 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
767 OUT_RING(ring
, 0x00007fff);
769 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
770 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
771 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
772 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
774 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
775 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
776 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
777 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
779 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
780 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
782 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
783 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
784 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
785 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
787 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
788 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
789 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
790 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
791 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
793 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
794 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
795 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
797 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
798 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
800 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
801 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
802 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
803 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
805 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
806 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
807 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
808 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
810 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
811 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
812 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
814 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
815 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
817 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
818 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
820 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
821 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
823 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
824 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
826 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
827 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
829 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
830 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
831 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
832 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
833 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
835 fd3_emit_cache_flush(ctx
, ring
);
837 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
838 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
840 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
841 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
842 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
844 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
845 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
847 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
848 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
849 A3XX_RB_WINDOW_OFFSET_Y(0));
851 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
852 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
853 A3XX_RB_BLEND_RED_FLOAT(0.0));
854 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
855 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
856 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
857 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
858 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
859 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
861 for (i
= 0; i
< 6; i
++) {
862 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
863 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
864 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
865 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
866 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
869 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
870 OUT_RING(ring
, 0x00000000);
872 fd_event_write(ctx
, ring
, CACHE_FLUSH
);
874 if (is_a3xx_p0(ctx
->screen
)) {
875 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
876 OUT_RING(ring
, 0x00000000);
877 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
878 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
879 OUT_RING(ring
, 0); /* NumIndices */
882 OUT_PKT3(ring
, CP_NOP
, 4);
883 OUT_RING(ring
, 0x00000000);
884 OUT_RING(ring
, 0x00000000);
885 OUT_RING(ring
, 0x00000000);
886 OUT_RING(ring
, 0x00000000);
890 ctx
->needs_rb_fbd
= true;
894 fd3_emit_init(struct pipe_context
*pctx
)
896 struct fd_context
*ctx
= fd_context(pctx
);
897 ctx
->emit_const
= fd3_emit_const
;
898 ctx
->emit_const_bo
= fd3_emit_const_bo
;