1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd3_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
88 for (i
= 0; i
< sz
; i
++) {
89 OUT_RING(ring
, dwords
[i
]);
94 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
95 uint32_t regid
, uint32_t num
, struct fd_bo
**bos
, uint32_t *offsets
)
99 debug_assert((regid
% 4) == 0);
100 debug_assert((num
% 4) == 0);
102 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
103 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num
/2));
107 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 for (i
= 0; i
< num
; i
++) {
113 OUT_RELOCW(ring
, bos
[i
], offsets
[i
], 0, 0);
115 OUT_RELOC(ring
, bos
[i
], offsets
[i
], 0, 0);
118 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
128 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
129 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
131 static const unsigned tex_off
[] = {
132 [SB_VERT_TEX
] = VERT_TEX_OFF
,
133 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
135 static const enum adreno_state_block mipaddr
[] = {
136 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
137 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
139 static const uint32_t bcolor_reg
[] = {
140 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
141 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
143 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
147 u_upload_alloc(fd3_ctx
->border_color_uploader
,
148 0, 2 * PIPE_MAX_SAMPLERS
* BORDERCOLOR_SIZE
, &off
,
149 &fd3_ctx
->border_color_buf
,
152 if (tex
->num_samplers
> 0) {
153 /* output sampler state: */
154 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
155 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
156 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
157 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
158 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
159 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
160 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
161 for (i
= 0; i
< tex
->num_samplers
; i
++) {
162 static const struct fd3_sampler_stateobj dummy_sampler
= {};
163 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
164 fd3_sampler_stateobj(tex
->samplers
[i
]) :
166 uint16_t *bcolor
= (uint16_t *)((uint8_t *)ptr
+
167 (BORDERCOLOR_SIZE
* tex_off
[sb
]) +
168 (BORDERCOLOR_SIZE
* i
));
169 uint32_t *bcolor32
= (uint32_t *)&bcolor
[16];
174 * The border colors need to be swizzled in a particular
175 * format-dependent order. Even though samplers don't know about
176 * formats, we can assume that with a GL state tracker, there's a
177 * 1:1 correspondence between sampler and texture. Take advantage
180 if (i
< tex
->num_textures
&& tex
->textures
[i
]) {
181 const struct util_format_description
*desc
=
182 util_format_description(tex
->textures
[i
]->format
);
183 for (j
= 0; j
< 4; j
++) {
184 if (desc
->swizzle
[j
] >= 4)
187 const struct util_format_channel_description
*chan
=
188 &desc
->channel
[desc
->swizzle
[j
]];
189 int size
= chan
->size
;
191 /* The Z16 texture format we use seems to look in the
192 * 32-bit border color slots
194 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
197 /* Formats like R11G11B10 or RGB9_E5 don't specify
198 * per-channel sizes properly.
200 if (desc
->layout
== UTIL_FORMAT_LAYOUT_OTHER
)
203 if (chan
->pure_integer
&& size
> 16)
204 bcolor32
[desc
->swizzle
[j
] + 4] =
205 sampler
->base
.border_color
.i
[j
];
207 bcolor32
[desc
->swizzle
[j
]] =
208 fui(sampler
->base
.border_color
.f
[j
]);
209 else if (chan
->pure_integer
)
210 bcolor
[desc
->swizzle
[j
] + 8] =
211 sampler
->base
.border_color
.i
[j
];
213 bcolor
[desc
->swizzle
[j
]] =
214 util_float_to_half(sampler
->base
.border_color
.f
[j
]);
218 OUT_RING(ring
, sampler
->texsamp0
);
219 OUT_RING(ring
, sampler
->texsamp1
);
223 if (tex
->num_textures
> 0) {
224 /* emit texture state: */
225 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
226 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
227 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
228 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
229 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
230 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
231 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
232 for (i
= 0; i
< tex
->num_textures
; i
++) {
233 static const struct fd3_pipe_sampler_view dummy_view
= {};
234 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
235 fd3_pipe_sampler_view(tex
->textures
[i
]) :
237 OUT_RING(ring
, view
->texconst0
);
238 OUT_RING(ring
, view
->texconst1
);
239 OUT_RING(ring
, view
->texconst2
|
240 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
241 OUT_RING(ring
, view
->texconst3
);
245 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
246 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
247 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
248 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
249 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
250 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
251 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
252 for (i
= 0; i
< tex
->num_textures
; i
++) {
253 static const struct fd3_pipe_sampler_view dummy_view
= {
254 .base
.u
.tex
.first_level
= 1,
256 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
257 fd3_pipe_sampler_view(tex
->textures
[i
]) :
259 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
260 unsigned start
= view
->base
.u
.tex
.first_level
;
261 unsigned end
= view
->base
.u
.tex
.last_level
;
263 for (j
= 0; j
< (end
- start
+ 1); j
++) {
264 struct fd_resource_slice
*slice
=
265 fd_resource_slice(rsc
, j
+ start
);
266 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
269 /* pad the remaining entries w/ null: */
270 for (; j
< BASETABLE_SZ
; j
++) {
271 OUT_RING(ring
, 0x00000000);
276 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
277 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
279 u_upload_unmap(fd3_ctx
->border_color_uploader
);
282 /* emit texture state for mem->gmem restore operation.. eventually it would
283 * be good to get rid of this and use normal CSO/etc state for more of these
284 * special cases, but for now the compiler is not sufficient..
286 * Also, for using normal state, not quite sure how to handle the special
287 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
290 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
291 struct pipe_surface
**psurf
,
296 /* output sampler state: */
297 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
298 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
299 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
300 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
301 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
302 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
303 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
304 for (i
= 0; i
< bufs
; i
++) {
305 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
306 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
307 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
308 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
309 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
310 OUT_RING(ring
, 0x00000000);
313 /* emit texture state: */
314 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
315 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
316 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
317 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
318 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
319 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
320 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
321 for (i
= 0; i
< bufs
; i
++) {
323 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
324 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
325 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
326 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
327 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
328 OUT_RING(ring
, 0x00000000);
329 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
330 OUT_RING(ring
, 0x00000000);
334 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
335 enum pipe_format format
= fd3_gmem_restore_format(psurf
[i
]->format
);
336 /* The restore blit_zs shader expects stencil in sampler 0, and depth
339 if (rsc
->stencil
&& i
== 0) {
341 format
= fd3_gmem_restore_format(rsc
->base
.b
.format
);
344 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
345 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
347 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
349 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
350 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
351 fd3_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
352 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
353 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
354 A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
355 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
356 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
357 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
358 OUT_RING(ring
, 0x00000000);
362 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
363 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
364 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
365 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
366 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
367 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
368 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
369 for (i
= 0; i
< bufs
; i
++) {
371 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
372 /* Matches above logic for blit_zs shader */
373 if (rsc
->stencil
&& i
== 0)
375 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
376 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
377 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
379 OUT_RING(ring
, 0x00000000);
382 /* pad the remaining entries w/ null: */
383 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
384 OUT_RING(ring
, 0x00000000);
390 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
392 int32_t i
, j
, last
= -1;
393 uint32_t total_in
= 0;
394 const struct fd_vertex_state
*vtx
= emit
->vtx
;
395 struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
396 unsigned vertex_regid
= regid(63, 0);
397 unsigned instance_regid
= regid(63, 0);
398 unsigned vtxcnt_regid
= regid(63, 0);
400 for (i
= 0; i
< vp
->inputs_count
; i
++) {
401 uint8_t semantic
= sem2name(vp
->inputs
[i
].semantic
);
402 if (semantic
== TGSI_SEMANTIC_VERTEXID_NOBASE
)
403 vertex_regid
= vp
->inputs
[i
].regid
;
404 else if (semantic
== TGSI_SEMANTIC_INSTANCEID
)
405 instance_regid
= vp
->inputs
[i
].regid
;
406 else if (semantic
== IR3_SEMANTIC_VTXCNT
)
407 vtxcnt_regid
= vp
->inputs
[i
].regid
;
408 else if (i
< vtx
->vtx
->num_elements
&& vp
->inputs
[i
].compmask
)
412 /* hw doesn't like to be configured for zero vbo's, it seems: */
413 if ((vtx
->vtx
->num_elements
== 0) &&
414 (vertex_regid
== regid(63, 0)) &&
415 (instance_regid
== regid(63, 0)) &&
416 (vtxcnt_regid
== regid(63, 0)))
419 for (i
= 0, j
= 0; i
<= last
; i
++) {
420 assert(sem2name(vp
->inputs
[i
].semantic
) == 0);
421 if (vp
->inputs
[i
].compmask
) {
422 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
423 const struct pipe_vertex_buffer
*vb
=
424 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
425 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
426 enum pipe_format pfmt
= elem
->src_format
;
427 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
428 bool switchnext
= (i
!= last
) ||
429 (vertex_regid
!= regid(63, 0)) ||
430 (instance_regid
!= regid(63, 0)) ||
431 (vtxcnt_regid
!= regid(63, 0));
432 bool isint
= util_format_is_pure_integer(pfmt
);
433 uint32_t fs
= util_format_get_blocksize(pfmt
);
435 debug_assert(fmt
!= ~0);
437 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
438 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
439 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
440 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
441 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
442 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
443 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
444 OUT_RELOC(ring
, rsc
->bo
, vb
->buffer_offset
+ elem
->src_offset
, 0, 0);
446 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
447 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
448 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
449 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
450 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
451 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
452 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
453 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
454 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
455 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
457 total_in
+= vp
->inputs
[i
].ncomp
;
462 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
463 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
464 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
465 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
466 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
467 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
468 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
469 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
471 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
472 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
473 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
477 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
478 struct fd3_emit
*emit
)
480 struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
481 struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
482 uint32_t dirty
= emit
->dirty
;
484 emit_marker(ring
, 5);
486 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
487 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
488 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
489 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
490 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
493 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) && !emit
->key
.binning_pass
) {
494 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
;
496 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
497 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
498 A3XX_RB_RENDER_CONTROL_YCOORD
|
499 A3XX_RB_RENDER_CONTROL_ZCOORD
|
500 A3XX_RB_RENDER_CONTROL_WCOORD
);
502 /* I suppose if we needed to (which I don't *think* we need
503 * to), we could emit this for binning pass too. But we
504 * would need to keep a different patch-list for binning
508 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
509 OUT_RINGP(ring
, val
, &fd3_context(ctx
)->rbrc_patches
);
512 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
513 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
514 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
516 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
517 OUT_RING(ring
, zsa
->rb_alpha_ref
);
519 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
520 OUT_RING(ring
, zsa
->rb_stencil_control
);
522 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
523 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
524 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
525 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
526 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
529 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
530 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
531 if (fp
->writes_pos
) {
532 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
533 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
536 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
538 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
542 if (dirty
& FD_DIRTY_RASTERIZER
) {
543 struct fd3_rasterizer_stateobj
*rasterizer
=
544 fd3_rasterizer_stateobj(ctx
->rasterizer
);
546 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
547 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
549 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
550 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
551 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
553 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
554 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
555 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
558 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
559 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
561 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
562 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
563 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
564 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
568 /* NOTE: since primitive_restart is not actually part of any
569 * state object, we need to make sure that we always emit
570 * PRIM_VTX_CNTL.. either that or be more clever and detect
574 const struct pipe_draw_info
*info
= emit
->info
;
575 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
578 if (!emit
->key
.binning_pass
) {
579 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
580 if (stride_in_vpc
> 0)
581 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
582 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
585 if (info
->indexed
&& info
->primitive_restart
) {
586 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
589 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
591 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
595 if (dirty
& FD_DIRTY_SCISSOR
) {
596 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
598 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
599 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
600 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
601 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
602 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
604 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
605 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
606 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
607 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
610 if (dirty
& FD_DIRTY_VIEWPORT
) {
612 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
613 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
614 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
615 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
616 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
617 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
618 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
621 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
622 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
623 fd3_program_emit(ring
, emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
626 /* TODO we should not need this or fd_wfi() before emit_constants():
628 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
629 OUT_RING(ring
, HLSQ_FLUSH
);
631 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
632 ir3_emit_consts(vp
, ring
, emit
->info
, dirty
);
633 if (!emit
->key
.binning_pass
)
634 ir3_emit_consts(fp
, ring
, emit
->info
, dirty
);
635 /* mark clean after emitting consts: */
639 if ((dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) && ctx
->blend
) {
640 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
643 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
644 enum pipe_format format
= pipe_surface_format(ctx
->framebuffer
.cbufs
[i
]);
645 const struct util_format_description
*desc
=
646 util_format_description(format
);
647 bool is_float
= util_format_is_float(format
);
648 bool is_int
= util_format_is_pure_integer(format
);
649 bool has_alpha
= util_format_has_alpha(format
);
650 uint32_t control
= blend
->rb_mrt
[i
].control
;
651 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
654 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
655 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
656 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
659 if (format
== PIPE_FORMAT_NONE
)
660 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
663 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
665 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
666 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
669 if (format
&& util_format_get_component_bits(
670 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
671 const struct pipe_rt_blend_state
*rt
;
672 if (ctx
->blend
->independent_blend_enable
)
673 rt
= &ctx
->blend
->rt
[i
];
675 rt
= &ctx
->blend
->rt
[0];
677 if (!util_format_colormask_full(desc
, rt
->colormask
))
678 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
681 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
682 OUT_RING(ring
, control
);
684 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
685 OUT_RING(ring
, blend_control
|
686 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
690 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
691 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
692 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
693 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
694 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
695 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
696 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
697 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
698 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
699 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
700 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
703 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
))
706 if (dirty
& FD_DIRTY_VERTTEX
) {
708 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
710 dirty
&= ~FD_DIRTY_VERTTEX
;
713 if (dirty
& FD_DIRTY_FRAGTEX
) {
715 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
717 dirty
&= ~FD_DIRTY_FRAGTEX
;
720 ctx
->dirty
&= ~dirty
;
723 /* emit setup at begin of new cmdstream buffer (don't rely on previous
724 * state, there could have been a context switch between ioctls):
727 fd3_emit_restore(struct fd_context
*ctx
)
729 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
730 struct fd_ringbuffer
*ring
= ctx
->ring
;
733 if (ctx
->screen
->gpu_id
== 320) {
734 OUT_PKT3(ring
, CP_REG_RMW
, 3);
735 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
736 OUT_RING(ring
, 0xfffcffff);
737 OUT_RING(ring
, 0x00000000);
741 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
742 OUT_RING(ring
, 0x00007fff);
744 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
745 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
746 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
747 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
749 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
750 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
751 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
752 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
754 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
755 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
757 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
758 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
759 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
760 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
762 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
763 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
764 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
765 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
766 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
768 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
769 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
770 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
772 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
773 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
775 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
776 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
777 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
778 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
780 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
781 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
782 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
783 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
785 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
786 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
787 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
789 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
790 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
792 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
793 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
795 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
796 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
798 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
799 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
801 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
802 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
804 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
805 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
806 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
807 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
808 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
810 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
811 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
812 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
813 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
814 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
816 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
817 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
819 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
820 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
821 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
823 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
824 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
826 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
827 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
828 A3XX_RB_WINDOW_OFFSET_Y(0));
830 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
831 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
832 A3XX_RB_BLEND_RED_FLOAT(0.0));
833 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
834 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
835 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
836 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
837 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
838 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
840 for (i
= 0; i
< 6; i
++) {
841 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
842 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
843 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
844 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
845 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
848 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
849 OUT_RING(ring
, 0x00000000);
851 fd_event_write(ctx
, ring
, CACHE_FLUSH
);
853 if (is_a3xx_p0(ctx
->screen
)) {
854 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
855 OUT_RING(ring
, 0x00000000);
856 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
857 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
858 OUT_RING(ring
, 0); /* NumIndices */
861 OUT_PKT3(ring
, CP_NOP
, 4);
862 OUT_RING(ring
, 0x00000000);
863 OUT_RING(ring
, 0x00000000);
864 OUT_RING(ring
, 0x00000000);
865 OUT_RING(ring
, 0x00000000);
869 ctx
->needs_rb_fbd
= true;
873 fd3_emit_init(struct pipe_context
*pctx
)
875 struct fd_context
*ctx
= fd_context(pctx
);
876 ctx
->emit_const
= fd3_emit_const
;
877 ctx
->emit_const_bo
= fd3_emit_const_bo
;