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Merge remote-tracking branch 'jekstrand/wip/i965-uniforms' into vulkan
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = SS_INDIRECT;
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/2));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 #define VERT_TEX_OFF 0
124 #define FRAG_TEX_OFF 16
125 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
126
127 static void
128 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
129 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
130 {
131 static const unsigned tex_off[] = {
132 [SB_VERT_TEX] = VERT_TEX_OFF,
133 [SB_FRAG_TEX] = FRAG_TEX_OFF,
134 };
135 static const enum adreno_state_block mipaddr[] = {
136 [SB_VERT_TEX] = SB_VERT_MIPADDR,
137 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
138 };
139 static const uint32_t bcolor_reg[] = {
140 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
141 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
142 };
143 struct fd3_context *fd3_ctx = fd3_context(ctx);
144 unsigned i, j, off;
145 void *ptr;
146
147 u_upload_alloc(fd3_ctx->border_color_uploader,
148 0, BORDER_COLOR_UPLOAD_SIZE,
149 BORDER_COLOR_UPLOAD_SIZE, &off,
150 &fd3_ctx->border_color_buf,
151 &ptr);
152
153 fd_setup_border_colors(tex, ptr, tex_off[sb]);
154
155 if (tex->num_samplers > 0) {
156 /* output sampler state: */
157 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
158 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
159 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
160 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
161 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
162 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
163 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
164 for (i = 0; i < tex->num_samplers; i++) {
165 static const struct fd3_sampler_stateobj dummy_sampler = {};
166 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
167 fd3_sampler_stateobj(tex->samplers[i]) :
168 &dummy_sampler;
169
170 OUT_RING(ring, sampler->texsamp0);
171 OUT_RING(ring, sampler->texsamp1);
172 }
173 }
174
175 if (tex->num_textures > 0) {
176 /* emit texture state: */
177 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
178 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
179 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
180 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
181 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
182 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
183 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
184 for (i = 0; i < tex->num_textures; i++) {
185 static const struct fd3_pipe_sampler_view dummy_view = {};
186 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
187 fd3_pipe_sampler_view(tex->textures[i]) :
188 &dummy_view;
189 OUT_RING(ring, view->texconst0);
190 OUT_RING(ring, view->texconst1);
191 OUT_RING(ring, view->texconst2 |
192 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
193 OUT_RING(ring, view->texconst3);
194 }
195
196 /* emit mipaddrs: */
197 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
198 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
199 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
200 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
201 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
202 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
203 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
204 for (i = 0; i < tex->num_textures; i++) {
205 static const struct fd3_pipe_sampler_view dummy_view = {
206 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
207 .base.u.tex.first_level = 1,
208 };
209 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
210 fd3_pipe_sampler_view(tex->textures[i]) :
211 &dummy_view;
212 struct fd_resource *rsc = fd_resource(view->base.texture);
213 if (rsc && rsc->base.b.target == PIPE_BUFFER) {
214 OUT_RELOC(ring, rsc->bo, view->base.u.buf.first_element *
215 util_format_get_blocksize(view->base.format), 0, 0);
216 j = 1;
217 } else {
218 unsigned start = fd_sampler_first_level(&view->base);
219 unsigned end = fd_sampler_last_level(&view->base);;
220
221 for (j = 0; j < (end - start + 1); j++) {
222 struct fd_resource_slice *slice =
223 fd_resource_slice(rsc, j + start);
224 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
225 }
226 }
227
228 /* pad the remaining entries w/ null: */
229 for (; j < BASETABLE_SZ; j++) {
230 OUT_RING(ring, 0x00000000);
231 }
232 }
233 }
234
235 OUT_PKT0(ring, bcolor_reg[sb], 1);
236 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
237
238 u_upload_unmap(fd3_ctx->border_color_uploader);
239 }
240
241 /* emit texture state for mem->gmem restore operation.. eventually it would
242 * be good to get rid of this and use normal CSO/etc state for more of these
243 * special cases, but for now the compiler is not sufficient..
244 *
245 * Also, for using normal state, not quite sure how to handle the special
246 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
247 */
248 void
249 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
250 struct pipe_surface **psurf,
251 int bufs)
252 {
253 int i, j;
254
255 /* output sampler state: */
256 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
257 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
258 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
259 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
260 CP_LOAD_STATE_0_NUM_UNIT(bufs));
261 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
262 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
263 for (i = 0; i < bufs; i++) {
264 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
265 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
266 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
267 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
268 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
269 OUT_RING(ring, 0x00000000);
270 }
271
272 /* emit texture state: */
273 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
274 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
275 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
276 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
277 CP_LOAD_STATE_0_NUM_UNIT(bufs));
278 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
279 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
280 for (i = 0; i < bufs; i++) {
281 if (!psurf[i]) {
282 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
283 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
284 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
285 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
286 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
287 OUT_RING(ring, 0x00000000);
288 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
289 OUT_RING(ring, 0x00000000);
290 continue;
291 }
292
293 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
294 enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
295 /* The restore blit_zs shader expects stencil in sampler 0, and depth
296 * in sampler 1
297 */
298 if (rsc->stencil && i == 0) {
299 rsc = rsc->stencil;
300 format = fd3_gmem_restore_format(rsc->base.b.format);
301 }
302
303 /* note: PIPE_BUFFER disallowed for surfaces */
304 unsigned lvl = psurf[i]->u.tex.level;
305 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
306
307 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
308
309 OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
310 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
311 fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
312 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
313 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
314 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
315 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
316 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
317 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
318 OUT_RING(ring, 0x00000000);
319 }
320
321 /* emit mipaddrs: */
322 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
323 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
324 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
325 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
326 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
327 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
328 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
329 for (i = 0; i < bufs; i++) {
330 if (psurf[i]) {
331 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
332 /* Matches above logic for blit_zs shader */
333 if (rsc->stencil && i == 0)
334 rsc = rsc->stencil;
335 unsigned lvl = psurf[i]->u.tex.level;
336 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
337 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
338 } else {
339 OUT_RING(ring, 0x00000000);
340 }
341
342 /* pad the remaining entries w/ null: */
343 for (j = 1; j < BASETABLE_SZ; j++) {
344 OUT_RING(ring, 0x00000000);
345 }
346 }
347 }
348
349 void
350 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
351 {
352 int32_t i, j, last = -1;
353 uint32_t total_in = 0;
354 const struct fd_vertex_state *vtx = emit->vtx;
355 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
356 unsigned vertex_regid = regid(63, 0);
357 unsigned instance_regid = regid(63, 0);
358 unsigned vtxcnt_regid = regid(63, 0);
359
360 /* Note that sysvals come *after* normal inputs: */
361 for (i = 0; i < vp->inputs_count; i++) {
362 if (!vp->inputs[i].compmask)
363 continue;
364 if (vp->inputs[i].sysval) {
365 switch(vp->inputs[i].slot) {
366 case SYSTEM_VALUE_BASE_VERTEX:
367 /* handled elsewhere */
368 break;
369 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
370 vertex_regid = vp->inputs[i].regid;
371 break;
372 case SYSTEM_VALUE_INSTANCE_ID:
373 instance_regid = vp->inputs[i].regid;
374 break;
375 case SYSTEM_VALUE_VERTEX_CNT:
376 vtxcnt_regid = vp->inputs[i].regid;
377 break;
378 default:
379 unreachable("invalid system value");
380 break;
381 }
382 } else if (i < vtx->vtx->num_elements) {
383 last = i;
384 }
385 }
386
387 for (i = 0, j = 0; i <= last; i++) {
388 assert(!vp->inputs[i].sysval);
389 if (vp->inputs[i].compmask) {
390 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
391 const struct pipe_vertex_buffer *vb =
392 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
393 struct fd_resource *rsc = fd_resource(vb->buffer);
394 enum pipe_format pfmt = elem->src_format;
395 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
396 bool switchnext = (i != last) ||
397 (vertex_regid != regid(63, 0)) ||
398 (instance_regid != regid(63, 0)) ||
399 (vtxcnt_regid != regid(63, 0));
400 bool isint = util_format_is_pure_integer(pfmt);
401 uint32_t fs = util_format_get_blocksize(pfmt);
402
403 debug_assert(fmt != ~0);
404
405 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
406 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
407 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
408 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
409 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
410 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
411 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
412 OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
413
414 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
415 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
416 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
417 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
418 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
419 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
420 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
421 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
422 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
423 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
424
425 total_in += vp->inputs[i].ncomp;
426 j++;
427 }
428 }
429
430 /* hw doesn't like to be configured for zero vbo's, it seems: */
431 if (last < 0) {
432 /* just recycle the shader bo, we just need to point to *something*
433 * valid:
434 */
435 struct fd_bo *dummy_vbo = vp->bo;
436 bool switchnext = (vertex_regid != regid(63, 0)) ||
437 (instance_regid != regid(63, 0)) ||
438 (vtxcnt_regid != regid(63, 0));
439
440 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
441 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
442 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
443 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
444 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
445 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
446 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
447
448 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
449 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
450 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
451 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
452 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
453 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
454 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
455 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
456 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
457
458 total_in = 1;
459 j = 1;
460 }
461
462 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
463 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
464 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
465 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
466 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
467 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
468 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
469 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
470
471 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
472 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
473 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
474 }
475
476 void
477 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
478 struct fd3_emit *emit)
479 {
480 struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
481 struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
482 uint32_t dirty = emit->dirty;
483
484 emit_marker(ring, 5);
485
486 if (dirty & FD_DIRTY_SAMPLE_MASK) {
487 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
488 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
489 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
490 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
491 }
492
493 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
494 !emit->key.binning_pass) {
495 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
496 fd3_blend_stateobj(ctx->blend)->rb_render_control;
497
498 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
499 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
500 A3XX_RB_RENDER_CONTROL_YCOORD |
501 A3XX_RB_RENDER_CONTROL_ZCOORD |
502 A3XX_RB_RENDER_CONTROL_WCOORD);
503
504 /* I suppose if we needed to (which I don't *think* we need
505 * to), we could emit this for binning pass too. But we
506 * would need to keep a different patch-list for binning
507 * vs render pass.
508 */
509
510 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
511 OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
512 }
513
514 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
515 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
516 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
517
518 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
519 OUT_RING(ring, zsa->rb_alpha_ref);
520
521 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
522 OUT_RING(ring, zsa->rb_stencil_control);
523
524 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
525 OUT_RING(ring, zsa->rb_stencilrefmask |
526 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
527 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
528 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
529 }
530
531 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
532 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
533 if (fp->writes_pos) {
534 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
535 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
536 }
537 if (fp->has_kill) {
538 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
539 }
540 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
541 OUT_RING(ring, val);
542 }
543
544 if (dirty & FD_DIRTY_RASTERIZER) {
545 struct fd3_rasterizer_stateobj *rasterizer =
546 fd3_rasterizer_stateobj(ctx->rasterizer);
547
548 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
549 OUT_RING(ring, rasterizer->gras_su_mode_control);
550
551 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
552 OUT_RING(ring, rasterizer->gras_su_point_minmax);
553 OUT_RING(ring, rasterizer->gras_su_point_size);
554
555 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
556 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
557 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
558 }
559
560 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
561 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
562 ->gras_cl_clip_cntl;
563 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
564 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
565 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
566 /* TODO only use if prog doesn't use clipvertex/clipdist */
567 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
568 MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
569 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
570 OUT_RING(ring, val);
571 }
572
573 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
574 uint32_t planes = ctx->rasterizer->clip_plane_enable;
575 int count = 0;
576
577 while (planes && count < 6) {
578 int i = ffs(planes) - 1;
579
580 planes &= ~(1U << i);
581 fd_wfi(ctx, ring);
582 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
583 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
584 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
585 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
586 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
587 }
588 }
589
590 /* NOTE: since primitive_restart is not actually part of any
591 * state object, we need to make sure that we always emit
592 * PRIM_VTX_CNTL.. either that or be more clever and detect
593 * when it changes.
594 */
595 if (emit->info) {
596 const struct pipe_draw_info *info = emit->info;
597 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
598 ->pc_prim_vtx_cntl;
599
600 if (!emit->key.binning_pass) {
601 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
602 if (stride_in_vpc > 0)
603 stride_in_vpc = MAX2(stride_in_vpc, 2);
604 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
605 }
606
607 if (info->indexed && info->primitive_restart) {
608 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
609 }
610
611 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
612
613 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
614 OUT_RING(ring, val);
615 }
616
617 if (dirty & FD_DIRTY_SCISSOR) {
618 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
619
620 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
621 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
622 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
623 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
624 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
625
626 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
627 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
628 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
629 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
630 }
631
632 if (dirty & FD_DIRTY_VIEWPORT) {
633 fd_wfi(ctx, ring);
634 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
635 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
636 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
637 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
638 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
639 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
640 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
641 }
642
643 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
644 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
645 int nr_cbufs = pfb->nr_cbufs;
646 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
647 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
648 nr_cbufs++;
649 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
650 }
651
652 /* TODO we should not need this or fd_wfi() before emit_constants():
653 */
654 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
655 OUT_RING(ring, HLSQ_FLUSH);
656
657 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
658 ir3_emit_consts(vp, ring, emit->info, dirty);
659 if (!emit->key.binning_pass)
660 ir3_emit_consts(fp, ring, emit->info, dirty);
661 /* mark clean after emitting consts: */
662 ctx->prog.dirty = 0;
663 }
664
665 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
666 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
667 uint32_t i;
668
669 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
670 enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
671 const struct util_format_description *desc =
672 util_format_description(format);
673 bool is_float = util_format_is_float(format);
674 bool is_int = util_format_is_pure_integer(format);
675 bool has_alpha = util_format_has_alpha(format);
676 uint32_t control = blend->rb_mrt[i].control;
677 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
678
679 if (is_int) {
680 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
681 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
682 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
683 }
684
685 if (format == PIPE_FORMAT_NONE)
686 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
687
688 if (has_alpha) {
689 blend_control |= blend->rb_mrt[i].blend_control_rgb;
690 } else {
691 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
692 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
693 }
694
695 if (format && util_format_get_component_bits(
696 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
697 const struct pipe_rt_blend_state *rt;
698 if (ctx->blend->independent_blend_enable)
699 rt = &ctx->blend->rt[i];
700 else
701 rt = &ctx->blend->rt[0];
702
703 if (!util_format_colormask_full(desc, rt->colormask))
704 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
705 }
706
707 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
708 OUT_RING(ring, control);
709
710 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
711 OUT_RING(ring, blend_control |
712 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
713 }
714 }
715
716 if (dirty & FD_DIRTY_BLEND_COLOR) {
717 struct pipe_blend_color *bcolor = &ctx->blend_color;
718 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
719 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
720 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
721 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
722 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
723 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
724 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
725 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
726 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
727 }
728
729 if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
730 fd_wfi(ctx, ring);
731
732 if (dirty & FD_DIRTY_VERTTEX) {
733 if (vp->has_samp)
734 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
735 else
736 dirty &= ~FD_DIRTY_VERTTEX;
737 }
738
739 if (dirty & FD_DIRTY_FRAGTEX) {
740 if (fp->has_samp)
741 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
742 else
743 dirty &= ~FD_DIRTY_FRAGTEX;
744 }
745
746 ctx->dirty &= ~dirty;
747 }
748
749 /* emit setup at begin of new cmdstream buffer (don't rely on previous
750 * state, there could have been a context switch between ioctls):
751 */
752 void
753 fd3_emit_restore(struct fd_context *ctx)
754 {
755 struct fd3_context *fd3_ctx = fd3_context(ctx);
756 struct fd_ringbuffer *ring = ctx->ring;
757 int i;
758
759 if (ctx->screen->gpu_id == 320) {
760 OUT_PKT3(ring, CP_REG_RMW, 3);
761 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
762 OUT_RING(ring, 0xfffcffff);
763 OUT_RING(ring, 0x00000000);
764 }
765
766 fd_wfi(ctx, ring);
767 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
768 OUT_RING(ring, 0x00007fff);
769
770 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
771 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
772 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
773 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
774
775 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
776 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
777 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
778 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
779
780 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
781 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
782
783 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
784 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
785 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
786 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
787
788 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
789 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
790 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
791 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
792 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
793
794 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
795 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
796 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
797
798 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
799 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
800
801 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
802 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
803 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
804 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
805
806 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
807 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
808 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
809 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
810
811 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
812 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
813 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
814
815 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
816 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
817
818 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
819 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
820
821 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
822 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
823
824 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
825 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
826
827 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
828 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
829
830 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
831 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
832 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
833 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
834 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
835
836 fd3_emit_cache_flush(ctx, ring);
837
838 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
839 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
840
841 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
842 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
843 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
844
845 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
846 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
847
848 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
849 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
850 A3XX_RB_WINDOW_OFFSET_Y(0));
851
852 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
853 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
854 A3XX_RB_BLEND_RED_FLOAT(0.0));
855 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
856 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
857 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
858 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
859 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
860 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
861
862 for (i = 0; i < 6; i++) {
863 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
864 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
865 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
866 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
867 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
868 }
869
870 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
871 OUT_RING(ring, 0x00000000);
872
873 fd_event_write(ctx, ring, CACHE_FLUSH);
874
875 if (is_a3xx_p0(ctx->screen)) {
876 OUT_PKT3(ring, CP_DRAW_INDX, 3);
877 OUT_RING(ring, 0x00000000);
878 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
879 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
880 OUT_RING(ring, 0); /* NumIndices */
881 }
882
883 OUT_PKT3(ring, CP_NOP, 4);
884 OUT_RING(ring, 0x00000000);
885 OUT_RING(ring, 0x00000000);
886 OUT_RING(ring, 0x00000000);
887 OUT_RING(ring, 0x00000000);
888
889 fd_wfi(ctx, ring);
890
891 ctx->needs_rb_fbd = true;
892 }
893
894 void
895 fd3_emit_init(struct pipe_context *pctx)
896 {
897 struct fd_context *ctx = fd_context(pctx);
898 ctx->emit_const = fd3_emit_const;
899 ctx->emit_const_bo = fd3_emit_const_bo;
900 }