src/gallium/drivers/freedreno/a3xx/fd3_emit.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_helpers.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_resource.h"
  36
  37 #include "fd3_emit.h"
  38 #include "fd3_blend.h"
  39 #include "fd3_context.h"
  40 #include "fd3_program.h"
  41 #include "fd3_rasterizer.h"
  42 #include "fd3_texture.h"
  43 #include "fd3_util.h"
  44 #include "fd3_zsa.h"
  45
  46 /* regid:          base const register
  47  * prsc or dwords: buffer containing constant values
  48  * sizedwords:     size of const value buffer
  49  */
  50 void
  51 fd3_emit_constant(struct fd_ringbuffer *ring,
  52                 enum adreno_state_block sb,
  53                 uint32_t regid, uint32_t offset, uint32_t sizedwords,
  54                 const uint32_t *dwords, struct pipe_resource *prsc)
  55 {
  56         uint32_t i, sz;
  57         enum adreno_state_src src;
  58
  59         if (prsc) {
  60                 sz = 0;
  61                 src = SS_INDIRECT;
  62         } else {
  63                 sz = sizedwords;
  64                 src = SS_DIRECT;
  65         }
  66
  67         /* we have this sometimes, not others.. perhaps we could be clever
  68          * and figure out actually when we need to invalidate cache:
  69          */
  70         OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
  71         OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
  72         OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
  73                         A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
  74                         A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
  75
  76         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
  77         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
  78                         CP_LOAD_STATE_0_STATE_SRC(src) |
  79                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
  80                         CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
  81         if (prsc) {
  82                 struct fd_bo *bo = fd_resource(prsc)->bo;
  83                 OUT_RELOC(ring, bo, offset,
  84                                 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
  85         } else {
  86                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
  87                                 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
  88                 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
  89         }
  90         for (i = 0; i < sz; i++) {
  91                 OUT_RING(ring, dwords[i]);
  92         }
  93 }
  94
  95 static void
  96 emit_constants(struct fd_ringbuffer *ring,
  97                 enum adreno_state_block sb,
  98                 struct fd_constbuf_stateobj *constbuf,
  99                 struct fd3_shader_stateobj *shader)
 100 {
 101         uint32_t enabled_mask = constbuf->enabled_mask;
 102         uint32_t base = 0;
 103         unsigned i;
 104
 105         // XXX TODO only emit dirty consts.. but we need to keep track if
 106         // they are clobbered by a clear, gmem2mem, or mem2gmem..
 107         constbuf->dirty_mask = enabled_mask;
 108
 109         /* emit user constants: */
 110         while (enabled_mask) {
 111                 unsigned index = ffs(enabled_mask) - 1;
 112                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
 113                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 114
 115                 // I expect that size should be a multiple of vec4's:
 116                 assert(size == align(size, 4));
 117
 118                 /* gallium could leave const buffers bound above what the
 119                  * current shader uses.. don't let that confuse us.
 120                  */
 121                 if (base >= (4 * shader->first_immediate))
 122                         break;
 123
 124                 if (constbuf->dirty_mask & (1 << index)) {
 125                         fd3_emit_constant(ring, sb, base,
 126                                         cb->buffer_offset, size,
 127                                         cb->user_buffer, cb->buffer);
 128                         constbuf->dirty_mask &= ~(1 << index);
 129                 }
 130
 131                 base += size;
 132                 enabled_mask &= ~(1 << index);
 133         }
 134
 135         /* emit shader immediates: */
 136         if (shader) {
 137                 for (i = 0; i < shader->immediates_count; i++) {
 138                         base = 4 * (shader->first_immediate + i);
 139                         if (base >= (4 * shader->constlen))
 140                                 break;
 141                         fd3_emit_constant(ring, sb, base,
 142                                 0, 4, shader->immediates[i].val, NULL);
 143                 }
 144         }
 145 }
 146
 147 #define VERT_TEX_OFF    0
 148 #define FRAG_TEX_OFF    16
 149 #define BASETABLE_SZ    A3XX_MAX_MIP_LEVELS
 150
 151 static void
 152 emit_textures(struct fd_ringbuffer *ring,
 153                 enum adreno_state_block sb,
 154                 struct fd_texture_stateobj *tex)
 155 {
 156         static const unsigned tex_off[] = {
 157                         [SB_VERT_TEX] = VERT_TEX_OFF,
 158                         [SB_FRAG_TEX] = FRAG_TEX_OFF,
 159         };
 160         static const enum adreno_state_block mipaddr[] = {
 161                         [SB_VERT_TEX] = SB_VERT_MIPADDR,
 162                         [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
 163         };
 164         unsigned i, j;
 165
 166         if (tex->num_samplers > 0) {
 167                 /* output sampler state: */
 168                 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
 169                 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
 170                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 171                                 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 172                                 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
 173                 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
 174                                 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 175                 for (i = 0; i < tex->num_samplers; i++) {
 176                         struct fd3_sampler_stateobj *sampler =
 177                                         fd3_sampler_stateobj(tex->samplers[i]);
 178                         OUT_RING(ring, sampler->texsamp0);
 179                         OUT_RING(ring, sampler->texsamp1);
 180                 }
 181         }
 182
 183         if (tex->num_textures > 0) {
 184                 /* emit texture state: */
 185                 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
 186                 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
 187                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 188                                 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 189                                 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
 190                 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 191                                 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 192                 for (i = 0; i < tex->num_textures; i++) {
 193                         struct fd3_pipe_sampler_view *view =
 194                                         fd3_pipe_sampler_view(tex->textures[i]);
 195                         OUT_RING(ring, view->texconst0);
 196                         OUT_RING(ring, view->texconst1);
 197                         OUT_RING(ring, view->texconst2 |
 198                                         A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
 199                         OUT_RING(ring, view->texconst3);
 200                 }
 201
 202                 /* emit mipaddrs: */
 203                 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
 204                 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
 205                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 206                                 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
 207                                 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
 208                 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 209                                 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 210                 for (i = 0; i < tex->num_textures; i++) {
 211                         struct fd3_pipe_sampler_view *view =
 212                                         fd3_pipe_sampler_view(tex->textures[i]);
 213                         struct fd_resource *rsc = view->tex_resource;
 214
 215                         for (j = 0; j < view->mipaddrs; j++) {
 216                                 struct fd_resource_slice *slice = fd_resource_slice(rsc, j);
 217                                 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
 218                         }
 219
 220                         /* pad the remaining entries w/ null: */
 221                         for (; j < BASETABLE_SZ; j++) {
 222                                 OUT_RING(ring, 0x00000000);
 223                         }
 224                 }
 225         }
 226 }
 227
 228 static void
 229 emit_cache_flush(struct fd_ringbuffer *ring)
 230 {
 231         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 232         OUT_RING(ring, CACHE_FLUSH);
 233
 234         /* probably only really needed on a320: */
 235         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 236         OUT_RING(ring, 0x00000000);
 237         OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
 238                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 239         OUT_RING(ring, 0);                                      /* NumIndices */
 240
 241         OUT_PKT3(ring, CP_NOP, 4);
 242         OUT_RING(ring, 0x00000000);
 243         OUT_RING(ring, 0x00000000);
 244         OUT_RING(ring, 0x00000000);
 245         OUT_RING(ring, 0x00000000);
 246 }
 247
 248 /* emit texture state for mem->gmem restore operation.. eventually it would
 249  * be good to get rid of this and use normal CSO/etc state for more of these
 250  * special cases, but for now the compiler is not sufficient..
 251  */
 252 void
 253 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
 254 {
 255         struct fd_resource *rsc = fd_resource(psurf->texture);
 256         enum pipe_format format = fd3_gmem_restore_format(psurf->format);
 257
 258         /* output sampler state: */
 259         OUT_PKT3(ring, CP_LOAD_STATE, 4);
 260         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
 261                         CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 262                         CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
 263                         CP_LOAD_STATE_0_NUM_UNIT(1));
 264         OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
 265                         CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 266         OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
 267                         A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
 268                         A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
 269                         A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
 270                         A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
 271         OUT_RING(ring, 0x00000000);
 272
 273         /* emit texture state: */
 274         OUT_PKT3(ring, CP_LOAD_STATE, 6);
 275         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
 276                         CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 277                         CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
 278                         CP_LOAD_STATE_0_NUM_UNIT(1));
 279         OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 280                         CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 281         OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) |
 282                         A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
 283                         fd3_tex_swiz(format,  PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
 284                                         PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
 285         OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
 286                         A3XX_TEX_CONST_1_WIDTH(psurf->width) |
 287                         A3XX_TEX_CONST_1_HEIGHT(psurf->height));
 288         OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->slices[0].pitch * rsc->cpp) |
 289                         A3XX_TEX_CONST_2_INDX(0));
 290         OUT_RING(ring, 0x00000000);
 291
 292         /* emit mipaddrs: */
 293         OUT_PKT3(ring, CP_LOAD_STATE, 3);
 294         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
 295                         CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 296                         CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
 297                         CP_LOAD_STATE_0_NUM_UNIT(1));
 298         OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 299                         CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 300         OUT_RELOC(ring, rsc->bo, 0, 0, 0);
 301 }
 302
 303 void
 304 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 305                 struct fd_program_stateobj *prog,
 306                 struct fd3_vertex_buf *vbufs, uint32_t n)
 307 {
 308         struct fd3_shader_stateobj *vp = prog->vp;
 309         uint32_t i;
 310
 311         n = MIN2(n, vp->inputs_count);
 312
 313         for (i = 0; i < n; i++) {
 314                 struct pipe_resource *prsc = vbufs[i].prsc;
 315                 struct fd_resource *rsc = fd_resource(prsc);
 316                 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(vbufs[i].format);
 317                 bool switchnext = (i != (n - 1));
 318                 uint32_t fs = util_format_get_blocksize(vbufs[i].format);
 319
 320                 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(i), 2);
 321                 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
 322                                 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) |
 323                                 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
 324                                 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) |
 325                                 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
 326                 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0);
 327
 328                 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1);
 329                 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
 330                                 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
 331                                 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
 332                                 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
 333                                 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
 334                                 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
 335                                 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
 336         }
 337 }
 338
 339 void
 340 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 341                 struct fd_program_stateobj *prog, uint32_t dirty, bool binning)
 342 {
 343         emit_marker(ring, 5);
 344
 345         if (dirty & FD_DIRTY_SAMPLE_MASK) {
 346                 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
 347                 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 348                                 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 349                                 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
 350         }
 351
 352         if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
 353                 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
 354                 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
 355
 356                 if (!binning) {
 357                         struct fd3_context *fd3_ctx = fd3_context(ctx);
 358
 359                         /* I suppose if we needed to (which I don't *think* we need
 360                          * to), we could emit this for binning pass too.  But we
 361                          * would need to keep a different patch-list for binning
 362                          * vs render pass.
 363                          */
 364
 365                         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 366                         OUT_RINGP(ring, zsa->rb_render_control,
 367                                         &fd3_ctx->rbrc_patches);
 368                 }
 369
 370                 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
 371                 OUT_RING(ring, zsa->rb_alpha_ref);
 372
 373                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 374                 OUT_RING(ring, zsa->rb_stencil_control);
 375
 376                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 377                 OUT_RING(ring, zsa->rb_stencilrefmask |
 378                                 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
 379                 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
 380                                 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
 381         }
 382
 383         if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
 384                 struct fd3_shader_stateobj *fp = prog->fp;
 385                 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
 386                 if (fp->writes_pos) {
 387                         val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
 388                         val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 389                 }
 390                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 391                 OUT_RING(ring, val);
 392         }
 393
 394         if (dirty & FD_DIRTY_RASTERIZER) {
 395                 struct fd3_rasterizer_stateobj *rasterizer =
 396                                 fd3_rasterizer_stateobj(ctx->rasterizer);
 397
 398                 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 399                 OUT_RING(ring, rasterizer->gras_su_mode_control);
 400
 401                 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
 402                 OUT_RING(ring, rasterizer->gras_su_point_minmax);
 403                 OUT_RING(ring, rasterizer->gras_su_point_size);
 404
 405                 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
 406                 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
 407                 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
 408         }
 409
 410         if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
 411                 struct fd3_shader_stateobj *fp = prog->fp;
 412                 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
 413                                 ->gras_cl_clip_cntl;
 414                 if (fp->writes_pos) {
 415                         val |= A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE;
 416                 }
 417                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 418                 OUT_RING(ring, val);
 419         }
 420
 421         if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
 422                 struct fd3_rasterizer_stateobj *rasterizer =
 423                                 fd3_rasterizer_stateobj(ctx->rasterizer);
 424                 struct fd3_shader_stateobj *fp = prog->fp;
 425                 uint32_t stride_in_vpc;
 426
 427                 stride_in_vpc = align(fp->total_in, 4) / 4;
 428                 if (stride_in_vpc > 0)
 429                         stride_in_vpc = MAX2(stride_in_vpc, 2);
 430
 431                 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 432                 OUT_RING(ring, rasterizer->pc_prim_vtx_cntl |
 433                                 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc));
 434         }
 435
 436         if (dirty & FD_DIRTY_SCISSOR) {
 437                 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 438
 439                 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 440                 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
 441                                 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
 442                 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
 443                                 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
 444
 445                 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
 446                 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
 447                 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
 448                 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
 449         }
 450
 451         if (dirty & FD_DIRTY_VIEWPORT) {
 452                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 453                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
 454                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
 455                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
 456                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
 457                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
 458                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
 459         }
 460
 461         if (dirty & FD_DIRTY_PROG)
 462                 fd3_program_emit(ring, prog, binning);
 463
 464         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 465         OUT_RING(ring, HLSQ_FLUSH);
 466
 467         if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
 468                         /* evil hack to deal sanely with clear path: */
 469                         (prog == &ctx->prog)) {
 470                 emit_constants(ring,  SB_VERT_SHADER,
 471                                 &ctx->constbuf[PIPE_SHADER_VERTEX],
 472                                 (prog->dirty & FD_SHADER_DIRTY_VP) ? prog->vp : NULL);
 473                 emit_constants(ring, SB_FRAG_SHADER,
 474                                 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
 475                                 (prog->dirty & FD_SHADER_DIRTY_FP) ? prog->fp : NULL);
 476         }
 477
 478         if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
 479                 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
 480                 uint32_t i;
 481
 482                 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
 483                         OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 484                         OUT_RING(ring, blend->rb_mrt[i].control);
 485
 486                         OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 487                         OUT_RING(ring, blend->rb_mrt[i].blend_control);
 488                 }
 489         }
 490
 491         if (dirty & FD_DIRTY_BLEND_COLOR) {
 492                 struct pipe_blend_color *bcolor = &ctx->blend_color;
 493                 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
 494                 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
 495                                 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
 496                 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
 497                                 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
 498                 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
 499                                 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
 500                 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
 501                                 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
 502         }
 503
 504         if (dirty & FD_DIRTY_VERTTEX)
 505                 emit_textures(ring, SB_VERT_TEX, &ctx->verttex);
 506
 507         if (dirty & FD_DIRTY_FRAGTEX)
 508                 emit_textures(ring, SB_FRAG_TEX, &ctx->fragtex);
 509
 510         ctx->dirty &= ~dirty;
 511 }
 512
 513 /* emit setup at begin of new cmdstream buffer (don't rely on previous
 514  * state, there could have been a context switch between ioctls):
 515  */
 516 void
 517 fd3_emit_restore(struct fd_context *ctx)
 518 {
 519         struct fd3_context *fd3_ctx = fd3_context(ctx);
 520         struct fd_ringbuffer *ring = ctx->ring;
 521         int i;
 522
 523         if (ctx->screen->gpu_id == 320) {
 524                 OUT_PKT3(ring, CP_REG_RMW, 3);
 525                 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
 526                 OUT_RING(ring, 0xfffcffff);
 527                 OUT_RING(ring, 0x00000000);
 528         }
 529
 530         OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 531         OUT_RING(ring, 0x00007fff);
 532
 533         OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
 534         OUT_RING(ring, 0x08000001);                  /* SP_VS_PVT_MEM_CTRL_REG */
 535         OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
 536         OUT_RING(ring, 0x00000000);                  /* SP_VS_PVT_MEM_SIZE_REG */
 537
 538         OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
 539         OUT_RING(ring, 0x08000001);                  /* SP_FS_PVT_MEM_CTRL_REG */
 540         OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
 541         OUT_RING(ring, 0x00000000);                  /* SP_FS_PVT_MEM_SIZE_REG */
 542
 543         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
 544         OUT_RING(ring, 0x0000000b);                  /* PC_VERTEX_REUSE_BLOCK_CNTL */
 545
 546         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 547         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 548                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 549                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 550
 551         OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
 552         OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 553                         A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 554                         A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
 555         OUT_RING(ring, 0x00000000);        /* RB_ALPHA_REF */
 556
 557         OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
 558         OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
 559                         A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
 560
 561         OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
 562         OUT_RING(ring, 0x00000001);        /* GRAS_TSE_DEBUG_ECO */
 563
 564         OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
 565         OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
 566                         A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
 567                         A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
 568
 569         OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
 570         OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
 571                         A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
 572                         A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
 573
 574         OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
 575         OUT_RING(ring, 0x00000000);        /* VPC_VARY_CYLWRAP_ENABLE_0 */
 576         OUT_RING(ring, 0x00000000);        /* VPC_VARY_CYLWRAP_ENABLE_1 */
 577
 578         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
 579         OUT_RING(ring, 0x00000001);        /* UNKNOWN_0E43 */
 580
 581         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
 582         OUT_RING(ring, 0x00000001);        /* UNKNOWN_0F03 */
 583
 584         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
 585         OUT_RING(ring, 0x00000003);        /* UNKNOWN_0EE0 */
 586
 587         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
 588         OUT_RING(ring, 0x00000001);        /* UNKNOWN_0C3D */
 589
 590         OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
 591         OUT_RING(ring, 0x00000000);        /* HLSQ_PERFCOUNTER0_SELECT */
 592
 593         OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
 594         OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
 595                         A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
 596         OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
 597                         A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
 598
 599         OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
 600         OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
 601         OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
 602                         A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
 603                         A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
 604
 605         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 606         OUT_RING(ring, 0x00000000);                  /* GRAS_CL_CLIP_CNTL */
 607
 608         OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
 609         OUT_RING(ring, 0xffc00010);        /* GRAS_SU_POINT_MINMAX */
 610         OUT_RING(ring, 0x00000008);        /* GRAS_SU_POINT_SIZE */
 611
 612         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 613         OUT_RING(ring, 0xffffffff);        /* PC_RESTART_INDEX */
 614
 615         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 616         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
 617                         A3XX_RB_WINDOW_OFFSET_Y(0));
 618
 619         OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
 620         OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
 621                         A3XX_RB_BLEND_RED_FLOAT(0.0));
 622         OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
 623                         A3XX_RB_BLEND_GREEN_FLOAT(0.0));
 624         OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
 625                         A3XX_RB_BLEND_BLUE_FLOAT(0.0));
 626         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 627                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 628
 629         for (i = 0; i < 6; i++) {
 630                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
 631                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].X */
 632                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].Y */
 633                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].Z */
 634                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].W */
 635         }
 636
 637         OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 638         OUT_RING(ring, 0x00000000);
 639
 640         emit_cache_flush(ring);
 641         fd_rmw_wfi(ctx, ring);
 642 }