1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd3_emit_constant(struct fd_ringbuffer
*ring
,
52 enum adreno_state_block sb
,
53 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
54 const uint32_t *dwords
, struct pipe_resource
*prsc
)
57 enum adreno_state_src src
;
67 /* we have this sometimes, not others.. perhaps we could be clever
68 * and figure out actually when we need to invalidate cache:
70 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
71 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
72 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
73 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
74 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 emit_constants(struct fd_ringbuffer
*ring
,
97 enum adreno_state_block sb
,
98 struct fd_constbuf_stateobj
*constbuf
,
99 struct fd3_shader_stateobj
*shader
)
101 uint32_t enabled_mask
= constbuf
->enabled_mask
;
105 // XXX TODO only emit dirty consts.. but we need to keep track if
106 // they are clobbered by a clear, gmem2mem, or mem2gmem..
107 constbuf
->dirty_mask
= enabled_mask
;
109 /* emit user constants: */
110 while (enabled_mask
) {
111 unsigned index
= ffs(enabled_mask
) - 1;
112 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
113 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
115 // I expect that size should be a multiple of vec4's:
116 assert(size
== align(size
, 4));
118 /* gallium could have const-buffer still bound, even though the
119 * shader is not using it. Writing consts above constlen (or
120 * rather, HLSQ_{VS,FS}_CONTROL_REG.CONSTLENGTH) will cause a
123 if ((base
/ 4) >= shader
->constlen
)
126 if (constbuf
->dirty_mask
& (1 << index
)) {
127 fd3_emit_constant(ring
, sb
, base
,
128 cb
->buffer_offset
, size
,
129 cb
->user_buffer
, cb
->buffer
);
130 constbuf
->dirty_mask
&= ~(1 << index
);
134 enabled_mask
&= ~(1 << index
);
137 /* emit shader immediates: */
139 for (i
= 0; i
< shader
->immediates_count
; i
++) {
140 fd3_emit_constant(ring
, sb
,
141 4 * (shader
->first_immediate
+ i
),
142 0, 4, shader
->immediates
[i
].val
, NULL
);
147 #define VERT_TEX_OFF 0
148 #define FRAG_TEX_OFF 16
149 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
152 emit_textures(struct fd_ringbuffer
*ring
,
153 enum adreno_state_block sb
,
154 struct fd_texture_stateobj
*tex
)
156 static const unsigned tex_off
[] = {
157 [SB_VERT_TEX
] = VERT_TEX_OFF
,
158 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
160 static const enum adreno_state_block mipaddr
[] = {
161 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
162 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
166 if (tex
->num_samplers
> 0) {
167 /* output sampler state: */
168 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
169 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
170 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
171 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
172 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
173 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
174 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
175 for (i
= 0; i
< tex
->num_samplers
; i
++) {
176 struct fd3_sampler_stateobj
*sampler
=
177 fd3_sampler_stateobj(tex
->samplers
[i
]);
178 OUT_RING(ring
, sampler
->texsamp0
);
179 OUT_RING(ring
, sampler
->texsamp1
);
183 if (tex
->num_textures
> 0) {
184 /* emit texture state: */
185 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
186 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
187 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
188 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
189 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
190 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
191 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
192 for (i
= 0; i
< tex
->num_textures
; i
++) {
193 struct fd3_pipe_sampler_view
*view
=
194 fd3_pipe_sampler_view(tex
->textures
[i
]);
195 OUT_RING(ring
, view
->texconst0
);
196 OUT_RING(ring
, view
->texconst1
);
197 OUT_RING(ring
, view
->texconst2
|
198 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
199 OUT_RING(ring
, view
->texconst3
);
203 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
204 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
205 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
206 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
207 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
208 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
209 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
210 for (i
= 0; i
< tex
->num_textures
; i
++) {
211 struct fd3_pipe_sampler_view
*view
=
212 fd3_pipe_sampler_view(tex
->textures
[i
]);
213 struct fd_resource
*rsc
= view
->tex_resource
;
215 for (j
= 0; j
< view
->mipaddrs
; j
++) {
216 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, j
);
217 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
220 /* pad the remaining entries w/ null: */
221 for (; j
< BASETABLE_SZ
; j
++) {
222 OUT_RING(ring
, 0x00000000);
229 emit_cache_flush(struct fd_ringbuffer
*ring
)
231 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
232 OUT_RING(ring
, CACHE_FLUSH
);
234 /* probably only really needed on a320: */
235 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
236 OUT_RING(ring
, 0x00000000);
237 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
238 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
239 OUT_RING(ring
, 0); /* NumIndices */
241 OUT_PKT3(ring
, CP_NOP
, 4);
242 OUT_RING(ring
, 0x00000000);
243 OUT_RING(ring
, 0x00000000);
244 OUT_RING(ring
, 0x00000000);
245 OUT_RING(ring
, 0x00000000);
248 /* emit texture state for mem->gmem restore operation.. eventually it would
249 * be good to get rid of this and use normal CSO/etc state for more of these
250 * special cases, but for now the compiler is not sufficient..
253 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, struct pipe_surface
*psurf
)
255 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
256 enum pipe_format format
= fd3_gmem_restore_format(psurf
->format
);
258 /* output sampler state: */
259 OUT_PKT3(ring
, CP_LOAD_STATE
, 4);
260 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
261 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
262 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
263 CP_LOAD_STATE_0_NUM_UNIT(1));
264 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
265 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
266 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
267 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
268 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
269 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
270 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
271 OUT_RING(ring
, 0x00000000);
273 /* emit texture state: */
274 OUT_PKT3(ring
, CP_LOAD_STATE
, 6);
275 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
276 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
277 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
278 CP_LOAD_STATE_0_NUM_UNIT(1));
279 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
280 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
281 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf
->format
)) |
282 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
283 fd3_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
284 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
285 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
286 A3XX_TEX_CONST_1_WIDTH(psurf
->width
) |
287 A3XX_TEX_CONST_1_HEIGHT(psurf
->height
));
288 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(rsc
->slices
[0].pitch
* rsc
->cpp
) |
289 A3XX_TEX_CONST_2_INDX(0));
290 OUT_RING(ring
, 0x00000000);
293 OUT_PKT3(ring
, CP_LOAD_STATE
, 3);
294 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
295 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
296 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
297 CP_LOAD_STATE_0_NUM_UNIT(1));
298 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
299 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
300 OUT_RELOC(ring
, rsc
->bo
, 0, 0, 0);
304 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
,
305 struct fd_program_stateobj
*prog
,
306 struct fd3_vertex_buf
*vbufs
, uint32_t n
)
308 struct fd3_shader_stateobj
*vp
= prog
->vp
;
311 n
= MIN2(n
, vp
->inputs_count
);
313 for (i
= 0; i
< n
; i
++) {
314 struct pipe_resource
*prsc
= vbufs
[i
].prsc
;
315 struct fd_resource
*rsc
= fd_resource(prsc
);
316 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(vbufs
[i
].format
);
317 bool switchnext
= (i
!= (n
- 1));
318 uint32_t fs
= util_format_get_blocksize(vbufs
[i
].format
);
320 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(i
), 2);
321 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
322 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs
[i
].stride
) |
323 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
324 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i
) |
325 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
326 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 0, 0);
328 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(i
), 1);
329 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
330 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
331 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
332 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
333 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
334 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
335 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
340 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
341 uint32_t dirty
, bool binning
)
343 emit_marker(ring
, 5);
345 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
346 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
347 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
348 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
349 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
352 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
353 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
354 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
357 fd3_emit_rbrc_draw_state(ctx
, ring
, zsa
->rb_render_control
);
359 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
360 OUT_RING(ring
, zsa
->rb_alpha_ref
);
362 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
363 OUT_RING(ring
, zsa
->rb_depth_control
);
365 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
366 OUT_RING(ring
, zsa
->rb_stencil_control
);
368 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
369 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
370 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
371 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
372 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
375 if (dirty
& FD_DIRTY_RASTERIZER
) {
376 struct fd3_rasterizer_stateobj
*rasterizer
=
377 fd3_rasterizer_stateobj(ctx
->rasterizer
);
379 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
380 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
382 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
383 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
384 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
386 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
387 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
388 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
390 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
391 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
394 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
395 struct fd3_rasterizer_stateobj
*rasterizer
=
396 fd3_rasterizer_stateobj(ctx
->rasterizer
);
397 struct fd3_shader_stateobj
*fp
= ctx
->prog
.fp
;
398 uint32_t stride_in_vpc
;
400 stride_in_vpc
= align(fp
->total_in
, 4) / 4;
401 if (stride_in_vpc
> 0)
402 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
404 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
405 OUT_RING(ring
, rasterizer
->pc_prim_vtx_cntl
|
406 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
));
409 if (dirty
& FD_DIRTY_SCISSOR
) {
410 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
412 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
413 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
414 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
415 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
416 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
418 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
419 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
420 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
421 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
424 if (dirty
& FD_DIRTY_VIEWPORT
) {
425 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
426 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
427 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
428 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
429 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
430 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
431 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
434 if (dirty
& FD_DIRTY_PROG
)
435 fd3_program_emit(ring
, &ctx
->prog
, binning
);
437 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
438 OUT_RING(ring
, HLSQ_FLUSH
);
440 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
441 struct fd_program_stateobj
*prog
= &ctx
->prog
;
443 emit_constants(ring
, SB_VERT_SHADER
,
444 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
445 (prog
->dirty
& FD_SHADER_DIRTY_VP
) ? prog
->vp
: NULL
);
446 emit_constants(ring
, SB_FRAG_SHADER
,
447 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
448 (prog
->dirty
& FD_SHADER_DIRTY_FP
) ? prog
->fp
: NULL
);
451 if (dirty
& FD_DIRTY_BLEND
) {
452 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
455 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
456 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
457 OUT_RING(ring
, blend
->rb_mrt
[i
].control
);
459 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
460 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
464 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
465 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
466 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
467 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
468 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
469 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
470 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
471 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
472 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
473 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
474 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
477 if (dirty
& FD_DIRTY_VERTTEX
)
478 emit_textures(ring
, SB_VERT_TEX
, &ctx
->verttex
);
480 if (dirty
& FD_DIRTY_FRAGTEX
)
481 emit_textures(ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
483 ctx
->dirty
&= ~dirty
;
486 /* emit setup at begin of new cmdstream buffer (don't rely on previous
487 * state, there could have been a context switch between ioctls):
490 fd3_emit_restore(struct fd_context
*ctx
)
492 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
493 struct fd_ringbuffer
*ring
= ctx
->ring
;
496 if (ctx
->screen
->gpu_id
== 320) {
497 OUT_PKT3(ring
, CP_REG_RMW
, 3);
498 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
499 OUT_RING(ring
, 0xfffcffff);
500 OUT_RING(ring
, 0x00000000);
503 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
504 OUT_RING(ring
, 0x00007fff);
506 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
507 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
508 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
509 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
511 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
512 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
513 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
514 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
516 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
517 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
519 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
520 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
521 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
522 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
524 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
525 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
526 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
527 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
528 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
530 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
531 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
532 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
534 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
535 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
537 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
538 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
539 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
540 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
542 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
543 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
544 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
545 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
547 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
548 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
549 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
551 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
552 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
554 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
555 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
557 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
558 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
560 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
561 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
563 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
564 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
566 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
567 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
568 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
569 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
570 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
572 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
573 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
574 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
575 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
576 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
578 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
579 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
581 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
582 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
583 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
585 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
586 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
588 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
589 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
590 A3XX_RB_WINDOW_OFFSET_Y(0));
592 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
593 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
594 A3XX_RB_BLEND_RED_FLOAT(0.0));
595 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
596 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
597 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
598 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
599 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
600 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
602 for (i
= 0; i
< 6; i
++) {
603 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
604 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
605 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
606 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
607 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
610 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
611 OUT_RING(ring
, 0x00000000);
613 emit_cache_flush(ring
);
614 fd_rmw_wfi(ctx
, ring
);