1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd3_emit_constant(struct fd_ringbuffer
*ring
,
52 enum adreno_state_block sb
,
53 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
54 const uint32_t *dwords
, struct pipe_resource
*prsc
)
57 enum adreno_state_src src
;
67 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
68 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
69 CP_LOAD_STATE_0_STATE_SRC(src
) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
73 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
74 OUT_RELOC(ring
, bo
, offset
,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
77 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
79 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
81 for (i
= 0; i
< sz
; i
++) {
82 OUT_RING(ring
, dwords
[i
]);
87 emit_constants(struct fd_ringbuffer
*ring
,
88 enum adreno_state_block sb
,
89 struct fd_constbuf_stateobj
*constbuf
,
90 struct ir3_shader_variant
*shader
)
92 uint32_t enabled_mask
= constbuf
->enabled_mask
;
93 uint32_t first_immediate
;
97 // XXX TODO only emit dirty consts.. but we need to keep track if
98 // they are clobbered by a clear, gmem2mem, or mem2gmem..
99 constbuf
->dirty_mask
= enabled_mask
;
101 /* in particular, with binning shader and a unneeded consts no
102 * longer referenced, we could end up w/ constlen that is smaller
103 * than first_immediate. In that case truncate the user consts
104 * early to avoid HLSQ lockup caused by writing too many consts
106 first_immediate
= MIN2(shader
->first_immediate
, shader
->constlen
);
108 /* emit user constants: */
109 while (enabled_mask
) {
110 unsigned index
= ffs(enabled_mask
) - 1;
111 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
112 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
114 // I expect that size should be a multiple of vec4's:
115 assert(size
== align(size
, 4));
117 /* gallium could leave const buffers bound above what the
118 * current shader uses.. don't let that confuse us.
120 if (base
>= (4 * first_immediate
))
123 if (constbuf
->dirty_mask
& (1 << index
)) {
124 /* and even if the start of the const buffer is before
125 * first_immediate, the end may not be:
127 size
= MIN2(size
, (4 * first_immediate
) - base
);
128 fd3_emit_constant(ring
, sb
, base
,
129 cb
->buffer_offset
, size
,
130 cb
->user_buffer
, cb
->buffer
);
131 constbuf
->dirty_mask
&= ~(1 << index
);
135 enabled_mask
&= ~(1 << index
);
138 /* emit shader immediates: */
140 for (i
= 0; i
< shader
->immediates_count
; i
++) {
141 base
= 4 * (shader
->first_immediate
+ i
);
142 if (base
>= (4 * shader
->constlen
))
144 fd3_emit_constant(ring
, sb
, base
,
145 0, 4, shader
->immediates
[i
].val
, NULL
);
150 #define VERT_TEX_OFF 0
151 #define FRAG_TEX_OFF 16
152 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
155 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
156 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
158 static const unsigned tex_off
[] = {
159 [SB_VERT_TEX
] = VERT_TEX_OFF
,
160 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
162 static const enum adreno_state_block mipaddr
[] = {
163 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
164 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
166 static const uint32_t bcolor_reg
[] = {
167 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
168 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
170 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
174 u_upload_alloc(fd3_ctx
->border_color_uploader
,
175 0, 2 * PIPE_MAX_SAMPLERS
* BORDERCOLOR_SIZE
, &off
,
176 &fd3_ctx
->border_color_buf
,
179 if (tex
->num_samplers
> 0) {
180 /* output sampler state: */
181 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
182 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
183 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
184 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
185 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
186 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
187 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
188 for (i
= 0; i
< tex
->num_samplers
; i
++) {
189 static const struct fd3_sampler_stateobj dummy_sampler
= {};
190 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
191 fd3_sampler_stateobj(tex
->samplers
[i
]) :
193 uint16_t *bcolor
= (uint16_t *)((uint8_t *)ptr
+
194 (BORDERCOLOR_SIZE
* tex_off
[sb
]) +
195 (BORDERCOLOR_SIZE
* i
));
197 /* TODO not quite sure if bcolor is pre or post swizzle: */
198 for (j
= 0; j
< 4; j
++) {
200 util_float_to_half(sampler
->base
.border_color
.f
[j
]);
203 OUT_RING(ring
, sampler
->texsamp0
);
204 OUT_RING(ring
, sampler
->texsamp1
);
208 if (tex
->num_textures
> 0) {
209 /* emit texture state: */
210 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
211 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
212 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
213 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
214 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
215 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
216 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
217 for (i
= 0; i
< tex
->num_textures
; i
++) {
218 static const struct fd3_pipe_sampler_view dummy_view
= {};
219 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
220 fd3_pipe_sampler_view(tex
->textures
[i
]) :
222 OUT_RING(ring
, view
->texconst0
);
223 OUT_RING(ring
, view
->texconst1
);
224 OUT_RING(ring
, view
->texconst2
|
225 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
226 OUT_RING(ring
, view
->texconst3
);
230 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
231 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
232 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
233 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
234 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
235 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
236 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
237 for (i
= 0; i
< tex
->num_textures
; i
++) {
238 static const struct fd3_pipe_sampler_view dummy_view
= {
239 .base
.u
.tex
.first_level
= 1,
241 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
242 fd3_pipe_sampler_view(tex
->textures
[i
]) :
244 struct fd_resource
*rsc
= view
->tex_resource
;
245 unsigned start
= view
->base
.u
.tex
.first_level
;
246 unsigned end
= view
->base
.u
.tex
.last_level
;
248 for (j
= 0; j
< (end
- start
+ 1); j
++) {
249 struct fd_resource_slice
*slice
=
250 fd_resource_slice(rsc
, j
+ start
);
251 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
254 /* pad the remaining entries w/ null: */
255 for (; j
< BASETABLE_SZ
; j
++) {
256 OUT_RING(ring
, 0x00000000);
261 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
262 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
264 u_upload_unmap(fd3_ctx
->border_color_uploader
);
267 /* emit texture state for mem->gmem restore operation.. eventually it would
268 * be good to get rid of this and use normal CSO/etc state for more of these
269 * special cases, but for now the compiler is not sufficient..
271 * Also, for using normal state, not quite sure how to handle the special
272 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
275 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, struct pipe_surface
*psurf
)
277 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
278 enum pipe_format format
= fd3_gmem_restore_format(psurf
->format
);
280 /* output sampler state: */
281 OUT_PKT3(ring
, CP_LOAD_STATE
, 4);
282 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
283 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
284 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
285 CP_LOAD_STATE_0_NUM_UNIT(1));
286 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
287 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
288 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
289 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
290 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
291 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
292 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
293 OUT_RING(ring
, 0x00000000);
295 /* emit texture state: */
296 OUT_PKT3(ring
, CP_LOAD_STATE
, 6);
297 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
298 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
299 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
300 CP_LOAD_STATE_0_NUM_UNIT(1));
301 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
302 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
303 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
304 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
305 fd3_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
306 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
307 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
308 A3XX_TEX_CONST_1_WIDTH(psurf
->width
) |
309 A3XX_TEX_CONST_1_HEIGHT(psurf
->height
));
310 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(rsc
->slices
[0].pitch
* rsc
->cpp
) |
311 A3XX_TEX_CONST_2_INDX(0));
312 OUT_RING(ring
, 0x00000000);
315 OUT_PKT3(ring
, CP_LOAD_STATE
, 3);
316 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
317 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
318 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
319 CP_LOAD_STATE_0_NUM_UNIT(1));
320 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
321 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
322 OUT_RELOC(ring
, rsc
->bo
, 0, 0, 0);
326 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
,
327 struct ir3_shader_variant
*vp
,
328 struct fd3_vertex_buf
*vbufs
, uint32_t n
)
330 uint32_t i
, j
, last
= 0;
331 uint32_t total_in
= 0;
333 n
= MIN2(n
, vp
->inputs_count
);
335 for (i
= 0; i
< n
; i
++)
336 if (vp
->inputs
[i
].compmask
)
339 for (i
= 0, j
= 0; i
<= last
; i
++) {
340 if (vp
->inputs
[i
].compmask
) {
341 struct pipe_resource
*prsc
= vbufs
[i
].prsc
;
342 struct fd_resource
*rsc
= fd_resource(prsc
);
343 enum pipe_format pfmt
= vbufs
[i
].format
;
344 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
345 bool switchnext
= (i
!= last
);
346 bool isint
= util_format_is_pure_integer(pfmt
);
347 uint32_t fs
= util_format_get_blocksize(pfmt
);
349 debug_assert(fmt
!= ~0);
351 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
352 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
353 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs
[i
].stride
) |
354 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
355 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
356 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
357 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 0, 0);
359 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
360 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
361 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
362 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
363 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
364 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
365 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
366 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
367 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
368 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
370 total_in
+= vp
->inputs
[i
].ncomp
;
375 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
376 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
377 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
378 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
379 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
380 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
381 A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
382 A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
386 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
387 const struct pipe_draw_info
*info
, struct fd_program_stateobj
*prog
,
388 struct ir3_shader_key key
, uint32_t dirty
)
390 struct ir3_shader_variant
*vp
;
391 struct ir3_shader_variant
*fp
;
393 fp
= fd3_shader_variant(prog
->fp
, key
);
394 vp
= fd3_shader_variant(prog
->vp
, key
);
396 emit_marker(ring
, 5);
398 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
399 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
400 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
401 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
402 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
405 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) && !key
.binning_pass
) {
406 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
;
408 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
409 val
|= COND(fp
->frag_coord
, A3XX_RB_RENDER_CONTROL_XCOORD
|
410 A3XX_RB_RENDER_CONTROL_YCOORD
|
411 A3XX_RB_RENDER_CONTROL_ZCOORD
|
412 A3XX_RB_RENDER_CONTROL_WCOORD
);
414 /* I suppose if we needed to (which I don't *think* we need
415 * to), we could emit this for binning pass too. But we
416 * would need to keep a different patch-list for binning
420 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
421 OUT_RINGP(ring
, val
, &fd3_context(ctx
)->rbrc_patches
);
424 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
425 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
426 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
428 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
429 OUT_RING(ring
, zsa
->rb_alpha_ref
);
431 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
432 OUT_RING(ring
, zsa
->rb_stencil_control
);
434 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
435 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
436 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
437 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
438 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
441 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
442 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
443 if (fp
->writes_pos
) {
444 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
445 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
447 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
451 if (dirty
& FD_DIRTY_RASTERIZER
) {
452 struct fd3_rasterizer_stateobj
*rasterizer
=
453 fd3_rasterizer_stateobj(ctx
->rasterizer
);
455 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
456 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
458 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
459 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
460 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
462 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
463 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
464 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
467 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
468 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
470 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
471 val
|= COND(fp
->frag_coord
, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
472 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
473 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
477 /* NOTE: since primitive_restart is not actually part of any
478 * state object, we need to make sure that we always emit
479 * PRIM_VTX_CNTL.. either that or be more clever and detect
483 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
486 if (!key
.binning_pass
) {
487 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
488 if (stride_in_vpc
> 0)
489 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
490 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
493 if (info
&& info
->indexed
&& info
->primitive_restart
) {
494 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
497 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
499 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
503 if (dirty
& FD_DIRTY_SCISSOR
) {
504 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
506 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
507 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
508 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
509 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
510 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
512 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
513 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
514 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
515 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
518 if (dirty
& FD_DIRTY_VIEWPORT
) {
520 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
521 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
522 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
523 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
524 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
525 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
526 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
529 if (dirty
& FD_DIRTY_PROG
) {
530 bool flat
= ctx
->rasterizer
&& ctx
->rasterizer
->flatshade
;
531 fd3_program_emit(ring
, prog
, key
, flat
);
534 /* TODO we should not need this or fd_wfi() before emit_constants():
536 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
537 OUT_RING(ring
, HLSQ_FLUSH
);
539 if ((dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) &&
540 /* evil hack to deal sanely with clear path: */
541 (prog
== &ctx
->prog
)) {
543 emit_constants(ring
, SB_VERT_SHADER
,
544 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
545 (prog
->dirty
& FD_SHADER_DIRTY_VP
) ? vp
: NULL
);
546 if (!key
.binning_pass
) {
547 emit_constants(ring
, SB_FRAG_SHADER
,
548 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
549 (prog
->dirty
& FD_SHADER_DIRTY_FP
) ? fp
: NULL
);
553 if ((dirty
& FD_DIRTY_BLEND
) && ctx
->blend
) {
554 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
557 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
558 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
559 OUT_RING(ring
, blend
->rb_mrt
[i
].control
);
561 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
562 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
566 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
567 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
568 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
569 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
570 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
571 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
572 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
573 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
574 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
575 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
576 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
579 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
))
582 if (dirty
& FD_DIRTY_VERTTEX
) {
584 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
586 dirty
&= ~FD_DIRTY_VERTTEX
;
589 if (dirty
& FD_DIRTY_FRAGTEX
) {
591 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
593 dirty
&= ~FD_DIRTY_FRAGTEX
;
596 ctx
->dirty
&= ~dirty
;
599 /* emit setup at begin of new cmdstream buffer (don't rely on previous
600 * state, there could have been a context switch between ioctls):
603 fd3_emit_restore(struct fd_context
*ctx
)
605 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
606 struct fd_ringbuffer
*ring
= ctx
->ring
;
609 if (ctx
->screen
->gpu_id
== 320) {
610 OUT_PKT3(ring
, CP_REG_RMW
, 3);
611 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
612 OUT_RING(ring
, 0xfffcffff);
613 OUT_RING(ring
, 0x00000000);
617 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
618 OUT_RING(ring
, 0x00007fff);
620 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
621 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
622 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
623 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
625 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
626 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
627 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
628 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
630 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
631 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
633 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
634 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
635 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
636 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
638 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
639 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
640 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
641 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
642 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
644 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
645 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
646 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
648 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
649 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
651 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
652 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
653 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
654 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
656 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
657 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
658 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
659 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
661 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
662 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
663 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
665 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
666 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
668 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
669 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
671 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
672 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
674 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
675 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
677 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
678 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
680 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
681 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
682 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
683 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
684 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
686 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
687 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
688 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
689 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
690 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
692 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
693 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
695 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
696 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
697 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
699 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
700 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
702 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
703 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
704 A3XX_RB_WINDOW_OFFSET_Y(0));
706 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
707 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
708 A3XX_RB_BLEND_RED_FLOAT(0.0));
709 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
710 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
711 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
712 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
713 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
714 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
716 for (i
= 0; i
< 6; i
++) {
717 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
718 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
719 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
720 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
721 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
724 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
725 OUT_RING(ring
, 0x00000000);
727 fd_event_write(ctx
, ring
, CACHE_FLUSH
);
729 if (is_a3xx_p0(ctx
->screen
)) {
730 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
731 OUT_RING(ring
, 0x00000000);
732 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
733 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
734 OUT_RING(ring
, 0); /* NumIndices */
737 OUT_PKT3(ring
, CP_NOP
, 4);
738 OUT_RING(ring
, 0x00000000);
739 OUT_RING(ring
, 0x00000000);
740 OUT_RING(ring
, 0x00000000);
741 OUT_RING(ring
, 0x00000000);
745 ctx
->needs_rb_fbd
= true;