1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd3_emit_constant(struct fd_ringbuffer
*ring
,
52 enum adreno_state_block sb
,
53 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
54 const uint32_t *dwords
, struct pipe_resource
*prsc
)
57 enum adreno_state_src src
;
67 /* we have this sometimes, not others.. perhaps we could be clever
68 * and figure out actually when we need to invalidate cache:
70 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
71 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
72 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
73 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
74 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 emit_constants(struct fd_ringbuffer
*ring
,
97 enum adreno_state_block sb
,
98 struct fd_constbuf_stateobj
*constbuf
,
99 struct fd3_shader_stateobj
*shader
)
101 uint32_t enabled_mask
= constbuf
->enabled_mask
;
105 // XXX TODO only emit dirty consts.. but we need to keep track if
106 // they are clobbered by a clear, gmem2mem, or mem2gmem..
107 constbuf
->dirty_mask
= enabled_mask
;
109 /* emit user constants: */
110 while (enabled_mask
) {
111 unsigned index
= ffs(enabled_mask
) - 1;
112 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
113 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
115 // I expect that size should be a multiple of vec4's:
116 assert(size
== align(size
, 4));
118 /* gallium could have const-buffer still bound, even though the
119 * shader is not using it. Writing consts above constlen (or
120 * rather, HLSQ_{VS,FS}_CONTROL_REG.CONSTLENGTH) will cause a
123 if ((base
/ 4) >= shader
->constlen
)
126 if (constbuf
->dirty_mask
& (1 << index
)) {
127 fd3_emit_constant(ring
, sb
, base
,
128 cb
->buffer_offset
, size
,
129 cb
->user_buffer
, cb
->buffer
);
130 constbuf
->dirty_mask
&= ~(1 << index
);
134 enabled_mask
&= ~(1 << index
);
137 /* emit shader immediates: */
139 for (i
= 0; i
< shader
->immediates_count
; i
++) {
140 fd3_emit_constant(ring
, sb
,
141 4 * (shader
->first_immediate
+ i
),
142 0, 4, shader
->immediates
[i
].val
, NULL
);
147 #define VERT_TEX_OFF 0
148 #define FRAG_TEX_OFF 16
149 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
152 emit_textures(struct fd_ringbuffer
*ring
,
153 enum adreno_state_block sb
,
154 struct fd_texture_stateobj
*tex
)
156 static const unsigned tex_off
[] = {
157 [SB_VERT_TEX
] = VERT_TEX_OFF
,
158 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
160 static const enum adreno_state_block mipaddr
[] = {
161 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
162 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
166 assert(tex
->num_samplers
== tex
->num_textures
); // TODO check..
168 if (!tex
->num_samplers
)
171 /* output sampler state: */
172 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
173 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
174 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
175 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
176 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
177 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
178 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
179 for (i
= 0; i
< tex
->num_samplers
; i
++) {
180 struct fd3_sampler_stateobj
*sampler
=
181 fd3_sampler_stateobj(tex
->samplers
[i
]);
182 OUT_RING(ring
, sampler
->texsamp0
);
183 OUT_RING(ring
, sampler
->texsamp1
);
186 /* emit texture state: */
187 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
188 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
189 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
190 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
191 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
192 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
193 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
194 for (i
= 0; i
< tex
->num_textures
; i
++) {
195 struct fd3_pipe_sampler_view
*view
=
196 fd3_pipe_sampler_view(tex
->textures
[i
]);
197 OUT_RING(ring
, view
->texconst0
);
198 OUT_RING(ring
, view
->texconst1
);
199 OUT_RING(ring
, view
->texconst2
|
200 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
201 OUT_RING(ring
, view
->texconst3
);
205 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
206 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
207 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
208 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
209 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
210 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
211 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
212 for (i
= 0; i
< tex
->num_textures
; i
++) {
213 struct fd3_pipe_sampler_view
*view
=
214 fd3_pipe_sampler_view(tex
->textures
[i
]);
215 struct fd_resource
*rsc
= view
->tex_resource
;
217 for (j
= 0; j
< view
->mipaddrs
; j
++) {
218 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, j
);
219 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
222 /* pad the remaining entries w/ null: */
223 for (; j
< BASETABLE_SZ
; j
++) {
224 OUT_RING(ring
, 0x00000000);
230 emit_cache_flush(struct fd_ringbuffer
*ring
)
232 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
233 OUT_RING(ring
, CACHE_FLUSH
);
235 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
236 OUT_RING(ring
, 0x00000000);
237 OUT_RING(ring
, DRAW(DI_PT_POINTLIST
, DI_SRC_SEL_AUTO_INDEX
,
238 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
239 OUT_RING(ring
, 0); /* NumIndices */
241 OUT_PKT3(ring
, CP_NOP
, 4);
242 OUT_RING(ring
, 0x00000000);
243 OUT_RING(ring
, 0x00000000);
244 OUT_RING(ring
, 0x00000000);
245 OUT_RING(ring
, 0x00000000);
250 /* emit texture state for mem->gmem restore operation.. eventually it would
251 * be good to get rid of this and use normal CSO/etc state for more of these
252 * special cases, but for now the compiler is not sufficient..
255 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, struct pipe_surface
*psurf
)
257 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
259 /* output sampler state: */
260 OUT_PKT3(ring
, CP_LOAD_STATE
, 4);
261 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
262 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
263 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
264 CP_LOAD_STATE_0_NUM_UNIT(1));
265 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
266 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
267 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
268 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
269 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
270 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
271 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
272 OUT_RING(ring
, 0x00000000);
274 /* emit texture state: */
275 OUT_PKT3(ring
, CP_LOAD_STATE
, 6);
276 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
277 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
278 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
279 CP_LOAD_STATE_0_NUM_UNIT(1));
280 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
281 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
282 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf
->format
)) |
284 fd3_tex_swiz(psurf
->format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
285 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
286 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
287 A3XX_TEX_CONST_1_WIDTH(psurf
->width
) |
288 A3XX_TEX_CONST_1_HEIGHT(psurf
->height
));
289 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(rsc
->slices
[0].pitch
* rsc
->cpp
) |
290 A3XX_TEX_CONST_2_INDX(0));
291 OUT_RING(ring
, 0x00000000);
294 OUT_PKT3(ring
, CP_LOAD_STATE
, 3);
295 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
296 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
297 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
298 CP_LOAD_STATE_0_NUM_UNIT(1));
299 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
300 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
301 OUT_RELOC(ring
, rsc
->bo
, 0, 0, 0);
305 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
,
306 struct fd_program_stateobj
*prog
,
307 struct fd3_vertex_buf
*vbufs
, uint32_t n
)
309 struct fd3_shader_stateobj
*vp
= prog
->vp
;
312 n
= MIN2(n
, vp
->inputs_count
);
314 for (i
= 0; i
< n
; i
++) {
315 struct pipe_resource
*prsc
= vbufs
[i
].prsc
;
316 struct fd_resource
*rsc
= fd_resource(prsc
);
317 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(vbufs
[i
].format
);
318 bool switchnext
= (i
!= (n
- 1));
319 uint32_t fs
= util_format_get_blocksize(vbufs
[i
].format
);
321 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(i
), 2);
322 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
323 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs
[i
].stride
) |
324 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
325 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i
) |
326 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
327 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 0, 0);
329 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(i
), 1);
330 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
331 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
332 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
333 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
334 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
335 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
336 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
341 fd3_emit_state(struct fd_context
*ctx
, uint32_t dirty
)
343 struct fd_ringbuffer
*ring
= ctx
->ring
;
345 emit_marker(ring
, 5);
347 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
348 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
349 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
350 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
351 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
354 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
355 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
356 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
358 fd3_emit_rbrc_draw_state(ring
, zsa
->rb_render_control
);
360 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
361 OUT_RING(ring
, zsa
->rb_depth_control
);
363 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
364 OUT_RING(ring
, zsa
->rb_stencil_control
);
366 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
367 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
368 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
369 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
370 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
373 if (dirty
& FD_DIRTY_RASTERIZER
) {
374 struct fd3_rasterizer_stateobj
*rasterizer
=
375 fd3_rasterizer_stateobj(ctx
->rasterizer
);
377 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
378 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
380 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
381 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
382 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
384 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
385 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
386 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
388 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
389 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
392 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
393 struct fd3_rasterizer_stateobj
*rasterizer
=
394 fd3_rasterizer_stateobj(ctx
->rasterizer
);
395 struct fd3_shader_stateobj
*fp
= ctx
->prog
.fp
;
396 uint32_t stride_in_vpc
;
398 stride_in_vpc
= align(fp
->total_in
, 4) / 4;
399 if (stride_in_vpc
> 0)
400 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
402 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
403 OUT_RING(ring
, rasterizer
->pc_prim_vtx_cntl
|
404 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
));
407 if (dirty
& FD_DIRTY_SCISSOR
) {
408 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
410 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
411 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
412 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
413 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
414 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
416 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
417 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
418 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
419 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
422 if (dirty
& FD_DIRTY_VIEWPORT
) {
423 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
424 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
425 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
426 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
427 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
428 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
429 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
432 if (dirty
& FD_DIRTY_PROG
)
433 fd3_program_emit(ring
, &ctx
->prog
);
435 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
436 struct fd_program_stateobj
*prog
= &ctx
->prog
;
438 emit_constants(ring
, SB_VERT_SHADER
,
439 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
440 (prog
->dirty
& FD_SHADER_DIRTY_VP
) ? prog
->vp
: NULL
);
441 emit_constants(ring
, SB_FRAG_SHADER
,
442 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
443 (prog
->dirty
& FD_SHADER_DIRTY_FP
) ? prog
->fp
: NULL
);
446 if (dirty
& FD_DIRTY_BLEND
) {
447 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
450 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
451 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
452 OUT_RING(ring
, blend
->rb_mrt
[i
].control
);
454 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
455 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
459 if (dirty
& FD_DIRTY_VERTTEX
)
460 emit_textures(ring
, SB_VERT_TEX
, &ctx
->verttex
);
462 if (dirty
& FD_DIRTY_FRAGTEX
)
463 emit_textures(ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
465 ctx
->dirty
&= ~dirty
;
468 /* emit setup at begin of new cmdstream buffer (don't rely on previous
469 * state, there could have been a context switch between ioctls):
472 fd3_emit_restore(struct fd_context
*ctx
)
474 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
475 struct fd_ringbuffer
*ring
= ctx
->ring
;
478 OUT_PKT3(ring
, CP_REG_RMW
, 3);
479 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
480 OUT_RING(ring
, 0xfffcffff);
481 OUT_RING(ring
, 0x00000000);
483 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
484 OUT_RING(ring
, 0x00007fff);
486 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG
, 3);
487 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
488 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
489 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
491 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG
, 3);
492 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
493 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
494 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
496 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
497 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
499 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
500 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
501 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
502 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
504 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
505 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
506 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
507 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
508 OUT_RING(ring
, 0x00000000); /* UNKNOWN_20C3 */
510 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
511 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
512 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
514 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C81
, 1);
515 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C81 */
517 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
518 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
519 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
520 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
522 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
523 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
524 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
525 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
527 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
528 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
529 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
531 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
532 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
534 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
535 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
537 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
538 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
540 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
541 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
543 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
544 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
546 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
547 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
548 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
549 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
550 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
552 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG
, 1);
553 OUT_RING(ring
, 0x00000001); /* UCHE_CACHE_MODE_CONTROL_REG */
555 OUT_PKT0(ring
, REG_A3XX_VSC_SIZE_ADDRESS
, 1);
556 OUT_RELOC(ring
, fd3_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
558 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
559 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
561 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
562 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
563 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
565 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
566 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
568 OUT_PKT0(ring
, REG_A3XX_PA_SC_WINDOW_OFFSET
, 1);
569 OUT_RING(ring
, A3XX_PA_SC_WINDOW_OFFSET_X(0) |
570 A3XX_PA_SC_WINDOW_OFFSET_Y(0));
572 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
573 OUT_RING(ring
, 0x00000000); /* RB_BLEND_RED */
574 OUT_RING(ring
, 0x00000000); /* RB_BLEND_GREEN */
575 OUT_RING(ring
, 0x00000000); /* RB_BLEND_BLUE */
576 OUT_RING(ring
, 0x3c0000ff); /* RB_BLEND_ALPHA */
578 for (i
= 0; i
< 6; i
++) {
579 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
580 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
581 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
582 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
583 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
586 emit_cache_flush(ring
);