1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd3_emit_constant(struct fd_ringbuffer
*ring
,
52 enum adreno_state_block sb
,
53 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
54 const uint32_t *dwords
, struct pipe_resource
*prsc
)
57 enum adreno_state_src src
;
67 /* we have this sometimes, not others.. perhaps we could be clever
68 * and figure out actually when we need to invalidate cache:
70 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
, 2);
71 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
72 OUT_RING(ring
, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
73 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE
) |
74 A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 emit_constants(struct fd_ringbuffer
*ring
,
97 enum adreno_state_block sb
,
98 struct fd_constbuf_stateobj
*constbuf
,
99 struct fd3_shader_stateobj
*shader
)
101 uint32_t enabled_mask
= constbuf
->enabled_mask
;
105 // XXX TODO only emit dirty consts.. but we need to keep track if
106 // they are clobbered by a clear, gmem2mem, or mem2gmem..
107 constbuf
->dirty_mask
= enabled_mask
;
109 /* emit user constants: */
110 while (enabled_mask
) {
111 unsigned index
= ffs(enabled_mask
) - 1;
112 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
113 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
115 // I expect that size should be a multiple of vec4's:
116 assert(size
== align(size
, 4));
118 /* gallium could have const-buffer still bound, even though the
119 * shader is not using it. Writing consts above constlen (or
120 * rather, HLSQ_{VS,FS}_CONTROL_REG.CONSTLENGTH) will cause a
123 if ((base
/ 4) >= shader
->constlen
)
126 if (constbuf
->dirty_mask
& (1 << index
)) {
127 fd3_emit_constant(ring
, sb
, base
,
128 cb
->buffer_offset
, size
,
129 cb
->user_buffer
, cb
->buffer
);
130 constbuf
->dirty_mask
&= ~(1 << index
);
134 enabled_mask
&= ~(1 << index
);
137 /* emit shader immediates: */
139 for (i
= 0; i
< shader
->immediates_count
; i
++) {
140 fd3_emit_constant(ring
, sb
,
141 4 * (shader
->first_immediate
+ i
),
142 0, 4, shader
->immediates
[i
].val
, NULL
);
147 #define VERT_TEX_OFF 0
148 #define FRAG_TEX_OFF 16
149 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
152 emit_textures(struct fd_ringbuffer
*ring
,
153 enum adreno_state_block sb
,
154 struct fd_texture_stateobj
*tex
)
156 static const unsigned tex_off
[] = {
157 [SB_VERT_TEX
] = VERT_TEX_OFF
,
158 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
160 static const enum adreno_state_block mipaddr
[] = {
161 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
162 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
166 assert(tex
->num_samplers
== tex
->num_textures
); // TODO check..
168 if (!tex
->num_samplers
)
171 /* output sampler state: */
172 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
173 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
174 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
175 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
176 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
177 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
178 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
179 for (i
= 0; i
< tex
->num_samplers
; i
++) {
180 struct fd3_sampler_stateobj
*sampler
=
181 fd3_sampler_stateobj(tex
->samplers
[i
]);
182 OUT_RING(ring
, sampler
->texsamp0
);
183 OUT_RING(ring
, sampler
->texsamp1
);
186 /* emit texture state: */
187 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
188 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
189 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
190 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
191 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
192 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
193 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
194 for (i
= 0; i
< tex
->num_textures
; i
++) {
195 struct fd3_pipe_sampler_view
*view
=
196 fd3_pipe_sampler_view(tex
->textures
[i
]);
197 OUT_RING(ring
, view
->texconst0
);
198 OUT_RING(ring
, view
->texconst1
);
199 OUT_RING(ring
, view
->texconst2
|
200 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
201 OUT_RING(ring
, view
->texconst3
);
205 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
206 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
207 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
208 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
209 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
210 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
211 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
212 for (i
= 0; i
< tex
->num_textures
; i
++) {
213 struct fd3_pipe_sampler_view
*view
=
214 fd3_pipe_sampler_view(tex
->textures
[i
]);
215 struct fd_resource
*rsc
= view
->tex_resource
;
217 for (j
= 0; j
< view
->mipaddrs
; j
++) {
218 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, j
);
219 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
222 /* pad the remaining entries w/ null: */
223 for (; j
< BASETABLE_SZ
; j
++) {
224 OUT_RING(ring
, 0x00000000);
230 emit_cache_flush(struct fd_ringbuffer
*ring
)
232 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
233 OUT_RING(ring
, CACHE_FLUSH
);
235 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
236 OUT_RING(ring
, 0x00000000);
237 OUT_RING(ring
, DRAW(DI_PT_POINTLIST
, DI_SRC_SEL_AUTO_INDEX
,
238 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
239 OUT_RING(ring
, 0); /* NumIndices */
241 OUT_PKT3(ring
, CP_NOP
, 4);
242 OUT_RING(ring
, 0x00000000);
243 OUT_RING(ring
, 0x00000000);
244 OUT_RING(ring
, 0x00000000);
245 OUT_RING(ring
, 0x00000000);
250 /* emit texture state for mem->gmem restore operation.. eventually it would
251 * be good to get rid of this and use normal CSO/etc state for more of these
252 * special cases, but for now the compiler is not sufficient..
255 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, struct pipe_surface
*psurf
)
257 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
258 enum pipe_format format
= fd3_gmem_restore_format(psurf
->format
);
260 /* output sampler state: */
261 OUT_PKT3(ring
, CP_LOAD_STATE
, 4);
262 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
263 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
264 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
265 CP_LOAD_STATE_0_NUM_UNIT(1));
266 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
267 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
268 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
269 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
270 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
271 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
272 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
273 OUT_RING(ring
, 0x00000000);
275 /* emit texture state: */
276 OUT_PKT3(ring
, CP_LOAD_STATE
, 6);
277 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
278 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
279 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
280 CP_LOAD_STATE_0_NUM_UNIT(1));
281 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
282 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
283 OUT_RING(ring
, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf
->format
)) |
284 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
285 fd3_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
286 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
287 OUT_RING(ring
, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE
) |
288 A3XX_TEX_CONST_1_WIDTH(psurf
->width
) |
289 A3XX_TEX_CONST_1_HEIGHT(psurf
->height
));
290 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(rsc
->slices
[0].pitch
* rsc
->cpp
) |
291 A3XX_TEX_CONST_2_INDX(0));
292 OUT_RING(ring
, 0x00000000);
295 OUT_PKT3(ring
, CP_LOAD_STATE
, 3);
296 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
297 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
298 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
299 CP_LOAD_STATE_0_NUM_UNIT(1));
300 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
301 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
302 OUT_RELOC(ring
, rsc
->bo
, 0, 0, 0);
306 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
,
307 struct fd_program_stateobj
*prog
,
308 struct fd3_vertex_buf
*vbufs
, uint32_t n
)
310 struct fd3_shader_stateobj
*vp
= prog
->vp
;
313 n
= MIN2(n
, vp
->inputs_count
);
315 for (i
= 0; i
< n
; i
++) {
316 struct pipe_resource
*prsc
= vbufs
[i
].prsc
;
317 struct fd_resource
*rsc
= fd_resource(prsc
);
318 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(vbufs
[i
].format
);
319 bool switchnext
= (i
!= (n
- 1));
320 uint32_t fs
= util_format_get_blocksize(vbufs
[i
].format
);
322 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(i
), 2);
323 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
324 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs
[i
].stride
) |
325 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
326 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i
) |
327 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
328 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 0, 0);
330 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(i
), 1);
331 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
332 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
333 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
334 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
335 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
336 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
337 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
342 fd3_emit_state(struct fd_context
*ctx
, uint32_t dirty
)
344 struct fd_ringbuffer
*ring
= ctx
->ring
;
346 emit_marker(ring
, 5);
348 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
349 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
350 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
351 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
352 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
355 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
356 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
357 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
359 fd3_emit_rbrc_draw_state(ring
, zsa
->rb_render_control
);
361 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
362 OUT_RING(ring
, zsa
->rb_alpha_ref
);
364 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
365 OUT_RING(ring
, zsa
->rb_depth_control
);
367 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
368 OUT_RING(ring
, zsa
->rb_stencil_control
);
370 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
371 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
372 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
373 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
374 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
377 if (dirty
& FD_DIRTY_RASTERIZER
) {
378 struct fd3_rasterizer_stateobj
*rasterizer
=
379 fd3_rasterizer_stateobj(ctx
->rasterizer
);
381 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
382 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
384 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
385 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
386 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
388 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
389 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
390 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
392 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
393 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
396 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
397 struct fd3_rasterizer_stateobj
*rasterizer
=
398 fd3_rasterizer_stateobj(ctx
->rasterizer
);
399 struct fd3_shader_stateobj
*fp
= ctx
->prog
.fp
;
400 uint32_t stride_in_vpc
;
402 stride_in_vpc
= align(fp
->total_in
, 4) / 4;
403 if (stride_in_vpc
> 0)
404 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
406 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
407 OUT_RING(ring
, rasterizer
->pc_prim_vtx_cntl
|
408 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
));
411 if (dirty
& FD_DIRTY_SCISSOR
) {
412 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
414 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
415 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
416 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
417 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
418 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
420 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
421 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
422 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
423 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
426 if (dirty
& FD_DIRTY_VIEWPORT
) {
427 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
428 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
429 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
430 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
431 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
432 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
433 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
436 if (dirty
& FD_DIRTY_PROG
)
437 fd3_program_emit(ring
, &ctx
->prog
);
439 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
440 struct fd_program_stateobj
*prog
= &ctx
->prog
;
442 emit_constants(ring
, SB_VERT_SHADER
,
443 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
444 (prog
->dirty
& FD_SHADER_DIRTY_VP
) ? prog
->vp
: NULL
);
445 emit_constants(ring
, SB_FRAG_SHADER
,
446 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
447 (prog
->dirty
& FD_SHADER_DIRTY_FP
) ? prog
->fp
: NULL
);
450 if (dirty
& FD_DIRTY_BLEND
) {
451 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
454 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
455 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
456 OUT_RING(ring
, blend
->rb_mrt
[i
].control
);
458 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
459 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
463 if (dirty
& FD_DIRTY_VERTTEX
)
464 emit_textures(ring
, SB_VERT_TEX
, &ctx
->verttex
);
466 if (dirty
& FD_DIRTY_FRAGTEX
)
467 emit_textures(ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
469 ctx
->dirty
&= ~dirty
;
472 /* emit setup at begin of new cmdstream buffer (don't rely on previous
473 * state, there could have been a context switch between ioctls):
476 fd3_emit_restore(struct fd_context
*ctx
)
478 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
479 struct fd_ringbuffer
*ring
= ctx
->ring
;
482 OUT_PKT3(ring
, CP_REG_RMW
, 3);
483 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
484 OUT_RING(ring
, 0xfffcffff);
485 OUT_RING(ring
, 0x00000000);
487 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
488 OUT_RING(ring
, 0x00007fff);
490 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG
, 3);
491 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
492 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
493 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
495 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG
, 3);
496 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
497 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
498 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
500 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
501 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
503 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
504 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
505 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
506 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
508 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
509 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
510 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
511 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
512 OUT_RING(ring
, 0x00000000); /* UNKNOWN_20C3 */
514 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
515 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
516 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
518 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C81
, 1);
519 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C81 */
521 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
522 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
523 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
524 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
526 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
527 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
528 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
529 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
531 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
532 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
533 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
535 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
536 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
538 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
539 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
541 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
542 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
544 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
545 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
547 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
548 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
550 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
551 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
552 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
553 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
554 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
556 OUT_PKT0(ring
, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG
, 1);
557 OUT_RING(ring
, 0x00000001); /* UCHE_CACHE_MODE_CONTROL_REG */
559 OUT_PKT0(ring
, REG_A3XX_VSC_SIZE_ADDRESS
, 1);
560 OUT_RELOC(ring
, fd3_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
562 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
563 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
565 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
566 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
567 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
569 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
570 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
572 OUT_PKT0(ring
, REG_A3XX_PA_SC_WINDOW_OFFSET
, 1);
573 OUT_RING(ring
, A3XX_PA_SC_WINDOW_OFFSET_X(0) |
574 A3XX_PA_SC_WINDOW_OFFSET_Y(0));
576 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
577 OUT_RING(ring
, 0x00000000); /* RB_BLEND_RED */
578 OUT_RING(ring
, 0x00000000); /* RB_BLEND_GREEN */
579 OUT_RING(ring
, 0x00000000); /* RB_BLEND_BLUE */
580 OUT_RING(ring
, 0x3c0000ff); /* RB_BLEND_ALPHA */
582 for (i
= 0; i
< 6; i
++) {
583 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
584 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
585 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
586 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
587 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
590 emit_cache_flush(ring
);