src/gallium/drivers/freedreno/a3xx/fd3_emit.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_helpers.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_resource.h"
  36
  37 #include "fd3_emit.h"
  38 #include "fd3_blend.h"
  39 #include "fd3_context.h"
  40 #include "fd3_program.h"
  41 #include "fd3_rasterizer.h"
  42 #include "fd3_texture.h"
  43 #include "fd3_util.h"
  44 #include "fd3_zsa.h"
  45
  46 /* regid:          base const register
  47  * prsc or dwords: buffer containing constant values
  48  * sizedwords:     size of const value buffer
  49  */
  50 void
  51 fd3_emit_constant(struct fd_ringbuffer *ring,
  52                 enum adreno_state_block sb,
  53                 uint32_t regid, uint32_t offset, uint32_t sizedwords,
  54                 const uint32_t *dwords, struct pipe_resource *prsc)
  55 {
  56         uint32_t i, sz;
  57         enum adreno_state_src src;
  58
  59         if (prsc) {
  60                 sz = 0;
  61                 src = SS_INDIRECT;
  62         } else {
  63                 sz = sizedwords;
  64                 src = SS_DIRECT;
  65         }
  66
  67         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
  68         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
  69                         CP_LOAD_STATE_0_STATE_SRC(src) |
  70                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
  71                         CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
  72         if (prsc) {
  73                 struct fd_bo *bo = fd_resource(prsc)->bo;
  74                 OUT_RELOC(ring, bo, offset,
  75                                 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
  76         } else {
  77                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
  78                                 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
  79                 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
  80         }
  81         for (i = 0; i < sz; i++) {
  82                 OUT_RING(ring, dwords[i]);
  83         }
  84 }
  85
  86 static void
  87 emit_constants(struct fd_ringbuffer *ring,
  88                 enum adreno_state_block sb,
  89                 struct fd_constbuf_stateobj *constbuf,
  90                 struct fd3_shader_stateobj *shader)
  91 {
  92         uint32_t enabled_mask = constbuf->enabled_mask;
  93         uint32_t base = 0;
  94         unsigned i;
  95
  96         // XXX TODO only emit dirty consts.. but we need to keep track if
  97         // they are clobbered by a clear, gmem2mem, or mem2gmem..
  98         constbuf->dirty_mask = enabled_mask;
  99
 100         /* emit user constants: */
 101         while (enabled_mask) {
 102                 unsigned index = ffs(enabled_mask) - 1;
 103                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
 104                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 105
 106                 // I expect that size should be a multiple of vec4's:
 107                 assert(size == align(size, 4));
 108
 109                 /* gallium could leave const buffers bound above what the
 110                  * current shader uses.. don't let that confuse us.
 111                  */
 112                 if (base >= (4 * shader->first_immediate))
 113                         break;
 114
 115                 if (constbuf->dirty_mask & (1 << index)) {
 116                         fd3_emit_constant(ring, sb, base,
 117                                         cb->buffer_offset, size,
 118                                         cb->user_buffer, cb->buffer);
 119                         constbuf->dirty_mask &= ~(1 << index);
 120                 }
 121
 122                 base += size;
 123                 enabled_mask &= ~(1 << index);
 124         }
 125
 126         /* emit shader immediates: */
 127         if (shader) {
 128                 for (i = 0; i < shader->immediates_count; i++) {
 129                         base = 4 * (shader->first_immediate + i);
 130                         if (base >= (4 * shader->constlen))
 131                                 break;
 132                         fd3_emit_constant(ring, sb, base,
 133                                 0, 4, shader->immediates[i].val, NULL);
 134                 }
 135         }
 136 }
 137
 138 #define VERT_TEX_OFF    0
 139 #define FRAG_TEX_OFF    16
 140 #define BASETABLE_SZ    A3XX_MAX_MIP_LEVELS
 141
 142 static void
 143 emit_textures(struct fd_ringbuffer *ring,
 144                 enum adreno_state_block sb,
 145                 struct fd_texture_stateobj *tex)
 146 {
 147         static const unsigned tex_off[] = {
 148                         [SB_VERT_TEX] = VERT_TEX_OFF,
 149                         [SB_FRAG_TEX] = FRAG_TEX_OFF,
 150         };
 151         static const enum adreno_state_block mipaddr[] = {
 152                         [SB_VERT_TEX] = SB_VERT_MIPADDR,
 153                         [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
 154         };
 155         unsigned i, j;
 156
 157         if (tex->num_samplers > 0) {
 158                 /* output sampler state: */
 159                 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
 160                 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
 161                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 162                                 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 163                                 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
 164                 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
 165                                 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 166                 for (i = 0; i < tex->num_samplers; i++) {
 167                         struct fd3_sampler_stateobj *sampler =
 168                                         fd3_sampler_stateobj(tex->samplers[i]);
 169                         OUT_RING(ring, sampler->texsamp0);
 170                         OUT_RING(ring, sampler->texsamp1);
 171                 }
 172         }
 173
 174         if (tex->num_textures > 0) {
 175                 /* emit texture state: */
 176                 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
 177                 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
 178                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 179                                 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 180                                 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
 181                 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 182                                 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 183                 for (i = 0; i < tex->num_textures; i++) {
 184                         struct fd3_pipe_sampler_view *view =
 185                                         fd3_pipe_sampler_view(tex->textures[i]);
 186                         OUT_RING(ring, view->texconst0);
 187                         OUT_RING(ring, view->texconst1);
 188                         OUT_RING(ring, view->texconst2 |
 189                                         A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
 190                         OUT_RING(ring, view->texconst3);
 191                 }
 192
 193                 /* emit mipaddrs: */
 194                 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
 195                 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
 196                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 197                                 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
 198                                 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
 199                 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 200                                 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 201                 for (i = 0; i < tex->num_textures; i++) {
 202                         struct fd3_pipe_sampler_view *view =
 203                                         fd3_pipe_sampler_view(tex->textures[i]);
 204                         struct fd_resource *rsc = view->tex_resource;
 205
 206                         for (j = 0; j < view->mipaddrs; j++) {
 207                                 struct fd_resource_slice *slice = fd_resource_slice(rsc, j);
 208                                 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
 209                         }
 210
 211                         /* pad the remaining entries w/ null: */
 212                         for (; j < BASETABLE_SZ; j++) {
 213                                 OUT_RING(ring, 0x00000000);
 214                         }
 215                 }
 216         }
 217 }
 218
 219 static void
 220 emit_cache_flush(struct fd_ringbuffer *ring)
 221 {
 222         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 223         OUT_RING(ring, CACHE_FLUSH);
 224
 225         /* probably only really needed on a320: */
 226         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 227         OUT_RING(ring, 0x00000000);
 228         OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
 229                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 230         OUT_RING(ring, 0);                                      /* NumIndices */
 231
 232         OUT_PKT3(ring, CP_NOP, 4);
 233         OUT_RING(ring, 0x00000000);
 234         OUT_RING(ring, 0x00000000);
 235         OUT_RING(ring, 0x00000000);
 236         OUT_RING(ring, 0x00000000);
 237 }
 238
 239 /* emit texture state for mem->gmem restore operation.. eventually it would
 240  * be good to get rid of this and use normal CSO/etc state for more of these
 241  * special cases, but for now the compiler is not sufficient..
 242  */
 243 void
 244 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
 245 {
 246         struct fd_resource *rsc = fd_resource(psurf->texture);
 247         enum pipe_format format = fd3_gmem_restore_format(psurf->format);
 248
 249         /* output sampler state: */
 250         OUT_PKT3(ring, CP_LOAD_STATE, 4);
 251         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
 252                         CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 253                         CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
 254                         CP_LOAD_STATE_0_NUM_UNIT(1));
 255         OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
 256                         CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 257         OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
 258                         A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
 259                         A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
 260                         A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
 261                         A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
 262         OUT_RING(ring, 0x00000000);
 263
 264         /* emit texture state: */
 265         OUT_PKT3(ring, CP_LOAD_STATE, 6);
 266         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
 267                         CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 268                         CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
 269                         CP_LOAD_STATE_0_NUM_UNIT(1));
 270         OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 271                         CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 272         OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) |
 273                         A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
 274                         fd3_tex_swiz(format,  PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
 275                                         PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
 276         OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
 277                         A3XX_TEX_CONST_1_WIDTH(psurf->width) |
 278                         A3XX_TEX_CONST_1_HEIGHT(psurf->height));
 279         OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->slices[0].pitch * rsc->cpp) |
 280                         A3XX_TEX_CONST_2_INDX(0));
 281         OUT_RING(ring, 0x00000000);
 282
 283         /* emit mipaddrs: */
 284         OUT_PKT3(ring, CP_LOAD_STATE, 3);
 285         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
 286                         CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 287                         CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
 288                         CP_LOAD_STATE_0_NUM_UNIT(1));
 289         OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 290                         CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 291         OUT_RELOC(ring, rsc->bo, 0, 0, 0);
 292 }
 293
 294 void
 295 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 296                 struct fd_program_stateobj *prog,
 297                 struct fd3_vertex_buf *vbufs, uint32_t n)
 298 {
 299         struct fd3_shader_stateobj *vp = prog->vp;
 300         uint32_t i;
 301
 302         n = MIN2(n, vp->inputs_count);
 303
 304         for (i = 0; i < n; i++) {
 305                 struct pipe_resource *prsc = vbufs[i].prsc;
 306                 struct fd_resource *rsc = fd_resource(prsc);
 307                 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(vbufs[i].format);
 308                 bool switchnext = (i != (n - 1));
 309                 uint32_t fs = util_format_get_blocksize(vbufs[i].format);
 310
 311                 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(i), 2);
 312                 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
 313                                 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) |
 314                                 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
 315                                 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) |
 316                                 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
 317                 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0);
 318
 319                 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1);
 320                 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
 321                                 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
 322                                 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
 323                                 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
 324                                 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
 325                                 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
 326                                 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
 327         }
 328 }
 329
 330 void
 331 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 332                 struct fd_program_stateobj *prog, uint32_t dirty, bool binning)
 333 {
 334         emit_marker(ring, 5);
 335
 336         if (dirty & FD_DIRTY_SAMPLE_MASK) {
 337                 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
 338                 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 339                                 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 340                                 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
 341         }
 342
 343         if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
 344                 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
 345                 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
 346
 347                 if (!binning) {
 348                         struct fd3_context *fd3_ctx = fd3_context(ctx);
 349
 350                         /* I suppose if we needed to (which I don't *think* we need
 351                          * to), we could emit this for binning pass too.  But we
 352                          * would need to keep a different patch-list for binning
 353                          * vs render pass.
 354                          */
 355
 356                         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 357                         OUT_RINGP(ring, zsa->rb_render_control,
 358                                         &fd3_ctx->rbrc_patches);
 359                 }
 360
 361                 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
 362                 OUT_RING(ring, zsa->rb_alpha_ref);
 363
 364                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 365                 OUT_RING(ring, zsa->rb_stencil_control);
 366
 367                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 368                 OUT_RING(ring, zsa->rb_stencilrefmask |
 369                                 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
 370                 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
 371                                 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
 372         }
 373
 374         if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
 375                 struct fd3_shader_stateobj *fp = prog->fp;
 376                 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
 377                 if (fp->writes_pos) {
 378                         val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
 379                         val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 380                 }
 381                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 382                 OUT_RING(ring, val);
 383         }
 384
 385         if (dirty & FD_DIRTY_RASTERIZER) {
 386                 struct fd3_rasterizer_stateobj *rasterizer =
 387                                 fd3_rasterizer_stateobj(ctx->rasterizer);
 388
 389                 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 390                 OUT_RING(ring, rasterizer->gras_su_mode_control);
 391
 392                 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
 393                 OUT_RING(ring, rasterizer->gras_su_point_minmax);
 394                 OUT_RING(ring, rasterizer->gras_su_point_size);
 395
 396                 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
 397                 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
 398                 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
 399         }
 400
 401         if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
 402                 struct fd3_shader_stateobj *fp = prog->fp;
 403                 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
 404                                 ->gras_cl_clip_cntl;
 405                 if (fp->writes_pos) {
 406                         val |= A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE;
 407                 }
 408                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 409                 OUT_RING(ring, val);
 410         }
 411
 412         if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
 413                 struct fd3_rasterizer_stateobj *rasterizer =
 414                                 fd3_rasterizer_stateobj(ctx->rasterizer);
 415                 struct fd3_shader_stateobj *fp = prog->fp;
 416                 uint32_t stride_in_vpc;
 417
 418                 stride_in_vpc = align(fp->total_in, 4) / 4;
 419                 if (stride_in_vpc > 0)
 420                         stride_in_vpc = MAX2(stride_in_vpc, 2);
 421
 422                 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 423                 OUT_RING(ring, rasterizer->pc_prim_vtx_cntl |
 424                                 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc));
 425         }
 426
 427         if (dirty & FD_DIRTY_SCISSOR) {
 428                 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 429
 430                 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 431                 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
 432                                 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
 433                 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
 434                                 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
 435
 436                 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
 437                 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
 438                 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
 439                 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
 440         }
 441
 442         if (dirty & FD_DIRTY_VIEWPORT) {
 443                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 444                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
 445                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
 446                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
 447                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
 448                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
 449                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
 450         }
 451
 452         if (dirty & FD_DIRTY_PROG) {
 453                 fd_wfi(ctx, ring);
 454                 fd3_program_emit(ring, prog, binning);
 455         }
 456
 457         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 458         OUT_RING(ring, HLSQ_FLUSH);
 459
 460         if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
 461                         /* evil hack to deal sanely with clear path: */
 462                         (prog == &ctx->prog)) {
 463                 fd_wfi(ctx, ring);
 464                 emit_constants(ring,  SB_VERT_SHADER,
 465                                 &ctx->constbuf[PIPE_SHADER_VERTEX],
 466                                 (prog->dirty & FD_SHADER_DIRTY_VP) ? prog->vp : NULL);
 467                 emit_constants(ring, SB_FRAG_SHADER,
 468                                 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
 469                                 (prog->dirty & FD_SHADER_DIRTY_FP) ? prog->fp : NULL);
 470         }
 471
 472         if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
 473                 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
 474                 uint32_t i;
 475
 476                 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
 477                         OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 478                         OUT_RING(ring, blend->rb_mrt[i].control);
 479
 480                         OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 481                         OUT_RING(ring, blend->rb_mrt[i].blend_control);
 482                 }
 483         }
 484
 485         if (dirty & FD_DIRTY_BLEND_COLOR) {
 486                 struct pipe_blend_color *bcolor = &ctx->blend_color;
 487                 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
 488                 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
 489                                 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
 490                 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
 491                                 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
 492                 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
 493                                 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
 494                 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
 495                                 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
 496         }
 497
 498         if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
 499                 fd_wfi(ctx, ring);
 500
 501         if (dirty & FD_DIRTY_VERTTEX)
 502                 emit_textures(ring, SB_VERT_TEX, &ctx->verttex);
 503
 504         if (dirty & FD_DIRTY_FRAGTEX)
 505                 emit_textures(ring, SB_FRAG_TEX, &ctx->fragtex);
 506
 507         ctx->dirty &= ~dirty;
 508 }
 509
 510 /* emit setup at begin of new cmdstream buffer (don't rely on previous
 511  * state, there could have been a context switch between ioctls):
 512  */
 513 void
 514 fd3_emit_restore(struct fd_context *ctx)
 515 {
 516         struct fd3_context *fd3_ctx = fd3_context(ctx);
 517         struct fd_ringbuffer *ring = ctx->ring;
 518         int i;
 519
 520         if (ctx->screen->gpu_id == 320) {
 521                 OUT_PKT3(ring, CP_REG_RMW, 3);
 522                 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
 523                 OUT_RING(ring, 0xfffcffff);
 524                 OUT_RING(ring, 0x00000000);
 525         }
 526
 527         OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 528         OUT_RING(ring, 0x00007fff);
 529
 530         OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
 531         OUT_RING(ring, 0x08000001);                  /* SP_VS_PVT_MEM_CTRL_REG */
 532         OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
 533         OUT_RING(ring, 0x00000000);                  /* SP_VS_PVT_MEM_SIZE_REG */
 534
 535         OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
 536         OUT_RING(ring, 0x08000001);                  /* SP_FS_PVT_MEM_CTRL_REG */
 537         OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
 538         OUT_RING(ring, 0x00000000);                  /* SP_FS_PVT_MEM_SIZE_REG */
 539
 540         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
 541         OUT_RING(ring, 0x0000000b);                  /* PC_VERTEX_REUSE_BLOCK_CNTL */
 542
 543         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 544         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 545                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 546                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 547
 548         OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
 549         OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 550                         A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 551                         A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
 552         OUT_RING(ring, 0x00000000);        /* RB_ALPHA_REF */
 553
 554         OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
 555         OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
 556                         A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
 557
 558         OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
 559         OUT_RING(ring, 0x00000001);        /* GRAS_TSE_DEBUG_ECO */
 560
 561         OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
 562         OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
 563                         A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
 564                         A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
 565
 566         OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
 567         OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
 568                         A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
 569                         A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
 570
 571         OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
 572         OUT_RING(ring, 0x00000000);        /* VPC_VARY_CYLWRAP_ENABLE_0 */
 573         OUT_RING(ring, 0x00000000);        /* VPC_VARY_CYLWRAP_ENABLE_1 */
 574
 575         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
 576         OUT_RING(ring, 0x00000001);        /* UNKNOWN_0E43 */
 577
 578         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
 579         OUT_RING(ring, 0x00000001);        /* UNKNOWN_0F03 */
 580
 581         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
 582         OUT_RING(ring, 0x00000003);        /* UNKNOWN_0EE0 */
 583
 584         OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
 585         OUT_RING(ring, 0x00000001);        /* UNKNOWN_0C3D */
 586
 587         OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
 588         OUT_RING(ring, 0x00000000);        /* HLSQ_PERFCOUNTER0_SELECT */
 589
 590         OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
 591         OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
 592                         A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
 593         OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
 594                         A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
 595
 596         OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
 597         OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
 598         OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
 599                         A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
 600                         A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
 601
 602         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 603         OUT_RING(ring, 0x00000000);                  /* GRAS_CL_CLIP_CNTL */
 604
 605         OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
 606         OUT_RING(ring, 0xffc00010);        /* GRAS_SU_POINT_MINMAX */
 607         OUT_RING(ring, 0x00000008);        /* GRAS_SU_POINT_SIZE */
 608
 609         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 610         OUT_RING(ring, 0xffffffff);        /* PC_RESTART_INDEX */
 611
 612         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 613         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
 614                         A3XX_RB_WINDOW_OFFSET_Y(0));
 615
 616         OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
 617         OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
 618                         A3XX_RB_BLEND_RED_FLOAT(0.0));
 619         OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
 620                         A3XX_RB_BLEND_GREEN_FLOAT(0.0));
 621         OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
 622                         A3XX_RB_BLEND_BLUE_FLOAT(0.0));
 623         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 624                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 625
 626         for (i = 0; i < 6; i++) {
 627                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
 628                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].X */
 629                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].Y */
 630                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].Z */
 631                 OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].W */
 632         }
 633
 634         OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 635         OUT_RING(ring, 0x00000000);
 636
 637         emit_cache_flush(ring);
 638         fd_wfi(ctx, ring);
 639 }