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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd3_gmem.h"
38 #include "fd3_context.h"
39 #include "fd3_emit.h"
40 #include "fd3_program.h"
41 #include "fd3_format.h"
42 #include "fd3_zsa.h"
43
44 static void
45 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
46 struct pipe_surface **bufs, const uint32_t *bases, uint32_t bin_w,
47 bool decode_srgb)
48 {
49 enum a3xx_tile_mode tile_mode;
50 unsigned i;
51
52 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
53 enum pipe_format pformat = 0;
54 enum a3xx_color_fmt format = 0;
55 enum a3xx_color_swap swap = WZYX;
56 bool srgb = false;
57 struct fd_resource *rsc = NULL;
58 uint32_t stride = 0;
59 uint32_t base = 0;
60 uint32_t offset = 0;
61
62 if (bin_w) {
63 tile_mode = TILE_32X32;
64 } else {
65 tile_mode = LINEAR;
66 }
67
68 if ((i < nr_bufs) && bufs[i]) {
69 struct pipe_surface *psurf = bufs[i];
70
71 rsc = fd_resource(psurf->texture);
72 pformat = psurf->format;
73 /* In case we're drawing to Z32F_S8, the "color" actually goes to
74 * the stencil
75 */
76 if (rsc->stencil) {
77 rsc = rsc->stencil;
78 pformat = rsc->base.format;
79 if (bases)
80 bases++;
81 }
82 format = fd3_pipe2color(pformat);
83 if (decode_srgb)
84 srgb = util_format_is_srgb(pformat);
85 else
86 pformat = util_format_linear(pformat);
87
88 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
89
90 offset = fd_resource_offset(rsc, psurf->u.tex.level,
91 psurf->u.tex.first_layer);
92 swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
93
94 if (bin_w) {
95 stride = bin_w << fdl_cpp_shift(&rsc->layout);
96
97 if (bases) {
98 base = bases[i];
99 }
100 } else {
101 stride = fd_resource_pitch(rsc, psurf->u.tex.level);
102 tile_mode = rsc->layout.tile_mode;
103 }
104 } else if (i < nr_bufs && bases) {
105 base = bases[i];
106 }
107
108 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
109 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
110 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
111 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
112 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
113 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
114 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
115 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
116 } else {
117 OUT_RELOC(ring, rsc->bo, offset, 0, -1);
118 }
119
120 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
121 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
122 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
123 fd3_fs_output_format(pformat))));
124 }
125 }
126
127 static bool
128 use_hw_binning(struct fd_batch *batch)
129 {
130 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
131
132 /* workaround: combining scissor optimization and hw binning
133 * seems problematic. Seems like we end up with a mismatch
134 * between binning pass and rendering pass, wrt. where the hw
135 * thinks the vertices belong. And the blob driver doesn't
136 * seem to implement anything like scissor optimization, so
137 * not entirely sure what I might be missing.
138 *
139 * But scissor optimization is mainly for window managers,
140 * which don't have many vertices (and therefore doesn't
141 * benefit much from binning pass).
142 *
143 * So for now just disable binning if scissor optimization is
144 * used.
145 */
146 if (gmem->minx || gmem->miny)
147 return false;
148
149 if ((gmem->maxpw * gmem->maxph) > 32)
150 return false;
151
152 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
153 return false;
154
155 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
156 }
157
158 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
159 static void update_vsc_pipe(struct fd_batch *batch);
160 static void
161 emit_binning_workaround(struct fd_batch *batch)
162 {
163 struct fd_context *ctx = batch->ctx;
164 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
165 struct fd_ringbuffer *ring = batch->gmem;
166 struct fd3_emit emit = {
167 .debug = &ctx->debug,
168 .vtx = &ctx->solid_vbuf_state,
169 .prog = &ctx->solid_prog,
170 };
171
172 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
173 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
174 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
175 A3XX_RB_MODE_CONTROL_MRT(0));
176 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
177 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
178 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
179
180 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
181 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
182 A3XX_RB_COPY_CONTROL_MODE(0) |
183 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
184 OUT_RELOC(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
185 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
186 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
187 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
188 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
189 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
190 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
191
192 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
193 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
194 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
195 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
196
197 fd3_program_emit(ring, &emit, 0, NULL);
198 fd3_emit_vertex_bufs(ring, &emit);
199
200 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
201 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
202 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
203 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
204 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
205 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
206 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
207 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
208 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
209
210 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
211 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
212 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
213
214 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
215 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
216 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
217 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
218
219 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
220 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
221
222 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
223 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
224 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
225 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
226 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
227 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
228 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
229 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
230 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
231
232 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
233 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
234
235 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
236 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
237 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
238 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
239 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
240
241 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
242 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
243 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
244 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
245 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
246
247 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
248 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
249 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
250 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
251 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
252
253 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
254 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
255 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
256 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
257 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
258
259 fd_wfi(batch, ring);
260 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
261 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
262 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
263 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
264 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
265 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
266 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
267
268 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
269 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
270 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
271 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
272 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
273 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
274
275 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
276 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
277 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
278
279 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
280 OUT_RING(ring, 0x00000000); /* viz query info. */
281 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
282 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
283 OUT_RING(ring, 2); /* NumIndices */
284 OUT_RING(ring, 2);
285 OUT_RING(ring, 1);
286 fd_reset_wfi(batch);
287
288 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
289 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
290
291 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
292 OUT_RING(ring, 0x00000000);
293
294 fd_wfi(batch, ring);
295 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
296 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
297 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
298
299 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
300 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
301 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
302 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
303
304 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
305 OUT_RING(ring, 0x00000000);
306 }
307
308 /* transfer from gmem to system memory (ie. normal RAM) */
309
310 static void
311 emit_gmem2mem_surf(struct fd_batch *batch,
312 enum adreno_rb_copy_control_mode mode,
313 bool stencil,
314 uint32_t base, struct pipe_surface *psurf)
315 {
316 struct fd_ringbuffer *ring = batch->gmem;
317 struct fd_resource *rsc = fd_resource(psurf->texture);
318 enum pipe_format format = psurf->format;
319
320 if (!rsc->valid)
321 return;
322
323 if (stencil) {
324 rsc = rsc->stencil;
325 format = rsc->base.format;
326 }
327
328 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
329 psurf->u.tex.first_layer);
330 uint32_t pitch = fd_resource_pitch(rsc, psurf->u.tex.level);
331
332 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
333
334 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
335 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
336 A3XX_RB_COPY_CONTROL_MODE(mode) |
337 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
338 COND(format == PIPE_FORMAT_Z32_FLOAT ||
339 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
340 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
341
342 OUT_RELOC(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
343 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(pitch));
344 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
345 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
346 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
347 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
348 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
349
350 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
351 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
352 }
353
354 static void
355 fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
356 {
357 struct fd_context *ctx = batch->ctx;
358 struct fd_ringbuffer *ring = batch->gmem;
359 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
360 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
361 struct fd3_emit emit = {
362 .debug = &ctx->debug,
363 .vtx = &ctx->solid_vbuf_state,
364 .prog = &ctx->solid_prog,
365 };
366 int i;
367
368 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
369 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
370
371 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
372 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
373 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
374 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
375 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
376 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
377 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
378 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
379 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
380
381 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
382 OUT_RING(ring, 0xff000000 |
383 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
384 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
385 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
386 OUT_RING(ring, 0xff000000 |
387 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
388 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
389 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
390
391 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
392 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
393
394 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
395 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
396
397 fd_wfi(batch, ring);
398 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
399 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
400 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
401 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
402 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
403 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
404 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
405
406 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
407 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
408 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
409 A3XX_RB_MODE_CONTROL_MRT(0));
410
411 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
412 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
413 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
414 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
415 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(batch->gmem_state->bin_w));
416
417 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
418 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
419 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
420 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
421
422 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
423 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
424 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
425 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
426 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
427
428 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
429 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
430 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
431 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
432 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
433
434 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
435 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
436 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
437 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
438 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
439
440 fd3_program_emit(ring, &emit, 0, NULL);
441 fd3_emit_vertex_bufs(ring, &emit);
442
443 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
444 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
445 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
446 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
447 gmem->zsbuf_base[0], pfb->zsbuf);
448 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
449 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
450 gmem->zsbuf_base[1], pfb->zsbuf);
451 }
452
453 if (batch->resolve & FD_BUFFER_COLOR) {
454 for (i = 0; i < pfb->nr_cbufs; i++) {
455 if (!pfb->cbufs[i])
456 continue;
457 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
458 continue;
459 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
460 gmem->cbuf_base[i], pfb->cbufs[i]);
461 }
462 }
463
464 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
465 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
466 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
467 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
468
469 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
470 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
471 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
472 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
473 }
474
475 /* transfer from system memory to gmem */
476
477 static void
478 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
479 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
480 {
481 struct fd_ringbuffer *ring = batch->gmem;
482 struct pipe_surface *zsbufs[2];
483
484 assert(bufs > 0);
485
486 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
487 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
488 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
489 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
490
491 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
492
493 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
494 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
495 /* Depth is stored as unorm in gmem, so we have to write it in using a
496 * special blit shader which writes depth.
497 */
498 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
499 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
500 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
501 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
502 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
503 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
504
505 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
506 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
507 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
508 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->gmem_state->bin_w));
509
510 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
511 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
512 OUT_RING(ring, 0);
513 } else {
514 /* The gmem_restore_tex logic will put the first buffer's stencil
515 * as color. Supply it with the proper information to make that
516 * happen.
517 */
518 zsbufs[0] = zsbufs[1] = psurf[0];
519 psurf = zsbufs;
520 bufs = 2;
521 }
522 } else {
523 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
524 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
525 }
526
527 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
528
529 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
530 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
531 }
532
533 static void
534 fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
535 {
536 struct fd_context *ctx = batch->ctx;
537 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
538 struct fd_ringbuffer *ring = batch->gmem;
539 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
540 struct fd3_emit emit = {
541 .debug = &ctx->debug,
542 .vtx = &ctx->blit_vbuf_state,
543 .sprite_coord_enable = 1,
544 /* NOTE: They all use the same VP, this is for vtx bufs. */
545 .prog = &ctx->blit_prog[0],
546 };
547 float x0, y0, x1, y1;
548 unsigned bin_w = tile->bin_w;
549 unsigned bin_h = tile->bin_h;
550 unsigned i;
551
552 /* write texture coordinates to vertexbuf: */
553 x0 = ((float)tile->xoff) / ((float)pfb->width);
554 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
555 y0 = ((float)tile->yoff) / ((float)pfb->height);
556 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
557
558 OUT_PKT3(ring, CP_MEM_WRITE, 5);
559 OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
560 OUT_RING(ring, fui(x0));
561 OUT_RING(ring, fui(y0));
562 OUT_RING(ring, fui(x1));
563 OUT_RING(ring, fui(y1));
564
565 fd3_emit_cache_flush(batch, ring);
566
567 for (i = 0; i < 4; i++) {
568 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
569 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
570 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
571 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
572
573 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
574 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
575 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
576 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
577 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
578 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
579 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
580 }
581
582 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
583 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
584 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
585
586 fd_wfi(batch, ring);
587 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
588 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
589
590 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
591 OUT_RING(ring, 0);
592 OUT_RING(ring, 0);
593
594 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
595 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
596
597 fd_wfi(batch, ring);
598 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
599 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
600 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
601 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
602 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
603 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
604 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
605
606 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
607 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
608 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
609 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
610 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
611
612 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
613 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
614 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
615 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
616 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
617
618 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
619 OUT_RING(ring, 0x2 |
620 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
621 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
622 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
623 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
624 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
625 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
626 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
627 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
628
629 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
630 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
631 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
632
633 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
634 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
635 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
636 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
637
638 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
639 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
640 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
641 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
642 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
643
644 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
645 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
646 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
647 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
648 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
649
650 fd3_emit_vertex_bufs(ring, &emit);
651
652 /* for gmem pitch/base calculations, we need to use the non-
653 * truncated tile sizes:
654 */
655 bin_w = gmem->bin_w;
656 bin_h = gmem->bin_h;
657
658 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
659 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
660 emit.fs = NULL; /* frag shader changed so clear cache */
661 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
662 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
663 }
664
665 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
666 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
667 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
668 /* Non-float can use a regular color write. It's split over 8-bit
669 * components, so half precision is always sufficient.
670 */
671 emit.prog = &ctx->blit_prog[0];
672 } else {
673 /* Float depth needs special blit shader that writes depth */
674 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
675 emit.prog = &ctx->blit_z;
676 else
677 emit.prog = &ctx->blit_zs;
678 }
679 emit.fs = NULL; /* frag shader changed so clear cache */
680 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
681 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
682 }
683
684 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
685 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
686 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
687 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
688
689 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
690 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
691 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
692 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
693 }
694
695 static void
696 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
697 {
698 unsigned i;
699 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
700 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
701 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
702 }
703 util_dynarray_clear(&batch->draw_patches);
704 }
705
706 static void
707 patch_rbrc(struct fd_batch *batch, uint32_t val)
708 {
709 unsigned i;
710 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
711 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
712 *patch->cs = patch->val | val;
713 }
714 util_dynarray_clear(&batch->rbrc_patches);
715 }
716
717 /* for rendering directly to system memory: */
718 static void
719 fd3_emit_sysmem_prep(struct fd_batch *batch)
720 {
721 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
722 struct fd_ringbuffer *ring = batch->gmem;
723 uint32_t i, pitch = 0;
724
725 for (i = 0; i < pfb->nr_cbufs; i++) {
726 struct pipe_surface *psurf = pfb->cbufs[i];
727 if (!psurf)
728 continue;
729 struct fd_resource *rsc = fd_resource(psurf->texture);
730 pitch = fd_resource_pitch(rsc, psurf->u.tex.level) / rsc->layout.cpp;
731 }
732
733 fd3_emit_restore(batch, ring);
734
735 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
736 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
737 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
738
739 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
740
741 /* setup scissor/offset for current tile: */
742 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
743 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
744 A3XX_RB_WINDOW_OFFSET_Y(0));
745
746 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
747 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
748 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
749 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
750 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
751
752 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
753 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
754 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
755 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
756 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
757
758 patch_draws(batch, IGNORE_VISIBILITY);
759 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
760 }
761
762 static void
763 update_vsc_pipe(struct fd_batch *batch)
764 {
765 struct fd_context *ctx = batch->ctx;
766 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
767 struct fd3_context *fd3_ctx = fd3_context(ctx);
768 struct fd_ringbuffer *ring = batch->gmem;
769 int i;
770
771 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
772 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
773
774 for (i = 0; i < 8; i++) {
775 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
776
777 if (!ctx->vsc_pipe_bo[i]) {
778 ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
779 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
780 }
781
782 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
783 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
784 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
785 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
786 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
787 OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
788 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
789 }
790 }
791
792 static void
793 emit_binning_pass(struct fd_batch *batch)
794 {
795 struct fd_context *ctx = batch->ctx;
796 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
797 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
798 struct fd_ringbuffer *ring = batch->gmem;
799 int i;
800
801 uint32_t x1 = gmem->minx;
802 uint32_t y1 = gmem->miny;
803 uint32_t x2 = gmem->minx + gmem->width - 1;
804 uint32_t y2 = gmem->miny + gmem->height - 1;
805
806 if (ctx->screen->gpu_id == 320) {
807 emit_binning_workaround(batch);
808 fd_wfi(batch, ring);
809 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
810 OUT_RING(ring, 0x00007fff);
811 }
812
813 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
814 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
815
816 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
817 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
818 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
819 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
820
821 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
822 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
823 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
824
825 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
826 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
827 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
828 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
829
830 /* setup scissor/offset for whole screen: */
831 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
832 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
833 A3XX_RB_WINDOW_OFFSET_Y(y1));
834
835 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
836 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
837
838 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
839 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
840 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
841 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
842 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
843
844 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
845 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
846 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
847 A3XX_RB_MODE_CONTROL_MRT(0));
848
849 for (i = 0; i < 4; i++) {
850 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
851 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
852 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
853 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
854 }
855
856 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
857 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
858 A3XX_PC_VSTREAM_CONTROL_N(0));
859
860 /* emit IB to binning drawcmds: */
861 fd3_emit_ib(ring, batch->binning);
862 fd_reset_wfi(batch);
863
864 fd_wfi(batch, ring);
865
866 /* and then put stuff back the way it was: */
867
868 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
869 OUT_RING(ring, 0x00000000);
870
871 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
872 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
873 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
874 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
875 A3XX_SP_SP_CTRL_REG_L0MODE(0));
876
877 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
878 OUT_RING(ring, 0x00000000);
879
880 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
881 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
882 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
883 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
884
885 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
886 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
887 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
888 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
889 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
890 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
891 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
892
893 fd_event_write(batch, ring, CACHE_FLUSH);
894 fd_wfi(batch, ring);
895
896 if (ctx->screen->gpu_id == 320) {
897 /* dummy-draw workaround: */
898 OUT_PKT3(ring, CP_DRAW_INDX, 3);
899 OUT_RING(ring, 0x00000000);
900 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
901 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
902 OUT_RING(ring, 0); /* NumIndices */
903 fd_reset_wfi(batch);
904 }
905
906 OUT_PKT3(ring, CP_NOP, 4);
907 OUT_RING(ring, 0x00000000);
908 OUT_RING(ring, 0x00000000);
909 OUT_RING(ring, 0x00000000);
910 OUT_RING(ring, 0x00000000);
911
912 fd_wfi(batch, ring);
913
914 if (ctx->screen->gpu_id == 320) {
915 emit_binning_workaround(batch);
916 }
917 }
918
919 /* before first tile */
920 static void
921 fd3_emit_tile_init(struct fd_batch *batch)
922 {
923 struct fd_ringbuffer *ring = batch->gmem;
924 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
925 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
926 uint32_t rb_render_control;
927
928 fd3_emit_restore(batch, ring);
929
930 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
931 * at the right and bottom edge tiles
932 */
933 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
934 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
935 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
936
937 update_vsc_pipe(batch);
938
939 fd_wfi(batch, ring);
940 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
941 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
942 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
943
944 if (use_hw_binning(batch)) {
945 /* emit hw binning pass: */
946 emit_binning_pass(batch);
947
948 patch_draws(batch, USE_VISIBILITY);
949 } else {
950 patch_draws(batch, IGNORE_VISIBILITY);
951 }
952
953 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
954 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
955
956 patch_rbrc(batch, rb_render_control);
957 }
958
959 /* before mem2gmem */
960 static void
961 fd3_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
962 {
963 struct fd_ringbuffer *ring = batch->gmem;
964 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
965
966 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
967 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
968 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
969 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
970 }
971
972 /* before IB to rendering cmds: */
973 static void
974 fd3_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
975 {
976 struct fd_context *ctx = batch->ctx;
977 struct fd3_context *fd3_ctx = fd3_context(ctx);
978 struct fd_ringbuffer *ring = batch->gmem;
979 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
980 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
981
982 uint32_t x1 = tile->xoff;
983 uint32_t y1 = tile->yoff;
984 uint32_t x2 = tile->xoff + tile->bin_w - 1;
985 uint32_t y2 = tile->yoff + tile->bin_h - 1;
986
987 uint32_t reg;
988
989 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
990 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
991 if (pfb->zsbuf) {
992 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
993 }
994 OUT_RING(ring, reg);
995 if (pfb->zsbuf) {
996 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
997 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(gmem->bin_w <<
998 fdl_cpp_shift(&rsc->layout)));
999 if (rsc->stencil) {
1000 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1001 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1002 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(gmem->bin_w <<
1003 fdl_cpp_shift(&rsc->stencil->layout)));
1004 }
1005 } else {
1006 OUT_RING(ring, 0x00000000);
1007 }
1008
1009 if (use_hw_binning(batch)) {
1010 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
1011 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
1012
1013 assert(pipe->w && pipe->h);
1014
1015 fd_event_write(batch, ring, HLSQ_FLUSH);
1016 fd_wfi(batch, ring);
1017
1018 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1019 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1020 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1021
1022
1023 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1024 OUT_RELOC(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1025 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1026 (tile->p * 4), 0, 0);
1027 } else {
1028 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1029 OUT_RING(ring, 0x00000000);
1030 }
1031
1032 OUT_PKT3(ring, CP_SET_BIN, 3);
1033 OUT_RING(ring, 0x00000000);
1034 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1035 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1036
1037 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1038
1039 /* setup scissor/offset for current tile: */
1040 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1041 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1042 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1043
1044 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1045 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1046 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1047 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1048 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1049 }
1050
1051 void
1052 fd3_gmem_init(struct pipe_context *pctx)
1053 {
1054 struct fd_context *ctx = fd_context(pctx);
1055
1056 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1057 ctx->emit_tile_init = fd3_emit_tile_init;
1058 ctx->emit_tile_prep = fd3_emit_tile_prep;
1059 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1060 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1061 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1062 }