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freedreno/a3xx: fix hang w/ large render targets and small gmem
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static void
47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
48 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
49 bool decode_srgb)
50 {
51 enum a3xx_tile_mode tile_mode;
52 unsigned i;
53
54 if (bin_w) {
55 tile_mode = TILE_32X32;
56 } else {
57 tile_mode = LINEAR;
58 }
59
60 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
61 enum pipe_format pformat = 0;
62 enum a3xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73
74 rsc = fd_resource(psurf->texture);
75 pformat = psurf->format;
76 /* In case we're drawing to Z32F_S8, the "color" actually goes to
77 * the stencil
78 */
79 if (rsc->stencil) {
80 rsc = rsc->stencil;
81 pformat = rsc->base.b.format;
82 if (bases)
83 bases++;
84 }
85 slice = fd_resource_slice(rsc, psurf->u.tex.level);
86 format = fd3_pipe2color(pformat);
87 swap = fd3_pipe2swap(pformat);
88 if (decode_srgb)
89 srgb = util_format_is_srgb(pformat);
90 else
91 pformat = util_format_linear(pformat);
92
93 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
94
95 offset = fd_resource_offset(rsc, psurf->u.tex.level,
96 psurf->u.tex.first_layer);
97
98 if (bin_w) {
99 stride = bin_w * rsc->cpp;
100
101 if (bases) {
102 base = bases[i];
103 }
104 } else {
105 stride = slice->pitch * rsc->cpp;
106 }
107 } else if (i < nr_bufs && bases) {
108 base = bases[i];
109 }
110
111 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
112 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
115 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
116 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
117 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
118 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
119 } else {
120 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
121 }
122
123 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
124 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
125 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
126 fd3_fs_output_format(pformat))));
127 }
128 }
129
130 static bool
131 use_hw_binning(struct fd_batch *batch)
132 {
133 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
134
135 /* workaround: combining scissor optimization and hw binning
136 * seems problematic. Seems like we end up with a mismatch
137 * between binning pass and rendering pass, wrt. where the hw
138 * thinks the vertices belong. And the blob driver doesn't
139 * seem to implement anything like scissor optimization, so
140 * not entirely sure what I might be missing.
141 *
142 * But scissor optimization is mainly for window managers,
143 * which don't have many vertices (and therefore doesn't
144 * benefit much from binning pass).
145 *
146 * So for now just disable binning if scissor optimization is
147 * used.
148 */
149 if (gmem->minx || gmem->miny)
150 return false;
151
152 if ((gmem->maxpw * gmem->maxph) > 32)
153 return false;
154
155 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
156 }
157
158 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
159 static void update_vsc_pipe(struct fd_batch *batch);
160 static void
161 emit_binning_workaround(struct fd_batch *batch)
162 {
163 struct fd_context *ctx = batch->ctx;
164 struct fd_gmem_stateobj *gmem = &ctx->gmem;
165 struct fd_ringbuffer *ring = batch->gmem;
166 struct fd3_emit emit = {
167 .debug = &ctx->debug,
168 .vtx = &ctx->solid_vbuf_state,
169 .prog = &ctx->solid_prog,
170 .key = {
171 .half_precision = true,
172 },
173 };
174
175 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
176 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
177 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
178 A3XX_RB_MODE_CONTROL_MRT(0));
179 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
180 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
181 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
182
183 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
184 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
185 A3XX_RB_COPY_CONTROL_MODE(0) |
186 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
187 OUT_RELOCW(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
188 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
189 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
190 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
191 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
192 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
193 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
194
195 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
196 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
197 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
198 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
199
200 fd3_program_emit(ring, &emit, 0, NULL);
201 fd3_emit_vertex_bufs(ring, &emit);
202
203 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
204 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
205 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
206 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
207 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
208 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
209 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
210 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
211 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
212
213 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
214 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
215 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
216
217 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
218 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
219 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
220 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
221
222 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
223 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
224
225 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
226 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
227 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
228 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
229 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
230 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
231 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
232 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
233 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
234
235 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
236 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
237
238 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
239 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
240 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
241 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
242 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
243
244 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
245 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
246 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
247 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
248 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
249
250 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
251 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
252 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
253 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
254 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
255
256 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
257 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
258 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
259 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
260 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
261
262 fd_wfi(batch, ring);
263 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
264 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
265 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
266 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
267 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
268 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
269 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
270
271 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
272 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
273 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
274 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
275 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
276 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
277
278 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
279 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
280 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
281
282 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
283 OUT_RING(ring, 0x00000000); /* viz query info. */
284 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
285 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
286 OUT_RING(ring, 2); /* NumIndices */
287 OUT_RING(ring, 2);
288 OUT_RING(ring, 1);
289 fd_reset_wfi(batch);
290
291 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
292 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
293
294 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
295 OUT_RING(ring, 0x00000000);
296
297 fd_wfi(batch, ring);
298 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
299 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
300 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
301
302 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
303 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
304 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
305 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
306
307 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
308 OUT_RING(ring, 0x00000000);
309 }
310
311 /* transfer from gmem to system memory (ie. normal RAM) */
312
313 static void
314 emit_gmem2mem_surf(struct fd_batch *batch,
315 enum adreno_rb_copy_control_mode mode,
316 bool stencil,
317 uint32_t base, struct pipe_surface *psurf)
318 {
319 struct fd_ringbuffer *ring = batch->gmem;
320 struct fd_resource *rsc = fd_resource(psurf->texture);
321 enum pipe_format format = psurf->format;
322 if (stencil) {
323 rsc = rsc->stencil;
324 format = rsc->base.b.format;
325 }
326 struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
327 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
328 psurf->u.tex.first_layer);
329
330 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
331
332 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
333 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
334 A3XX_RB_COPY_CONTROL_MODE(mode) |
335 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
336 COND(format == PIPE_FORMAT_Z32_FLOAT ||
337 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
338 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
339
340 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
341 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
342 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
343 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
344 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
345 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
346 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
347
348 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
349 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
350 }
351
352 static void
353 fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
354 {
355 struct fd_context *ctx = batch->ctx;
356 struct fd_ringbuffer *ring = batch->gmem;
357 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
358 struct fd3_emit emit = {
359 .debug = &ctx->debug,
360 .vtx = &ctx->solid_vbuf_state,
361 .prog = &ctx->solid_prog,
362 .key = {
363 .half_precision = true,
364 },
365 };
366 int i;
367
368 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
369 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
370
371 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
372 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
373 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
374 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
375 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
376 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
377 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
378 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
379 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
380
381 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
382 OUT_RING(ring, 0xff000000 |
383 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
384 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
385 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
386 OUT_RING(ring, 0xff000000 |
387 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
388 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
389 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
390
391 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
392 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
393
394 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
395 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
396
397 fd_wfi(batch, ring);
398 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
399 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
400 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
401 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
402 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
403 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
404 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
405
406 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
407 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
408 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
409 A3XX_RB_MODE_CONTROL_MRT(0));
410
411 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
412 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
413 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
414 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
415 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
416
417 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
418 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
419 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
420 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
421
422 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
423 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
424 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
425 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
426 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
427
428 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
429 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
430 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
431 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
432 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
433
434 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
435 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
436 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
437 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
438 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
439
440 fd3_program_emit(ring, &emit, 0, NULL);
441 fd3_emit_vertex_bufs(ring, &emit);
442
443 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
444 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
445 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
446 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
447 ctx->gmem.zsbuf_base[0], pfb->zsbuf);
448 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
449 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
450 ctx->gmem.zsbuf_base[1], pfb->zsbuf);
451 }
452
453 if (batch->resolve & FD_BUFFER_COLOR) {
454 for (i = 0; i < pfb->nr_cbufs; i++) {
455 if (!pfb->cbufs[i])
456 continue;
457 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
458 continue;
459 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
460 ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
461 }
462 }
463
464 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
465 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
466 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
467 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
468
469 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
470 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
471 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
472 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
473 }
474
475 /* transfer from system memory to gmem */
476
477 static void
478 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
479 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
480 {
481 struct fd_ringbuffer *ring = batch->gmem;
482 struct pipe_surface *zsbufs[2];
483
484 assert(bufs > 0);
485
486 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
487 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
488 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
489 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
490
491 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
492
493 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
494 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
495 /* Depth is stored as unorm in gmem, so we have to write it in using a
496 * special blit shader which writes depth.
497 */
498 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
499 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
500 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
501 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
502 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
503 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
504
505 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
506 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
507 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
508 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->ctx->gmem.bin_w));
509
510 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
511 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
512 OUT_RING(ring, 0);
513 } else {
514 /* The gmem_restore_tex logic will put the first buffer's stencil
515 * as color. Supply it with the proper information to make that
516 * happen.
517 */
518 zsbufs[0] = zsbufs[1] = psurf[0];
519 psurf = zsbufs;
520 bufs = 2;
521 }
522 } else {
523 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
524 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
525 }
526
527 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
528
529 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
530 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
531 }
532
533 static void
534 fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
535 {
536 struct fd_context *ctx = batch->ctx;
537 struct fd_gmem_stateobj *gmem = &ctx->gmem;
538 struct fd_ringbuffer *ring = batch->gmem;
539 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
540 struct fd3_emit emit = {
541 .debug = &ctx->debug,
542 .vtx = &ctx->blit_vbuf_state,
543 .sprite_coord_enable = 1,
544 /* NOTE: They all use the same VP, this is for vtx bufs. */
545 .prog = &ctx->blit_prog[0],
546 .key = {
547 .half_precision = fd_half_precision(pfb),
548 },
549 };
550 float x0, y0, x1, y1;
551 unsigned bin_w = tile->bin_w;
552 unsigned bin_h = tile->bin_h;
553 unsigned i;
554
555 /* write texture coordinates to vertexbuf: */
556 x0 = ((float)tile->xoff) / ((float)pfb->width);
557 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
558 y0 = ((float)tile->yoff) / ((float)pfb->height);
559 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
560
561 OUT_PKT3(ring, CP_MEM_WRITE, 5);
562 OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
563 OUT_RING(ring, fui(x0));
564 OUT_RING(ring, fui(y0));
565 OUT_RING(ring, fui(x1));
566 OUT_RING(ring, fui(y1));
567
568 fd3_emit_cache_flush(batch, ring);
569
570 for (i = 0; i < 4; i++) {
571 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
572 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
573 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
574 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
575
576 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
577 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
578 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
579 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
580 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
581 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
582 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
583 }
584
585 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
586 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
587 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
588
589 fd_wfi(batch, ring);
590 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
591 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
592
593 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
594 OUT_RING(ring, 0);
595 OUT_RING(ring, 0);
596
597 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
598 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
599
600 fd_wfi(batch, ring);
601 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
602 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
603 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
604 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
605 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
606 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
607 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
608
609 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
610 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
611 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
612 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
613 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
614
615 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
616 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
617 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
618 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
619 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
620
621 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
622 OUT_RING(ring, 0x2 |
623 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
624 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
625 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
626 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
627 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
628 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
629 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
630 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
631
632 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
633 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
634 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
635
636 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
637 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
638 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
639 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
640
641 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
642 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
643 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
644 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
645 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
646
647 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
648 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
649 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
650 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
651 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
652
653 fd3_emit_vertex_bufs(ring, &emit);
654
655 /* for gmem pitch/base calculations, we need to use the non-
656 * truncated tile sizes:
657 */
658 bin_w = gmem->bin_w;
659 bin_h = gmem->bin_h;
660
661 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
662 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
663 emit.fp = NULL; /* frag shader changed so clear cache */
664 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
665 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
666 }
667
668 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
669 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
670 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
671 /* Non-float can use a regular color write. It's split over 8-bit
672 * components, so half precision is always sufficient.
673 */
674 emit.prog = &ctx->blit_prog[0];
675 emit.key.half_precision = true;
676 } else {
677 /* Float depth needs special blit shader that writes depth */
678 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
679 emit.prog = &ctx->blit_z;
680 else
681 emit.prog = &ctx->blit_zs;
682 emit.key.half_precision = false;
683 }
684 emit.fp = NULL; /* frag shader changed so clear cache */
685 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
686 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
687 }
688
689 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
690 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
691 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
692 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
693
694 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
695 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
696 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
697 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
698 }
699
700 static void
701 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
702 {
703 unsigned i;
704 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
705 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
706 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
707 }
708 util_dynarray_resize(&batch->draw_patches, 0);
709 }
710
711 static void
712 patch_rbrc(struct fd_batch *batch, uint32_t val)
713 {
714 unsigned i;
715 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
716 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
717 *patch->cs = patch->val | val;
718 }
719 util_dynarray_resize(&batch->rbrc_patches, 0);
720 }
721
722 /* for rendering directly to system memory: */
723 static void
724 fd3_emit_sysmem_prep(struct fd_batch *batch)
725 {
726 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
727 struct fd_ringbuffer *ring = batch->gmem;
728 uint32_t i, pitch = 0;
729
730 for (i = 0; i < pfb->nr_cbufs; i++) {
731 struct pipe_surface *psurf = pfb->cbufs[i];
732 if (!psurf)
733 continue;
734 pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
735 }
736
737 fd3_emit_restore(batch, ring);
738
739 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
740 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
741 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
742
743 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
744
745 /* setup scissor/offset for current tile: */
746 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
747 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
748 A3XX_RB_WINDOW_OFFSET_Y(0));
749
750 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
751 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
752 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
753 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
754 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
755
756 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
757 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
758 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
759 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
760 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
761
762 patch_draws(batch, IGNORE_VISIBILITY);
763 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
764 }
765
766 static void
767 update_vsc_pipe(struct fd_batch *batch)
768 {
769 struct fd_context *ctx = batch->ctx;
770 struct fd3_context *fd3_ctx = fd3_context(ctx);
771 struct fd_ringbuffer *ring = batch->gmem;
772 int i;
773
774 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
775 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
776
777 for (i = 0; i < 8; i++) {
778 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
779
780 if (!pipe->bo) {
781 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
782 DRM_FREEDRENO_GEM_TYPE_KMEM);
783 }
784
785 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
786 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
787 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
788 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
789 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
790 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
791 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
792 }
793 }
794
795 static void
796 emit_binning_pass(struct fd_batch *batch)
797 {
798 struct fd_context *ctx = batch->ctx;
799 struct fd_gmem_stateobj *gmem = &ctx->gmem;
800 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
801 struct fd_ringbuffer *ring = batch->gmem;
802 int i;
803
804 uint32_t x1 = gmem->minx;
805 uint32_t y1 = gmem->miny;
806 uint32_t x2 = gmem->minx + gmem->width - 1;
807 uint32_t y2 = gmem->miny + gmem->height - 1;
808
809 if (ctx->screen->gpu_id == 320) {
810 emit_binning_workaround(batch);
811 fd_wfi(batch, ring);
812 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
813 OUT_RING(ring, 0x00007fff);
814 }
815
816 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
817 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
818
819 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
820 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
821 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
822 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
823
824 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
825 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
826 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
827
828 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
829 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
830 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
831 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
832
833 /* setup scissor/offset for whole screen: */
834 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
835 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
836 A3XX_RB_WINDOW_OFFSET_Y(y1));
837
838 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
839 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
840
841 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
842 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
843 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
844 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
845 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
846
847 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
848 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
849 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
850 A3XX_RB_MODE_CONTROL_MRT(0));
851
852 for (i = 0; i < 4; i++) {
853 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
854 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
855 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
856 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
857 }
858
859 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
860 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
861 A3XX_PC_VSTREAM_CONTROL_N(0));
862
863 /* emit IB to binning drawcmds: */
864 ctx->emit_ib(ring, batch->binning);
865 fd_reset_wfi(batch);
866
867 fd_wfi(batch, ring);
868
869 /* and then put stuff back the way it was: */
870
871 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
872 OUT_RING(ring, 0x00000000);
873
874 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
875 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
876 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
877 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
878 A3XX_SP_SP_CTRL_REG_L0MODE(0));
879
880 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
881 OUT_RING(ring, 0x00000000);
882
883 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
884 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
885 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
886 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
887
888 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
889 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
890 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
891 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
892 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
893 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
894 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
895
896 fd_event_write(batch, ring, CACHE_FLUSH);
897 fd_wfi(batch, ring);
898
899 if (ctx->screen->gpu_id == 320) {
900 /* dummy-draw workaround: */
901 OUT_PKT3(ring, CP_DRAW_INDX, 3);
902 OUT_RING(ring, 0x00000000);
903 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
904 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
905 OUT_RING(ring, 0); /* NumIndices */
906 fd_reset_wfi(batch);
907 }
908
909 OUT_PKT3(ring, CP_NOP, 4);
910 OUT_RING(ring, 0x00000000);
911 OUT_RING(ring, 0x00000000);
912 OUT_RING(ring, 0x00000000);
913 OUT_RING(ring, 0x00000000);
914
915 fd_wfi(batch, ring);
916
917 if (ctx->screen->gpu_id == 320) {
918 emit_binning_workaround(batch);
919 }
920 }
921
922 /* before first tile */
923 static void
924 fd3_emit_tile_init(struct fd_batch *batch)
925 {
926 struct fd_ringbuffer *ring = batch->gmem;
927 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
928 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
929 uint32_t rb_render_control;
930
931 fd3_emit_restore(batch, ring);
932
933 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
934 * at the right and bottom edge tiles
935 */
936 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
937 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
938 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
939
940 update_vsc_pipe(batch);
941
942 fd_wfi(batch, ring);
943 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
944 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
945 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
946
947 if (use_hw_binning(batch)) {
948 /* emit hw binning pass: */
949 emit_binning_pass(batch);
950
951 patch_draws(batch, USE_VISIBILITY);
952 } else {
953 patch_draws(batch, IGNORE_VISIBILITY);
954 }
955
956 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
957 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
958
959 patch_rbrc(batch, rb_render_control);
960 }
961
962 /* before mem2gmem */
963 static void
964 fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
965 {
966 struct fd_ringbuffer *ring = batch->gmem;
967 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
968
969 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
970 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
971 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
972 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
973 }
974
975 /* before IB to rendering cmds: */
976 static void
977 fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
978 {
979 struct fd_context *ctx = batch->ctx;
980 struct fd3_context *fd3_ctx = fd3_context(ctx);
981 struct fd_ringbuffer *ring = batch->gmem;
982 struct fd_gmem_stateobj *gmem = &ctx->gmem;
983 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
984
985 uint32_t x1 = tile->xoff;
986 uint32_t y1 = tile->yoff;
987 uint32_t x2 = tile->xoff + tile->bin_w - 1;
988 uint32_t y2 = tile->yoff + tile->bin_h - 1;
989
990 uint32_t reg;
991
992 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
993 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
994 if (pfb->zsbuf) {
995 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
996 }
997 OUT_RING(ring, reg);
998 if (pfb->zsbuf) {
999 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1000 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
1001 if (rsc->stencil) {
1002 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1003 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1004 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
1005 }
1006 } else {
1007 OUT_RING(ring, 0x00000000);
1008 }
1009
1010 if (use_hw_binning(batch)) {
1011 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
1012
1013 assert(pipe->w * pipe->h);
1014
1015 fd_event_write(batch, ring, HLSQ_FLUSH);
1016 fd_wfi(batch, ring);
1017
1018 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1019 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1020 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1021
1022
1023 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1024 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1025 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1026 (tile->p * 4), 0, 0);
1027 } else {
1028 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1029 OUT_RING(ring, 0x00000000);
1030 }
1031
1032 OUT_PKT3(ring, CP_SET_BIN, 3);
1033 OUT_RING(ring, 0x00000000);
1034 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1035 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1036
1037 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1038
1039 /* setup scissor/offset for current tile: */
1040 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1041 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1042 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1043
1044 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1045 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1046 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1047 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1048 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1049 }
1050
1051 void
1052 fd3_gmem_init(struct pipe_context *pctx)
1053 {
1054 struct fd_context *ctx = fd_context(pctx);
1055
1056 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1057 ctx->emit_tile_init = fd3_emit_tile_init;
1058 ctx->emit_tile_prep = fd3_emit_tile_prep;
1059 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1060 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1061 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1062 }