1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
40 #include "fd3_context.h"
42 #include "fd3_program.h"
46 static const struct ir3_shader_key key
= {
47 // XXX should set this based on render target format! We don't
48 // want half_precision if float32 render target!!!
49 .half_precision
= true,
53 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
54 struct pipe_surface
**bufs
, uint32_t *bases
, uint32_t bin_w
)
56 enum a3xx_tile_mode tile_mode
;
60 tile_mode
= TILE_32X32
;
65 for (i
= 0; i
< 4; i
++) {
66 enum a3xx_color_fmt format
= 0;
67 enum a3xx_color_swap swap
= WZYX
;
68 struct fd_resource
*rsc
= NULL
;
69 struct fd_resource_slice
*slice
= NULL
;
72 uint32_t layer_offset
= 0;
74 if ((i
< nr_bufs
) && bufs
[i
]) {
75 struct pipe_surface
*psurf
= bufs
[i
];
77 rsc
= fd_resource(psurf
->texture
);
78 slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
79 format
= fd3_pipe2color(psurf
->format
);
80 swap
= fd3_pipe2swap(psurf
->format
);
82 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
84 layer_offset
= slice
->size0
* psurf
->u
.tex
.first_layer
;
87 stride
= bin_w
* rsc
->cpp
;
93 stride
= slice
->pitch
* rsc
->cpp
;
97 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BUF_INFO(i
), 2);
98 OUT_RING(ring
, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
99 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
100 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
101 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
));
102 if (bin_w
|| (i
>= nr_bufs
)) {
103 OUT_RING(ring
, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base
));
105 OUT_RELOCW(ring
, rsc
->bo
,
106 slice
->offset
+ layer_offset
, 0, -1);
109 OUT_PKT0(ring
, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i
), 1);
110 OUT_RING(ring
, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format
));
115 depth_base(struct fd_context
*ctx
)
117 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
118 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
121 struct fd_resource
*rsc
=
122 fd_resource(pfb
->cbufs
[0]->texture
);
125 return align(gmem
->bin_w
* gmem
->bin_h
* cpp
, 0x4000);
129 use_hw_binning(struct fd_context
*ctx
)
131 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
133 /* workaround: combining scissor optimization and hw binning
134 * seems problematic. Seems like we end up with a mismatch
135 * between binning pass and rendering pass, wrt. where the hw
136 * thinks the vertices belong. And the blob driver doesn't
137 * seem to implement anything like scissor optimization, so
138 * not entirely sure what I might be missing.
140 * But scissor optimization is mainly for window managers,
141 * which don't have many vertices (and therefore doesn't
142 * benefit much from binning pass).
144 * So for now just disable binning if scissor optimization is
147 if (gmem
->minx
|| gmem
->miny
)
150 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2);
153 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
154 static void update_vsc_pipe(struct fd_context
*ctx
);
156 emit_binning_workaround(struct fd_context
*ctx
)
158 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
159 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
160 struct fd_ringbuffer
*ring
= ctx
->ring
;
162 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 2);
163 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
164 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
165 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
166 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
167 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
));
169 OUT_PKT0(ring
, REG_A3XX_RB_COPY_CONTROL
, 4);
170 OUT_RING(ring
, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
171 A3XX_RB_COPY_CONTROL_MODE(0) |
172 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
173 OUT_RELOCW(ring
, fd_resource(fd3_ctx
->solid_vbuf
)->bo
, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
174 OUT_RING(ring
, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
175 OUT_RING(ring
, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR
) |
176 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM
) |
177 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX
) |
178 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
179 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
));
181 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
182 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
183 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
184 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
186 fd3_program_emit(ring
, &ctx
->solid_prog
, key
, false);
187 fd3_emit_vertex_bufs(ring
, fd3_shader_variant(ctx
->solid_prog
.vp
, key
),
188 &fd3_ctx
->solid_vbuf_state
);
190 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 4);
191 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
192 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
193 A3XX_HLSQ_CONTROL_0_REG_RESERVED2
|
194 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
195 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
196 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
);
197 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
198 OUT_RING(ring
, 0); /* HLSQ_CONTROL_3_REG */
200 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG
, 1);
201 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
202 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
204 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
205 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
206 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
207 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
209 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
210 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
212 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
213 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
214 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
215 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
216 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
217 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
218 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
219 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
220 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
222 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
223 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
225 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
226 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
227 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
228 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
229 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
231 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
232 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
233 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
234 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
235 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
237 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
238 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
239 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
240 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
241 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
243 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
244 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
245 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
246 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
247 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
250 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
251 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
252 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
253 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
254 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
255 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
256 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
258 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
259 OUT_RING(ring
, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE
|
260 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE
|
261 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE
|
262 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE
|
263 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE
);
265 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
266 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
267 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
269 OUT_PKT3(ring
, CP_DRAW_INDX_2
, 5);
270 OUT_RING(ring
, 0x00000000); /* viz query info. */
271 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_IMMEDIATE
,
272 INDEX_SIZE_32_BIT
, IGNORE_VISIBILITY
));
273 OUT_RING(ring
, 2); /* NumIndices */
278 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 1);
279 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS
));
281 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
282 OUT_RING(ring
, 0x00000000);
285 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_SIZE
, 1);
286 OUT_RING(ring
, A3XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
287 A3XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
289 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
290 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
291 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
292 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
294 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
295 OUT_RING(ring
, 0x00000000);
298 /* transfer from gmem to system memory (ie. normal RAM) */
301 emit_gmem2mem_surf(struct fd_context
*ctx
,
302 enum adreno_rb_copy_control_mode mode
,
303 uint32_t base
, struct pipe_surface
*psurf
)
305 struct fd_ringbuffer
*ring
= ctx
->ring
;
306 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
307 struct fd_resource_slice
*slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
308 uint32_t layer_offset
= slice
->size0
* psurf
->u
.tex
.first_layer
;
310 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
312 OUT_PKT0(ring
, REG_A3XX_RB_COPY_CONTROL
, 4);
313 OUT_RING(ring
, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
314 A3XX_RB_COPY_CONTROL_MODE(mode
) |
315 A3XX_RB_COPY_CONTROL_GMEM_BASE(base
));
317 OUT_RELOCW(ring
, rsc
->bo
, slice
->offset
+ layer_offset
, 0, -1); /* RB_COPY_DEST_BASE */
318 OUT_RING(ring
, A3XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->cpp
));
319 OUT_RING(ring
, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR
) |
320 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf
->format
)) |
321 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
322 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
323 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf
->format
)));
325 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
326 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
330 fd3_emit_tile_gmem2mem(struct fd_context
*ctx
, struct fd_tile
*tile
)
332 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
333 struct fd_ringbuffer
*ring
= ctx
->ring
;
334 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
336 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
337 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
339 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
340 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
341 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
342 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
343 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
344 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
345 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
346 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
347 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
349 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
350 OUT_RING(ring
, 0xff000000 |
351 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
352 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
353 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
354 OUT_RING(ring
, 0xff000000 |
355 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
356 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
357 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
359 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
360 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
362 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
363 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
366 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
367 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb
->width
/2.0 - 0.5));
368 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb
->width
/2.0));
369 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb
->height
/2.0 - 0.5));
370 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb
->height
/2.0));
371 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
372 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
374 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
375 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
376 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
378 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
379 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
380 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
381 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
382 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx
->gmem
.bin_w
));
384 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
385 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
386 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
387 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
389 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
390 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
391 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
392 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
393 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
395 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
396 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
397 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
398 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
399 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
401 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
402 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
403 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
404 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
405 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
407 fd3_program_emit(ring
, &ctx
->solid_prog
, key
, false);
408 fd3_emit_vertex_bufs(ring
, fd3_shader_variant(ctx
->solid_prog
.vp
, key
),
409 &fd3_ctx
->solid_vbuf_state
);
411 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
412 uint32_t base
= depth_base(ctx
);
413 emit_gmem2mem_surf(ctx
, RB_COPY_DEPTH_STENCIL
, base
, pfb
->zsbuf
);
416 if (ctx
->resolve
& FD_BUFFER_COLOR
) {
417 emit_gmem2mem_surf(ctx
, RB_COPY_RESOLVE
, 0, pfb
->cbufs
[0]);
420 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
421 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
422 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
424 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
425 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
426 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
427 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
430 /* transfer from system memory to gmem */
433 emit_mem2gmem_surf(struct fd_context
*ctx
, uint32_t base
,
434 struct pipe_surface
*psurf
, uint32_t bin_w
)
436 struct fd_ringbuffer
*ring
= ctx
->ring
;
438 emit_mrt(ring
, 1, &psurf
, &base
, bin_w
);
440 fd3_emit_gmem_restore_tex(ring
, psurf
);
442 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
443 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
447 fd3_emit_tile_mem2gmem(struct fd_context
*ctx
, struct fd_tile
*tile
)
449 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
450 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
451 struct fd_ringbuffer
*ring
= ctx
->ring
;
452 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
453 float x0
, y0
, x1
, y1
;
454 unsigned bin_w
= tile
->bin_w
;
455 unsigned bin_h
= tile
->bin_h
;
458 /* write texture coordinates to vertexbuf: */
459 x0
= ((float)tile
->xoff
) / ((float)pfb
->width
);
460 x1
= ((float)tile
->xoff
+ bin_w
) / ((float)pfb
->width
);
461 y0
= ((float)tile
->yoff
) / ((float)pfb
->height
);
462 y1
= ((float)tile
->yoff
+ bin_h
) / ((float)pfb
->height
);
464 OUT_PKT3(ring
, CP_MEM_WRITE
, 5);
465 OUT_RELOCW(ring
, fd_resource(fd3_ctx
->blit_texcoord_vbuf
)->bo
, 0, 0, 0);
466 OUT_RING(ring
, fui(x0
));
467 OUT_RING(ring
, fui(y0
));
468 OUT_RING(ring
, fui(x1
));
469 OUT_RING(ring
, fui(y1
));
471 for (i
= 0; i
< 4; i
++) {
472 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
473 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
474 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE
) |
475 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
477 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
478 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
479 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
480 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
481 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
482 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
483 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
) |
484 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
);
487 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
488 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
) |
489 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
492 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
493 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS
));
495 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
496 OUT_RING(ring
, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER
); /* GRAS_CL_CLIP_CNTL */
499 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
500 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w
/2.0 - 0.5));
501 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w
/2.0));
502 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h
/2.0 - 0.5));
503 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h
/2.0));
504 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
505 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
507 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
508 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
509 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
510 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w
- 1) |
511 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h
- 1));
513 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
514 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
515 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
516 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w
- 1) |
517 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h
- 1));
519 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
521 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
522 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
523 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
524 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
525 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS
) |
526 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
527 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
528 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
530 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
531 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
532 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
533 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
535 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
536 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
537 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
538 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
539 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
541 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
542 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
543 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
544 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
545 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
547 fd3_program_emit(ring
, &ctx
->blit_prog
, key
, false);
548 fd3_emit_vertex_bufs(ring
, fd3_shader_variant(ctx
->blit_prog
.vp
, key
),
549 &fd3_ctx
->blit_vbuf_state
);
551 /* for gmem pitch/base calculations, we need to use the non-
552 * truncated tile sizes:
557 if (ctx
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
))
558 emit_mem2gmem_surf(ctx
, depth_base(ctx
), pfb
->zsbuf
, bin_w
);
560 if (ctx
->restore
& FD_BUFFER_COLOR
)
561 emit_mem2gmem_surf(ctx
, 0, pfb
->cbufs
[0], bin_w
);
563 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
564 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
565 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
566 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
570 patch_draws(struct fd_context
*ctx
, enum pc_di_vis_cull_mode vismode
)
573 for (i
= 0; i
< fd_patch_num_elements(&ctx
->draw_patches
); i
++) {
574 struct fd_cs_patch
*patch
= fd_patch_element(&ctx
->draw_patches
, i
);
575 *patch
->cs
= patch
->val
| DRAW(0, 0, 0, vismode
);
577 util_dynarray_resize(&ctx
->draw_patches
, 0);
581 patch_rbrc(struct fd_context
*ctx
, uint32_t val
)
583 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
585 for (i
= 0; i
< fd_patch_num_elements(&fd3_ctx
->rbrc_patches
); i
++) {
586 struct fd_cs_patch
*patch
= fd_patch_element(&fd3_ctx
->rbrc_patches
, i
);
587 *patch
->cs
= patch
->val
| val
;
589 util_dynarray_resize(&fd3_ctx
->rbrc_patches
, 0);
592 /* for rendering directly to system memory: */
594 fd3_emit_sysmem_prep(struct fd_context
*ctx
)
596 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
597 struct fd_ringbuffer
*ring
= ctx
->ring
;
601 pitch
= fd_resource(pfb
->cbufs
[0]->texture
)->slices
[0].pitch
;
603 fd3_emit_restore(ctx
);
605 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
606 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
607 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
609 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, 0);
611 /* setup scissor/offset for current tile: */
612 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
613 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
614 A3XX_RB_WINDOW_OFFSET_Y(0));
616 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
617 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
618 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
619 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb
->width
- 1) |
620 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb
->height
- 1));
622 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
623 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
624 A3XX_RB_MODE_CONTROL_GMEM_BYPASS
|
625 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
627 patch_draws(ctx
, IGNORE_VISIBILITY
);
628 patch_rbrc(ctx
, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch
));
632 update_vsc_pipe(struct fd_context
*ctx
)
634 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
635 struct fd_ringbuffer
*ring
= ctx
->ring
;
638 OUT_PKT0(ring
, REG_A3XX_VSC_SIZE_ADDRESS
, 1);
639 OUT_RELOCW(ring
, fd3_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
641 for (i
= 0; i
< 8; i
++) {
642 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
645 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x40000,
646 DRM_FREEDRENO_GEM_TYPE_KMEM
);
649 OUT_PKT0(ring
, REG_A3XX_VSC_PIPE(i
), 3);
650 OUT_RING(ring
, A3XX_VSC_PIPE_CONFIG_X(pipe
->x
) |
651 A3XX_VSC_PIPE_CONFIG_Y(pipe
->y
) |
652 A3XX_VSC_PIPE_CONFIG_W(pipe
->w
) |
653 A3XX_VSC_PIPE_CONFIG_H(pipe
->h
));
654 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
655 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE[i].DATA_LENGTH */
660 emit_binning_pass(struct fd_context
*ctx
)
662 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
663 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
664 struct fd_ringbuffer
*ring
= ctx
->ring
;
667 uint32_t x1
= gmem
->minx
;
668 uint32_t y1
= gmem
->miny
;
669 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
670 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
672 if (ctx
->screen
->gpu_id
== 320) {
673 emit_binning_workaround(ctx
);
675 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
676 OUT_RING(ring
, 0x00007fff);
679 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_CONTROL
, 1);
680 OUT_RING(ring
, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE
);
682 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
683 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
684 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
685 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
687 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
688 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
689 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
691 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
692 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
693 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
694 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
696 /* setup scissor/offset for whole screen: */
697 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
698 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(x1
) |
699 A3XX_RB_WINDOW_OFFSET_Y(y1
));
701 OUT_PKT0(ring
, REG_A3XX_RB_LRZ_VSC_CONTROL
, 1);
702 OUT_RING(ring
, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE
);
704 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
705 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
706 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
707 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
708 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
710 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
711 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
712 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
714 for (i
= 0; i
< 4; i
++) {
715 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
716 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR
) |
717 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE
) |
718 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
721 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
722 OUT_RING(ring
, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
723 A3XX_PC_VSTREAM_CONTROL_N(0));
725 /* emit IB to binning drawcmds: */
726 OUT_IB(ring
, ctx
->binning_start
, ctx
->binning_end
);
731 /* and then put stuff back the way it was: */
733 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_CONTROL
, 1);
734 OUT_RING(ring
, 0x00000000);
736 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
737 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_RESOLVE
|
738 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
739 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
740 A3XX_SP_SP_CTRL_REG_L0MODE(0));
742 OUT_PKT0(ring
, REG_A3XX_RB_LRZ_VSC_CONTROL
, 1);
743 OUT_RING(ring
, 0x00000000);
745 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
746 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
747 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
748 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
750 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 2);
751 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
752 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
753 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
754 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
755 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
757 fd_event_write(ctx
, ring
, CACHE_FLUSH
);
760 if (ctx
->screen
->gpu_id
== 320) {
761 /* dummy-draw workaround: */
762 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
763 OUT_RING(ring
, 0x00000000);
764 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
765 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
766 OUT_RING(ring
, 0); /* NumIndices */
770 OUT_PKT3(ring
, CP_NOP
, 4);
771 OUT_RING(ring
, 0x00000000);
772 OUT_RING(ring
, 0x00000000);
773 OUT_RING(ring
, 0x00000000);
774 OUT_RING(ring
, 0x00000000);
778 if (ctx
->screen
->gpu_id
== 320) {
779 emit_binning_workaround(ctx
);
783 /* before first tile */
785 fd3_emit_tile_init(struct fd_context
*ctx
)
787 struct fd_ringbuffer
*ring
= ctx
->ring
;
788 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
789 uint32_t rb_render_control
;
791 fd3_emit_restore(ctx
);
793 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
794 * at the right and bottom edge tiles
796 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_SIZE
, 1);
797 OUT_RING(ring
, A3XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
798 A3XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
800 update_vsc_pipe(ctx
);
802 if (use_hw_binning(ctx
)) {
803 /* mark the end of the binning cmds: */
804 fd_ringmarker_mark(ctx
->binning_end
);
806 /* emit hw binning pass: */
807 emit_binning_pass(ctx
);
809 patch_draws(ctx
, USE_VISIBILITY
);
811 patch_draws(ctx
, IGNORE_VISIBILITY
);
814 rb_render_control
= A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
815 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
);
817 patch_rbrc(ctx
, rb_render_control
);
820 /* before mem2gmem */
822 fd3_emit_tile_prep(struct fd_context
*ctx
, struct fd_tile
*tile
)
824 struct fd_ringbuffer
*ring
= ctx
->ring
;
825 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
826 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
829 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_INFO
, 2);
830 reg
= A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx
));
832 reg
|= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb
->zsbuf
->format
));
836 uint32_t cpp
= util_format_get_blocksize(pfb
->zsbuf
->format
);
837 OUT_RING(ring
, A3XX_RB_DEPTH_PITCH(cpp
* gmem
->bin_w
));
839 OUT_RING(ring
, 0x00000000);
842 if (ctx
->needs_rb_fbd
) {
844 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
845 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
846 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
847 ctx
->needs_rb_fbd
= false;
850 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
851 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
852 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
855 /* before IB to rendering cmds: */
857 fd3_emit_tile_renderprep(struct fd_context
*ctx
, struct fd_tile
*tile
)
859 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
860 struct fd_ringbuffer
*ring
= ctx
->ring
;
861 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
862 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
864 uint32_t x1
= tile
->xoff
;
865 uint32_t y1
= tile
->yoff
;
866 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
867 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
869 if (use_hw_binning(ctx
)) {
870 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[tile
->p
];
872 assert(pipe
->w
* pipe
->h
);
874 fd_event_write(ctx
, ring
, HLSQ_FLUSH
);
877 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
878 OUT_RING(ring
, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe
->w
* pipe
->h
) |
879 A3XX_PC_VSTREAM_CONTROL_N(tile
->n
));
882 OUT_PKT3(ring
, CP_SET_BIN_DATA
, 2);
883 OUT_RELOC(ring
, pipe
->bo
, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
884 OUT_RELOC(ring
, fd3_ctx
->vsc_size_mem
, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
885 (tile
->p
* 4), 0, 0);
887 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
888 OUT_RING(ring
, 0x00000000);
891 OUT_PKT3(ring
, CP_SET_BIN
, 3);
892 OUT_RING(ring
, 0x00000000);
893 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
894 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
896 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, gmem
->bin_w
);
898 /* setup scissor/offset for current tile: */
899 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
900 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(tile
->xoff
) |
901 A3XX_RB_WINDOW_OFFSET_Y(tile
->yoff
));
903 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
904 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
905 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
906 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
907 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
911 fd3_gmem_init(struct pipe_context
*pctx
)
913 struct fd_context
*ctx
= fd_context(pctx
);
915 ctx
->emit_sysmem_prep
= fd3_emit_sysmem_prep
;
916 ctx
->emit_tile_init
= fd3_emit_tile_init
;
917 ctx
->emit_tile_prep
= fd3_emit_tile_prep
;
918 ctx
->emit_tile_mem2gmem
= fd3_emit_tile_mem2gmem
;
919 ctx
->emit_tile_renderprep
= fd3_emit_tile_renderprep
;
920 ctx
->emit_tile_gmem2mem
= fd3_emit_tile_gmem2mem
;