1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
40 #include "fd3_context.h"
42 #include "fd3_program.h"
43 #include "fd3_format.h"
47 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
48 struct pipe_surface
**bufs
, uint32_t *bases
, uint32_t bin_w
,
51 enum a3xx_tile_mode tile_mode
;
55 tile_mode
= TILE_32X32
;
60 for (i
= 0; i
< A3XX_MAX_RENDER_TARGETS
; i
++) {
61 enum pipe_format pformat
= 0;
62 enum a3xx_color_fmt format
= 0;
63 enum a3xx_color_swap swap
= WZYX
;
65 struct fd_resource
*rsc
= NULL
;
66 struct fd_resource_slice
*slice
= NULL
;
71 if ((i
< nr_bufs
) && bufs
[i
]) {
72 struct pipe_surface
*psurf
= bufs
[i
];
74 rsc
= fd_resource(psurf
->texture
);
75 pformat
= psurf
->format
;
76 /* In case we're drawing to Z32F_S8, the "color" actually goes to
81 pformat
= rsc
->base
.b
.format
;
85 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
86 format
= fd3_pipe2color(pformat
);
87 swap
= fd3_pipe2swap(pformat
);
89 srgb
= util_format_is_srgb(pformat
);
91 pformat
= util_format_linear(pformat
);
93 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
95 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
96 psurf
->u
.tex
.first_layer
);
99 stride
= bin_w
* rsc
->cpp
;
105 stride
= slice
->pitch
* rsc
->cpp
;
107 } else if (i
< nr_bufs
&& bases
) {
111 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BUF_INFO(i
), 2);
112 OUT_RING(ring
, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
115 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
) |
116 COND(srgb
, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB
));
117 if (bin_w
|| (i
>= nr_bufs
) || !bufs
[i
]) {
118 OUT_RING(ring
, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base
));
120 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, -1);
123 OUT_PKT0(ring
, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i
), 1);
124 OUT_RING(ring
, COND((i
< nr_bufs
) && bufs
[i
],
125 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
126 fd3_fs_output_format(pformat
))));
131 use_hw_binning(struct fd_context
*ctx
)
133 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
135 /* workaround: combining scissor optimization and hw binning
136 * seems problematic. Seems like we end up with a mismatch
137 * between binning pass and rendering pass, wrt. where the hw
138 * thinks the vertices belong. And the blob driver doesn't
139 * seem to implement anything like scissor optimization, so
140 * not entirely sure what I might be missing.
142 * But scissor optimization is mainly for window managers,
143 * which don't have many vertices (and therefore doesn't
144 * benefit much from binning pass).
146 * So for now just disable binning if scissor optimization is
149 if (gmem
->minx
|| gmem
->miny
)
152 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2);
155 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
156 static void update_vsc_pipe(struct fd_context
*ctx
);
158 emit_binning_workaround(struct fd_context
*ctx
)
160 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
161 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
162 struct fd_ringbuffer
*ring
= ctx
->ring
;
163 struct fd3_emit emit
= {
164 .debug
= &ctx
->debug
,
165 .vtx
= &fd3_ctx
->solid_vbuf_state
,
166 .prog
= &ctx
->solid_prog
,
168 .half_precision
= true,
172 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 2);
173 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
174 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
175 A3XX_RB_MODE_CONTROL_MRT(0));
176 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
177 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
178 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
));
180 OUT_PKT0(ring
, REG_A3XX_RB_COPY_CONTROL
, 4);
181 OUT_RING(ring
, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
182 A3XX_RB_COPY_CONTROL_MODE(0) |
183 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
184 OUT_RELOCW(ring
, fd_resource(fd3_ctx
->solid_vbuf
)->bo
, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
185 OUT_RING(ring
, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
186 OUT_RING(ring
, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR
) |
187 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM
) |
188 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX
) |
189 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
190 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
));
192 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
193 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
194 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
195 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
197 fd3_program_emit(ring
, &emit
, 0, NULL
);
198 fd3_emit_vertex_bufs(ring
, &emit
);
200 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 4);
201 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
202 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
203 A3XX_HLSQ_CONTROL_0_REG_RESERVED2
|
204 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
205 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
206 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
);
207 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
208 OUT_RING(ring
, 0); /* HLSQ_CONTROL_3_REG */
210 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG
, 1);
211 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
212 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
214 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
215 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
216 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
217 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
219 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
220 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
222 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
223 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
224 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
225 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
226 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
227 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
228 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
229 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
230 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
232 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
233 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
235 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
236 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
237 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
238 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
239 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
241 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
242 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
243 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
244 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
245 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
247 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
248 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
249 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
250 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
251 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
253 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
254 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
255 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
256 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
257 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
260 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
261 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
262 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
263 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
264 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
265 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
266 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
268 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
269 OUT_RING(ring
, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE
|
270 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE
|
271 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE
|
272 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE
|
273 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE
);
275 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
276 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
277 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
279 OUT_PKT3(ring
, CP_DRAW_INDX_2
, 5);
280 OUT_RING(ring
, 0x00000000); /* viz query info. */
281 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_IMMEDIATE
,
282 INDEX_SIZE_32_BIT
, IGNORE_VISIBILITY
, 0));
283 OUT_RING(ring
, 2); /* NumIndices */
288 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 1);
289 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS
));
291 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
292 OUT_RING(ring
, 0x00000000);
295 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_SIZE
, 1);
296 OUT_RING(ring
, A3XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
297 A3XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
299 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
300 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
301 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
302 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
304 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
305 OUT_RING(ring
, 0x00000000);
308 /* transfer from gmem to system memory (ie. normal RAM) */
311 emit_gmem2mem_surf(struct fd_context
*ctx
,
312 enum adreno_rb_copy_control_mode mode
,
314 uint32_t base
, struct pipe_surface
*psurf
)
316 struct fd_ringbuffer
*ring
= ctx
->ring
;
317 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
318 enum pipe_format format
= psurf
->format
;
321 format
= rsc
->base
.b
.format
;
323 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
324 uint32_t offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
325 psurf
->u
.tex
.first_layer
);
327 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
329 OUT_PKT0(ring
, REG_A3XX_RB_COPY_CONTROL
, 4);
330 OUT_RING(ring
, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
331 A3XX_RB_COPY_CONTROL_MODE(mode
) |
332 A3XX_RB_COPY_CONTROL_GMEM_BASE(base
) |
333 COND(format
== PIPE_FORMAT_Z32_FLOAT
||
334 format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
,
335 A3XX_RB_COPY_CONTROL_UNK12
));
337 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, -1); /* RB_COPY_DEST_BASE */
338 OUT_RING(ring
, A3XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->cpp
));
339 OUT_RING(ring
, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR
) |
340 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format
)) |
341 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
342 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
343 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format
)));
345 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
346 DI_SRC_SEL_AUTO_INDEX
, 2, 0, INDEX_SIZE_IGN
, 0, 0, NULL
);
350 fd3_emit_tile_gmem2mem(struct fd_context
*ctx
, struct fd_tile
*tile
)
352 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
353 struct fd_ringbuffer
*ring
= ctx
->ring
;
354 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
355 struct fd3_emit emit
= {
356 .debug
= &ctx
->debug
,
357 .vtx
= &fd3_ctx
->solid_vbuf_state
,
358 .prog
= &ctx
->solid_prog
,
360 .half_precision
= true,
365 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
366 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
368 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
369 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
370 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
371 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
372 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
373 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
374 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
375 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
376 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
378 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
379 OUT_RING(ring
, 0xff000000 |
380 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
381 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
382 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
383 OUT_RING(ring
, 0xff000000 |
384 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
385 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
386 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
388 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
389 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
391 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
392 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
395 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
396 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb
->width
/2.0 - 0.5));
397 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb
->width
/2.0));
398 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb
->height
/2.0 - 0.5));
399 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb
->height
/2.0));
400 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
401 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
403 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
404 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
405 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
406 A3XX_RB_MODE_CONTROL_MRT(0));
408 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
409 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
410 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
411 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
412 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx
->gmem
.bin_w
));
414 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
415 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
416 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
417 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
419 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
420 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
421 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
422 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
423 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
425 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
426 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
427 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
428 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
429 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
431 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
432 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
433 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
434 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
435 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
437 fd3_program_emit(ring
, &emit
, 0, NULL
);
438 fd3_emit_vertex_bufs(ring
, &emit
);
440 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
441 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
442 if (!rsc
->stencil
|| ctx
->resolve
& FD_BUFFER_DEPTH
)
443 emit_gmem2mem_surf(ctx
, RB_COPY_DEPTH_STENCIL
, false,
444 ctx
->gmem
.zsbuf_base
[0], pfb
->zsbuf
);
445 if (rsc
->stencil
&& ctx
->resolve
& FD_BUFFER_STENCIL
)
446 emit_gmem2mem_surf(ctx
, RB_COPY_DEPTH_STENCIL
, true,
447 ctx
->gmem
.zsbuf_base
[1], pfb
->zsbuf
);
450 if (ctx
->resolve
& FD_BUFFER_COLOR
) {
451 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
454 if (!(ctx
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
456 emit_gmem2mem_surf(ctx
, RB_COPY_RESOLVE
, false,
457 ctx
->gmem
.cbuf_base
[i
], pfb
->cbufs
[i
]);
461 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
462 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
463 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
464 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb
->nr_cbufs
) - 1));
466 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
467 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
468 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
469 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
472 /* transfer from system memory to gmem */
475 emit_mem2gmem_surf(struct fd_context
*ctx
, uint32_t bases
[],
476 struct pipe_surface
**psurf
, uint32_t bufs
, uint32_t bin_w
)
478 struct fd_ringbuffer
*ring
= ctx
->ring
;
479 struct pipe_surface
*zsbufs
[2];
483 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
484 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
485 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
486 A3XX_RB_MODE_CONTROL_MRT(bufs
- 1));
488 emit_mrt(ring
, bufs
, psurf
, bases
, bin_w
, false);
490 if (psurf
[0] && (psurf
[0]->format
== PIPE_FORMAT_Z32_FLOAT
||
491 psurf
[0]->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
492 /* Depth is stored as unorm in gmem, so we have to write it in using a
493 * special blit shader which writes depth.
495 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
496 OUT_RING(ring
, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
|
497 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
498 A3XX_RB_DEPTH_CONTROL_Z_ENABLE
|
499 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
|
500 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
)));
502 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_INFO
, 2);
503 OUT_RING(ring
, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases
[0]) |
504 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32
));
505 OUT_RING(ring
, A3XX_RB_DEPTH_PITCH(4 * ctx
->gmem
.bin_w
));
507 if (psurf
[0]->format
== PIPE_FORMAT_Z32_FLOAT
) {
508 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(0), 1);
511 /* The gmem_restore_tex logic will put the first buffer's stencil
512 * as color. Supply it with the proper information to make that
515 zsbufs
[0] = zsbufs
[1] = psurf
[0];
520 OUT_PKT0(ring
, REG_A3XX_SP_FS_OUTPUT_REG
, 1);
521 OUT_RING(ring
, A3XX_SP_FS_OUTPUT_REG_MRT(bufs
- 1));
524 fd3_emit_gmem_restore_tex(ring
, psurf
, bufs
);
526 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
527 DI_SRC_SEL_AUTO_INDEX
, 2, 0, INDEX_SIZE_IGN
, 0, 0, NULL
);
531 fd3_emit_tile_mem2gmem(struct fd_context
*ctx
, struct fd_tile
*tile
)
533 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
534 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
535 struct fd_ringbuffer
*ring
= ctx
->ring
;
536 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
537 struct fd3_emit emit
= {
538 .debug
= &ctx
->debug
,
539 .vtx
= &fd3_ctx
->blit_vbuf_state
,
540 .sprite_coord_enable
= 1,
541 /* NOTE: They all use the same VP, this is for vtx bufs. */
542 .prog
= &ctx
->blit_prog
[0],
544 .half_precision
= fd_half_precision(pfb
),
547 float x0
, y0
, x1
, y1
;
548 unsigned bin_w
= tile
->bin_w
;
549 unsigned bin_h
= tile
->bin_h
;
552 /* write texture coordinates to vertexbuf: */
553 x0
= ((float)tile
->xoff
) / ((float)pfb
->width
);
554 x1
= ((float)tile
->xoff
+ bin_w
) / ((float)pfb
->width
);
555 y0
= ((float)tile
->yoff
) / ((float)pfb
->height
);
556 y1
= ((float)tile
->yoff
+ bin_h
) / ((float)pfb
->height
);
558 OUT_PKT3(ring
, CP_MEM_WRITE
, 5);
559 OUT_RELOCW(ring
, fd_resource(fd3_ctx
->blit_texcoord_vbuf
)->bo
, 0, 0, 0);
560 OUT_RING(ring
, fui(x0
));
561 OUT_RING(ring
, fui(y0
));
562 OUT_RING(ring
, fui(x1
));
563 OUT_RING(ring
, fui(y1
));
565 fd3_emit_cache_flush(ctx
, ring
);
567 for (i
= 0; i
< 4; i
++) {
568 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
569 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
570 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE
) |
571 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
573 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
574 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
575 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
576 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
577 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
578 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
579 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
582 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
583 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
) |
584 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
587 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
588 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS
));
590 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_INFO
, 2);
594 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
595 OUT_RING(ring
, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER
); /* GRAS_CL_CLIP_CNTL */
598 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
599 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w
/2.0 - 0.5));
600 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w
/2.0));
601 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h
/2.0 - 0.5));
602 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h
/2.0));
603 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
604 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
606 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
607 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
608 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
609 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w
- 1) |
610 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h
- 1));
612 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
613 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
614 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
615 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w
- 1) |
616 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h
- 1));
618 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
620 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
621 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
622 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
623 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
624 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS
) |
625 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
626 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
627 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
629 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_INFO
, 2);
630 OUT_RING(ring
, 0); /* RB_STENCIL_INFO */
631 OUT_RING(ring
, 0); /* RB_STENCIL_PITCH */
633 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
634 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
635 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
636 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
638 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
639 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
640 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
641 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
642 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
644 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
645 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
646 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
647 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
648 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
650 fd3_emit_vertex_bufs(ring
, &emit
);
652 /* for gmem pitch/base calculations, we need to use the non-
653 * truncated tile sizes:
658 if (fd_gmem_needs_restore(ctx
, tile
, FD_BUFFER_COLOR
)) {
659 emit
.prog
= &ctx
->blit_prog
[pfb
->nr_cbufs
- 1];
660 emit
.fp
= NULL
; /* frag shader changed so clear cache */
661 fd3_program_emit(ring
, &emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
662 emit_mem2gmem_surf(ctx
, gmem
->cbuf_base
, pfb
->cbufs
, pfb
->nr_cbufs
, bin_w
);
665 if (fd_gmem_needs_restore(ctx
, tile
, FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
666 if (pfb
->zsbuf
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
&&
667 pfb
->zsbuf
->format
!= PIPE_FORMAT_Z32_FLOAT
) {
668 /* Non-float can use a regular color write. It's split over 8-bit
669 * components, so half precision is always sufficient.
671 emit
.prog
= &ctx
->blit_prog
[0];
672 emit
.key
.half_precision
= true;
674 /* Float depth needs special blit shader that writes depth */
675 if (pfb
->zsbuf
->format
== PIPE_FORMAT_Z32_FLOAT
)
676 emit
.prog
= &ctx
->blit_z
;
678 emit
.prog
= &ctx
->blit_zs
;
679 emit
.key
.half_precision
= false;
681 emit
.fp
= NULL
; /* frag shader changed so clear cache */
682 fd3_program_emit(ring
, &emit
, 1, &pfb
->zsbuf
);
683 emit_mem2gmem_surf(ctx
, gmem
->zsbuf_base
, &pfb
->zsbuf
, 1, bin_w
);
686 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
687 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
688 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
689 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
691 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
692 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
693 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
694 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb
->nr_cbufs
) - 1));
698 patch_draws(struct fd_context
*ctx
, enum pc_di_vis_cull_mode vismode
)
701 for (i
= 0; i
< fd_patch_num_elements(&ctx
->draw_patches
); i
++) {
702 struct fd_cs_patch
*patch
= fd_patch_element(&ctx
->draw_patches
, i
);
703 *patch
->cs
= patch
->val
| DRAW(0, 0, 0, vismode
, 0);
705 util_dynarray_resize(&ctx
->draw_patches
, 0);
709 patch_rbrc(struct fd_context
*ctx
, uint32_t val
)
711 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
713 for (i
= 0; i
< fd_patch_num_elements(&fd3_ctx
->rbrc_patches
); i
++) {
714 struct fd_cs_patch
*patch
= fd_patch_element(&fd3_ctx
->rbrc_patches
, i
);
715 *patch
->cs
= patch
->val
| val
;
717 util_dynarray_resize(&fd3_ctx
->rbrc_patches
, 0);
720 /* for rendering directly to system memory: */
722 fd3_emit_sysmem_prep(struct fd_context
*ctx
)
724 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
725 struct fd_ringbuffer
*ring
= ctx
->ring
;
726 uint32_t i
, pitch
= 0;
728 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
729 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
732 pitch
= fd_resource(psurf
->texture
)->slices
[psurf
->u
.tex
.level
].pitch
;
735 fd3_emit_restore(ctx
, ring
);
737 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
738 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
739 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
741 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, 0, true);
743 /* setup scissor/offset for current tile: */
744 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
745 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
746 A3XX_RB_WINDOW_OFFSET_Y(0));
748 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
749 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
750 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
751 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb
->width
- 1) |
752 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb
->height
- 1));
754 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
755 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
756 A3XX_RB_MODE_CONTROL_GMEM_BYPASS
|
757 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
758 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb
->nr_cbufs
) - 1));
760 patch_draws(ctx
, IGNORE_VISIBILITY
);
761 patch_rbrc(ctx
, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch
));
765 update_vsc_pipe(struct fd_context
*ctx
)
767 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
768 struct fd_ringbuffer
*ring
= ctx
->ring
;
771 OUT_PKT0(ring
, REG_A3XX_VSC_SIZE_ADDRESS
, 1);
772 OUT_RELOCW(ring
, fd3_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
774 for (i
= 0; i
< 8; i
++) {
775 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
778 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x40000,
779 DRM_FREEDRENO_GEM_TYPE_KMEM
);
782 OUT_PKT0(ring
, REG_A3XX_VSC_PIPE(i
), 3);
783 OUT_RING(ring
, A3XX_VSC_PIPE_CONFIG_X(pipe
->x
) |
784 A3XX_VSC_PIPE_CONFIG_Y(pipe
->y
) |
785 A3XX_VSC_PIPE_CONFIG_W(pipe
->w
) |
786 A3XX_VSC_PIPE_CONFIG_H(pipe
->h
));
787 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
788 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE[i].DATA_LENGTH */
793 emit_binning_pass(struct fd_context
*ctx
)
795 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
796 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
797 struct fd_batch
*batch
= ctx
->batch
;
798 struct fd_ringbuffer
*ring
= ctx
->ring
;
801 uint32_t x1
= gmem
->minx
;
802 uint32_t y1
= gmem
->miny
;
803 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
804 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
806 if (ctx
->screen
->gpu_id
== 320) {
807 emit_binning_workaround(ctx
);
809 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
810 OUT_RING(ring
, 0x00007fff);
813 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_CONTROL
, 1);
814 OUT_RING(ring
, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE
);
816 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
817 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
818 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
819 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
821 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
822 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
823 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
825 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
826 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
827 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
828 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
830 /* setup scissor/offset for whole screen: */
831 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
832 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(x1
) |
833 A3XX_RB_WINDOW_OFFSET_Y(y1
));
835 OUT_PKT0(ring
, REG_A3XX_RB_LRZ_VSC_CONTROL
, 1);
836 OUT_RING(ring
, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE
);
838 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
839 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
840 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
841 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
842 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
844 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
845 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
846 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
847 A3XX_RB_MODE_CONTROL_MRT(0));
849 for (i
= 0; i
< 4; i
++) {
850 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
851 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR
) |
852 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE
) |
853 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
856 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
857 OUT_RING(ring
, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
858 A3XX_PC_VSTREAM_CONTROL_N(0));
860 /* emit IB to binning drawcmds: */
861 ctx
->emit_ib(ring
, batch
->binning
);
866 /* and then put stuff back the way it was: */
868 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_CONTROL
, 1);
869 OUT_RING(ring
, 0x00000000);
871 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
872 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_RESOLVE
|
873 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
874 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
875 A3XX_SP_SP_CTRL_REG_L0MODE(0));
877 OUT_PKT0(ring
, REG_A3XX_RB_LRZ_VSC_CONTROL
, 1);
878 OUT_RING(ring
, 0x00000000);
880 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
881 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
882 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
883 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
885 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 2);
886 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
887 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
888 A3XX_RB_MODE_CONTROL_MRT(pfb
->nr_cbufs
- 1));
889 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
890 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
891 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
893 fd_event_write(ctx
, ring
, CACHE_FLUSH
);
896 if (ctx
->screen
->gpu_id
== 320) {
897 /* dummy-draw workaround: */
898 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
899 OUT_RING(ring
, 0x00000000);
900 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
901 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
902 OUT_RING(ring
, 0); /* NumIndices */
906 OUT_PKT3(ring
, CP_NOP
, 4);
907 OUT_RING(ring
, 0x00000000);
908 OUT_RING(ring
, 0x00000000);
909 OUT_RING(ring
, 0x00000000);
910 OUT_RING(ring
, 0x00000000);
914 if (ctx
->screen
->gpu_id
== 320) {
915 emit_binning_workaround(ctx
);
919 /* before first tile */
921 fd3_emit_tile_init(struct fd_context
*ctx
)
923 struct fd_ringbuffer
*ring
= ctx
->ring
;
924 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
925 uint32_t rb_render_control
;
927 fd3_emit_restore(ctx
, ring
);
929 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
930 * at the right and bottom edge tiles
932 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_SIZE
, 1);
933 OUT_RING(ring
, A3XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
934 A3XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
936 update_vsc_pipe(ctx
);
938 if (use_hw_binning(ctx
)) {
939 /* emit hw binning pass: */
940 emit_binning_pass(ctx
);
942 patch_draws(ctx
, USE_VISIBILITY
);
944 patch_draws(ctx
, IGNORE_VISIBILITY
);
947 rb_render_control
= A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
948 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
);
950 patch_rbrc(ctx
, rb_render_control
);
953 /* before mem2gmem */
955 fd3_emit_tile_prep(struct fd_context
*ctx
, struct fd_tile
*tile
)
957 struct fd_ringbuffer
*ring
= ctx
->ring
;
958 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
960 if (ctx
->needs_rb_fbd
) {
962 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
963 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
964 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
965 ctx
->needs_rb_fbd
= false;
968 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
969 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
970 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
|
971 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb
->nr_cbufs
) - 1));
974 /* before IB to rendering cmds: */
976 fd3_emit_tile_renderprep(struct fd_context
*ctx
, struct fd_tile
*tile
)
978 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
979 struct fd_ringbuffer
*ring
= ctx
->ring
;
980 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
981 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
983 uint32_t x1
= tile
->xoff
;
984 uint32_t y1
= tile
->yoff
;
985 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
986 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
990 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_INFO
, 2);
991 reg
= A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem
->zsbuf_base
[0]);
993 reg
|= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb
->zsbuf
->format
));
997 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
998 OUT_RING(ring
, A3XX_RB_DEPTH_PITCH(rsc
->cpp
* gmem
->bin_w
));
1000 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_INFO
, 2);
1001 OUT_RING(ring
, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem
->zsbuf_base
[1]));
1002 OUT_RING(ring
, A3XX_RB_STENCIL_PITCH(rsc
->stencil
->cpp
* gmem
->bin_w
));
1005 OUT_RING(ring
, 0x00000000);
1008 if (use_hw_binning(ctx
)) {
1009 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[tile
->p
];
1011 assert(pipe
->w
* pipe
->h
);
1013 fd_event_write(ctx
, ring
, HLSQ_FLUSH
);
1016 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
1017 OUT_RING(ring
, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe
->w
* pipe
->h
) |
1018 A3XX_PC_VSTREAM_CONTROL_N(tile
->n
));
1021 OUT_PKT3(ring
, CP_SET_BIN_DATA
, 2);
1022 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1023 OUT_RELOCW(ring
, fd3_ctx
->vsc_size_mem
, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1024 (tile
->p
* 4), 0, 0);
1026 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
1027 OUT_RING(ring
, 0x00000000);
1030 OUT_PKT3(ring
, CP_SET_BIN
, 3);
1031 OUT_RING(ring
, 0x00000000);
1032 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
1033 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
1035 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, gmem
->cbuf_base
, gmem
->bin_w
, true);
1037 /* setup scissor/offset for current tile: */
1038 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
1039 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(tile
->xoff
) |
1040 A3XX_RB_WINDOW_OFFSET_Y(tile
->yoff
));
1042 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
1043 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
1044 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
1045 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
1046 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
1050 fd3_gmem_init(struct pipe_context
*pctx
)
1052 struct fd_context
*ctx
= fd_context(pctx
);
1054 ctx
->emit_sysmem_prep
= fd3_emit_sysmem_prep
;
1055 ctx
->emit_tile_init
= fd3_emit_tile_init
;
1056 ctx
->emit_tile_prep
= fd3_emit_tile_prep
;
1057 ctx
->emit_tile_mem2gmem
= fd3_emit_tile_mem2gmem
;
1058 ctx
->emit_tile_renderprep
= fd3_emit_tile_renderprep
;
1059 ctx
->emit_tile_gmem2mem
= fd3_emit_tile_gmem2mem
;