1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
40 #include "fd3_context.h"
42 #include "fd3_program.h"
46 static const struct fd3_shader_key key
= {
47 // XXX should set this based on render target format! We don't
48 // want half_precision if float32 render target!!!
49 .half_precision
= true,
53 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
54 struct pipe_surface
**bufs
, uint32_t *bases
, uint32_t bin_w
)
56 enum a3xx_tile_mode tile_mode
;
60 tile_mode
= TILE_32X32
;
65 for (i
= 0; i
< 4; i
++) {
66 enum a3xx_color_fmt format
= 0;
67 enum a3xx_color_swap swap
= WZYX
;
68 struct fd_resource
*rsc
= NULL
;
69 struct fd_resource_slice
*slice
= NULL
;
73 if ((i
< nr_bufs
) && bufs
[i
]) {
74 struct pipe_surface
*psurf
= bufs
[i
];
76 rsc
= fd_resource(psurf
->texture
);
77 slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
78 format
= fd3_pipe2color(psurf
->format
);
79 swap
= fd3_pipe2swap(psurf
->format
);
82 stride
= bin_w
* rsc
->cpp
;
85 base
= bases
[i
] * rsc
->cpp
;
88 stride
= slice
->pitch
* rsc
->cpp
;
92 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BUF_INFO(i
), 2);
93 OUT_RING(ring
, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
94 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
95 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
96 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
));
97 if (bin_w
|| (i
>= nr_bufs
)) {
98 OUT_RING(ring
, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base
));
100 OUT_RELOCW(ring
, rsc
->bo
, slice
->offset
, 0, -1);
103 OUT_PKT0(ring
, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i
), 1);
104 OUT_RING(ring
, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format
));
109 depth_base(struct fd_gmem_stateobj
*gmem
)
111 return align(gmem
->bin_w
* gmem
->bin_h
, 0x4000);
115 use_hw_binning(struct fd_context
*ctx
)
117 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
119 /* workaround: combining scissor optimization and hw binning
120 * seems problematic. Seems like we end up with a mismatch
121 * between binning pass and rendering pass, wrt. where the hw
122 * thinks the vertices belong. And the blob driver doesn't
123 * seem to implement anything like scissor optimization, so
124 * not entirely sure what I might be missing.
126 * But scissor optimization is mainly for window managers,
127 * which don't have many vertices (and therefore doesn't
128 * benefit much from binning pass).
130 * So for now just disable binning if scissor optimization is
133 if (gmem
->minx
|| gmem
->miny
)
136 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2);
139 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
140 static void update_vsc_pipe(struct fd_context
*ctx
);
142 emit_binning_workaround(struct fd_context
*ctx
)
144 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
145 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
146 struct fd_ringbuffer
*ring
= ctx
->ring
;
148 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 2);
149 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
150 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
151 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
152 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
153 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
));
155 OUT_PKT0(ring
, REG_A3XX_RB_COPY_CONTROL
, 4);
156 OUT_RING(ring
, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
157 A3XX_RB_COPY_CONTROL_MODE(0) |
158 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
159 OUT_RELOC(ring
, fd_resource(fd3_ctx
->solid_vbuf
)->bo
, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
160 OUT_RING(ring
, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
161 OUT_RING(ring
, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR
) |
162 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM
) |
163 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX
) |
164 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
165 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
));
167 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
168 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
169 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
170 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
173 fd3_program_emit(ring
, &ctx
->solid_prog
, key
);
174 fd3_emit_vertex_bufs(ring
, fd3_shader_variant(ctx
->solid_prog
.vp
, key
),
175 (struct fd3_vertex_buf
[]) {{
176 .prsc
= fd3_ctx
->solid_vbuf
,
178 .format
= PIPE_FORMAT_R32G32B32_FLOAT
,
181 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 4);
182 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
183 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
184 A3XX_HLSQ_CONTROL_0_REG_RESERVED2
|
185 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
186 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
187 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
);
188 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
189 OUT_RING(ring
, 0); /* HLSQ_CONTROL_3_REG */
191 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG
, 1);
192 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
193 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
195 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
196 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
197 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
198 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
200 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
201 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
203 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
204 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
205 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
206 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
207 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
208 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
209 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
210 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
211 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
213 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
214 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
216 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
217 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
218 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
219 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
220 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
222 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
223 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
224 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
225 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
226 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
228 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
229 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
230 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
231 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
232 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
234 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
235 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
236 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
237 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
238 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
240 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
241 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
242 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
243 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
244 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
245 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
246 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
248 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
249 OUT_RING(ring
, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE
|
250 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE
|
251 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE
|
252 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE
|
253 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE
);
255 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
256 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
257 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
259 OUT_PKT3(ring
, CP_DRAW_INDX_2
, 5);
260 OUT_RING(ring
, 0x00000000); /* viz query info. */
261 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_IMMEDIATE
,
262 INDEX_SIZE_32_BIT
, IGNORE_VISIBILITY
));
263 OUT_RING(ring
, 2); /* NumIndices */
268 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 1);
269 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS
));
271 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
272 OUT_RING(ring
, 0x00000000);
275 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_SIZE
, 1);
276 OUT_RING(ring
, A3XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
277 A3XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
279 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
280 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
281 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
282 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
284 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
285 OUT_RING(ring
, 0x00000000);
288 /* transfer from gmem to system memory (ie. normal RAM) */
291 emit_gmem2mem_surf(struct fd_context
*ctx
,
292 enum adreno_rb_copy_control_mode mode
,
293 uint32_t base
, struct pipe_surface
*psurf
)
295 struct fd_ringbuffer
*ring
= ctx
->ring
;
296 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
297 struct fd_resource_slice
*slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
299 OUT_PKT0(ring
, REG_A3XX_RB_COPY_CONTROL
, 4);
300 OUT_RING(ring
, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
301 A3XX_RB_COPY_CONTROL_MODE(mode
) |
302 A3XX_RB_COPY_CONTROL_GMEM_BASE(base
));
303 OUT_RELOCW(ring
, rsc
->bo
, slice
->offset
, 0, -1); /* RB_COPY_DEST_BASE */
304 OUT_RING(ring
, A3XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->cpp
));
305 OUT_RING(ring
, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR
) |
306 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf
->format
)) |
307 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
308 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
309 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf
->format
)));
311 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
312 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
316 fd3_emit_tile_gmem2mem(struct fd_context
*ctx
, struct fd_tile
*tile
)
318 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
319 struct fd_ringbuffer
*ring
= ctx
->ring
;
320 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
322 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
323 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
325 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
326 OUT_RING(ring
, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
327 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
328 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
329 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
330 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
331 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
332 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
333 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
335 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
336 OUT_RING(ring
, 0xff000000 |
337 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
338 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
339 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
340 OUT_RING(ring
, 0xff000000 |
341 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
342 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
343 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
345 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
346 OUT_RING(ring
, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
348 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
349 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
351 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
352 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb
->width
/2.0 - 0.5));
353 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb
->width
/2.0));
354 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb
->height
/2.0 - 0.5));
355 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb
->height
/2.0));
356 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
357 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
359 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
360 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
361 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
363 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
364 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
365 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
366 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
367 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx
->gmem
.bin_w
));
369 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
370 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
371 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
372 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
374 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
375 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
376 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
377 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
378 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
380 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
381 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
382 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
383 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
384 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
386 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
387 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
388 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
389 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
390 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
393 fd3_program_emit(ring
, &ctx
->solid_prog
, key
);
394 fd3_emit_vertex_bufs(ring
, fd3_shader_variant(ctx
->solid_prog
.vp
, key
),
395 (struct fd3_vertex_buf
[]) {{
396 .prsc
= fd3_ctx
->solid_vbuf
,
398 .format
= PIPE_FORMAT_R32G32B32_FLOAT
,
401 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
404 struct fd_resource
*rsc
=
405 fd_resource(pfb
->cbufs
[0]->texture
);
406 base
= depth_base(&ctx
->gmem
) * rsc
->cpp
;
408 emit_gmem2mem_surf(ctx
, RB_COPY_DEPTH_STENCIL
, base
, pfb
->zsbuf
);
411 if (ctx
->resolve
& FD_BUFFER_COLOR
) {
412 emit_gmem2mem_surf(ctx
, RB_COPY_RESOLVE
, 0, pfb
->cbufs
[0]);
415 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
416 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
417 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
419 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
420 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
421 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
422 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
425 /* transfer from system memory to gmem */
428 emit_mem2gmem_surf(struct fd_context
*ctx
, uint32_t base
,
429 struct pipe_surface
*psurf
, uint32_t bin_w
)
431 struct fd_ringbuffer
*ring
= ctx
->ring
;
433 emit_mrt(ring
, 1, &psurf
, &base
, bin_w
);
436 fd3_emit_gmem_restore_tex(ring
, psurf
);
438 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
439 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
443 fd3_emit_tile_mem2gmem(struct fd_context
*ctx
, struct fd_tile
*tile
)
445 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
446 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
447 struct fd_ringbuffer
*ring
= ctx
->ring
;
448 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
449 float x0
, y0
, x1
, y1
;
450 unsigned bin_w
= tile
->bin_w
;
451 unsigned bin_h
= tile
->bin_h
;
454 /* write texture coordinates to vertexbuf: */
455 x0
= ((float)tile
->xoff
) / ((float)pfb
->width
);
456 x1
= ((float)tile
->xoff
+ bin_w
) / ((float)pfb
->width
);
457 y0
= ((float)tile
->yoff
) / ((float)pfb
->height
);
458 y1
= ((float)tile
->yoff
+ bin_h
) / ((float)pfb
->height
);
460 OUT_PKT3(ring
, CP_MEM_WRITE
, 5);
461 OUT_RELOC(ring
, fd_resource(fd3_ctx
->blit_texcoord_vbuf
)->bo
, 0, 0, 0);
462 OUT_RING(ring
, fui(x0
));
463 OUT_RING(ring
, fui(y0
));
464 OUT_RING(ring
, fui(x1
));
465 OUT_RING(ring
, fui(y1
));
467 for (i
= 0; i
< 4; i
++) {
468 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
469 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
470 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE
) |
471 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
473 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
474 OUT_RING(ring
, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
475 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
476 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
477 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
478 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
479 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
) |
480 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
);
483 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
484 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
) |
485 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
487 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
488 OUT_RING(ring
, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS
));
490 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
491 OUT_RING(ring
, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER
); /* GRAS_CL_CLIP_CNTL */
493 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
494 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w
/2.0 - 0.5));
495 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w
/2.0));
496 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h
/2.0 - 0.5));
497 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h
/2.0));
498 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
499 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
501 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
502 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
503 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
504 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w
- 1) |
505 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h
- 1));
507 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
508 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
509 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
510 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w
- 1) |
511 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h
- 1));
513 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
515 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
516 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
517 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
518 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
519 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS
) |
520 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
521 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
522 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
524 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
525 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
526 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
527 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
529 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
530 OUT_RING(ring
, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
531 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
532 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES
) |
533 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
535 OUT_PKT0(ring
, REG_A3XX_VFD_INDEX_MIN
, 4);
536 OUT_RING(ring
, 0); /* VFD_INDEX_MIN */
537 OUT_RING(ring
, 2); /* VFD_INDEX_MAX */
538 OUT_RING(ring
, 0); /* VFD_INSTANCEID_OFFSET */
539 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
542 fd3_program_emit(ring
, &ctx
->blit_prog
, key
);
543 fd3_emit_vertex_bufs(ring
, fd3_shader_variant(ctx
->blit_prog
.vp
, key
),
544 (struct fd3_vertex_buf
[]) {{
545 .prsc
= fd3_ctx
->blit_texcoord_vbuf
,
547 .format
= PIPE_FORMAT_R32G32_FLOAT
,
549 .prsc
= fd3_ctx
->solid_vbuf
,
551 .format
= PIPE_FORMAT_R32G32B32_FLOAT
,
554 /* for gmem pitch/base calculations, we need to use the non-
555 * truncated tile sizes:
560 if (ctx
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
))
561 emit_mem2gmem_surf(ctx
, depth_base(gmem
), pfb
->zsbuf
, bin_w
);
563 if (ctx
->restore
& FD_BUFFER_COLOR
)
564 emit_mem2gmem_surf(ctx
, 0, pfb
->cbufs
[0], bin_w
);
566 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
567 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
568 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
569 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
573 patch_draws(struct fd_context
*ctx
, enum pc_di_vis_cull_mode vismode
)
576 for (i
= 0; i
< fd_patch_num_elements(&ctx
->draw_patches
); i
++) {
577 struct fd_cs_patch
*patch
= fd_patch_element(&ctx
->draw_patches
, i
);
578 *patch
->cs
= patch
->val
| DRAW(0, 0, 0, vismode
);
580 util_dynarray_resize(&ctx
->draw_patches
, 0);
584 patch_rbrc(struct fd_context
*ctx
, uint32_t val
)
586 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
588 for (i
= 0; i
< fd_patch_num_elements(&fd3_ctx
->rbrc_patches
); i
++) {
589 struct fd_cs_patch
*patch
= fd_patch_element(&fd3_ctx
->rbrc_patches
, i
);
590 *patch
->cs
= patch
->val
| val
;
592 util_dynarray_resize(&fd3_ctx
->rbrc_patches
, 0);
595 /* for rendering directly to system memory: */
597 fd3_emit_sysmem_prep(struct fd_context
*ctx
)
599 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
600 struct fd_ringbuffer
*ring
= ctx
->ring
;
604 pitch
= fd_resource(pfb
->cbufs
[0]->texture
)->slices
[0].pitch
;
606 fd3_emit_restore(ctx
);
608 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
609 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
610 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
612 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, 0);
614 /* setup scissor/offset for current tile: */
615 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
616 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
617 A3XX_RB_WINDOW_OFFSET_Y(0));
619 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
620 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
621 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
622 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb
->width
- 1) |
623 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb
->height
- 1));
625 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
626 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
627 A3XX_RB_MODE_CONTROL_GMEM_BYPASS
|
628 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
630 patch_draws(ctx
, IGNORE_VISIBILITY
);
631 patch_rbrc(ctx
, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch
));
635 update_vsc_pipe(struct fd_context
*ctx
)
637 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
638 struct fd_ringbuffer
*ring
= ctx
->ring
;
641 OUT_PKT0(ring
, REG_A3XX_VSC_SIZE_ADDRESS
, 1);
642 OUT_RELOC(ring
, fd3_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
644 for (i
= 0; i
< 8; i
++) {
645 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
648 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x40000,
649 DRM_FREEDRENO_GEM_TYPE_KMEM
);
652 OUT_PKT0(ring
, REG_A3XX_VSC_PIPE(i
), 3);
653 OUT_RING(ring
, A3XX_VSC_PIPE_CONFIG_X(pipe
->x
) |
654 A3XX_VSC_PIPE_CONFIG_Y(pipe
->y
) |
655 A3XX_VSC_PIPE_CONFIG_W(pipe
->w
) |
656 A3XX_VSC_PIPE_CONFIG_H(pipe
->h
));
657 OUT_RELOC(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
658 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE[i].DATA_LENGTH */
663 emit_binning_pass(struct fd_context
*ctx
)
665 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
666 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
667 struct fd_ringbuffer
*ring
= ctx
->ring
;
670 uint32_t x1
= gmem
->minx
;
671 uint32_t y1
= gmem
->miny
;
672 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
673 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
675 if (ctx
->screen
->gpu_id
== 320) {
676 emit_binning_workaround(ctx
);
678 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
679 OUT_RING(ring
, 0x00007fff);
682 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_CONTROL
, 1);
683 OUT_RING(ring
, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE
);
685 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
686 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
687 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
688 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
690 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
691 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
692 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
694 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
695 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
696 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
697 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
699 /* setup scissor/offset for whole screen: */
700 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
701 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(x1
) |
702 A3XX_RB_WINDOW_OFFSET_Y(y1
));
704 OUT_PKT0(ring
, REG_A3XX_RB_LRZ_VSC_CONTROL
, 1);
705 OUT_RING(ring
, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE
);
707 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
708 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
709 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
710 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
711 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
713 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
714 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
715 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
717 for (i
= 0; i
< 4; i
++) {
718 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
719 OUT_RING(ring
, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR
) |
720 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE
) |
721 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
724 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
725 OUT_RING(ring
, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
726 A3XX_PC_VSTREAM_CONTROL_N(0));
728 /* emit IB to binning drawcmds: */
729 OUT_IB(ring
, ctx
->binning_start
, ctx
->binning_end
);
734 /* and then put stuff back the way it was: */
736 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_CONTROL
, 1);
737 OUT_RING(ring
, 0x00000000);
739 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
740 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_RESOLVE
|
741 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
742 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
743 A3XX_SP_SP_CTRL_REG_L0MODE(0));
745 OUT_PKT0(ring
, REG_A3XX_RB_LRZ_VSC_CONTROL
, 1);
746 OUT_RING(ring
, 0x00000000);
748 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
749 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
750 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
751 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
753 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 2);
754 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
755 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
756 OUT_RING(ring
, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
757 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
) |
758 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
760 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
761 OUT_RING(ring
, CACHE_FLUSH
);
763 if (ctx
->screen
->gpu_id
== 320) {
764 /* dummy-draw workaround: */
765 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
766 OUT_RING(ring
, 0x00000000);
767 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
768 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
769 OUT_RING(ring
, 0); /* NumIndices */
773 OUT_PKT3(ring
, CP_NOP
, 4);
774 OUT_RING(ring
, 0x00000000);
775 OUT_RING(ring
, 0x00000000);
776 OUT_RING(ring
, 0x00000000);
777 OUT_RING(ring
, 0x00000000);
781 if (ctx
->screen
->gpu_id
== 320) {
782 emit_binning_workaround(ctx
);
786 /* before first tile */
788 fd3_emit_tile_init(struct fd_context
*ctx
)
790 struct fd_ringbuffer
*ring
= ctx
->ring
;
791 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
793 fd3_emit_restore(ctx
);
795 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
796 * at the right and bottom edge tiles
798 OUT_PKT0(ring
, REG_A3XX_VSC_BIN_SIZE
, 1);
799 OUT_RING(ring
, A3XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
800 A3XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
802 update_vsc_pipe(ctx
);
804 if (use_hw_binning(ctx
)) {
805 /* mark the end of the binning cmds: */
806 fd_ringmarker_mark(ctx
->binning_end
);
808 /* emit hw binning pass: */
809 emit_binning_pass(ctx
);
811 patch_draws(ctx
, USE_VISIBILITY
);
813 patch_draws(ctx
, IGNORE_VISIBILITY
);
816 patch_rbrc(ctx
, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
|
817 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem
->bin_w
));
820 /* before mem2gmem */
822 fd3_emit_tile_prep(struct fd_context
*ctx
, struct fd_tile
*tile
)
824 struct fd_ringbuffer
*ring
= ctx
->ring
;
825 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
826 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
829 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_INFO
, 2);
830 reg
= A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(gmem
));
832 reg
|= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb
->zsbuf
->format
));
836 uint32_t cpp
= util_format_get_blocksize(pfb
->zsbuf
->format
);
837 OUT_RING(ring
, A3XX_RB_DEPTH_PITCH(cpp
* gmem
->bin_w
));
839 OUT_RING(ring
, 0x00000000);
842 if (ctx
->needs_rb_fbd
) {
844 OUT_PKT0(ring
, REG_A3XX_RB_FRAME_BUFFER_DIMENSION
, 1);
845 OUT_RING(ring
, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
846 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
847 ctx
->needs_rb_fbd
= false;
850 OUT_PKT0(ring
, REG_A3XX_RB_MODE_CONTROL
, 1);
851 OUT_RING(ring
, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
852 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
);
855 /* before IB to rendering cmds: */
857 fd3_emit_tile_renderprep(struct fd_context
*ctx
, struct fd_tile
*tile
)
859 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
860 struct fd_ringbuffer
*ring
= ctx
->ring
;
861 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
862 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
864 uint32_t x1
= tile
->xoff
;
865 uint32_t y1
= tile
->yoff
;
866 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
867 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
869 if (use_hw_binning(ctx
)) {
870 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[tile
->p
];
872 assert(pipe
->w
* pipe
->h
);
874 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
875 OUT_RING(ring
, HLSQ_FLUSH
);
879 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
880 OUT_RING(ring
, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe
->w
* pipe
->h
) |
881 A3XX_PC_VSTREAM_CONTROL_N(tile
->n
));
883 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
884 OUT_RING(ring
, CACHE_FLUSH
);
886 OUT_PKT3(ring
, CP_SET_BIN_DATA
, 2);
887 OUT_RELOC(ring
, pipe
->bo
, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
888 OUT_RELOC(ring
, fd3_ctx
->vsc_size_mem
, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
889 (tile
->p
* 4), 0, 0);
891 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
892 OUT_RING(ring
, 0x00000000);
895 OUT_PKT3(ring
, CP_SET_BIN
, 3);
896 OUT_RING(ring
, 0x00000000);
897 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
898 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
900 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, gmem
->bin_w
);
902 /* setup scissor/offset for current tile: */
903 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
904 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(tile
->xoff
) |
905 A3XX_RB_WINDOW_OFFSET_Y(tile
->yoff
));
907 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
908 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
909 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
910 OUT_RING(ring
, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
911 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
915 fd3_gmem_init(struct pipe_context
*pctx
)
917 struct fd_context
*ctx
= fd_context(pctx
);
919 ctx
->emit_sysmem_prep
= fd3_emit_sysmem_prep
;
920 ctx
->emit_tile_init
= fd3_emit_tile_init
;
921 ctx
->emit_tile_prep
= fd3_emit_tile_prep
;
922 ctx
->emit_tile_mem2gmem
= fd3_emit_tile_mem2gmem
;
923 ctx
->emit_tile_renderprep
= fd3_emit_tile_renderprep
;
924 ctx
->emit_tile_gmem2mem
= fd3_emit_tile_gmem2mem
;