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81a613fa87028ad21a6ff09cf08c4a2518683734
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static void
47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
48 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
49 bool decode_srgb)
50 {
51 enum a3xx_tile_mode tile_mode;
52 unsigned i;
53
54 if (bin_w) {
55 tile_mode = TILE_32X32;
56 } else {
57 tile_mode = LINEAR;
58 }
59
60 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
61 enum pipe_format pformat = 0;
62 enum a3xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73
74 rsc = fd_resource(psurf->texture);
75 pformat = psurf->format;
76 /* In case we're drawing to Z32F_S8, the "color" actually goes to
77 * the stencil
78 */
79 if (rsc->stencil) {
80 rsc = rsc->stencil;
81 pformat = rsc->base.b.format;
82 bases++;
83 }
84 slice = fd_resource_slice(rsc, psurf->u.tex.level);
85 format = fd3_pipe2color(pformat);
86 swap = fd3_pipe2swap(pformat);
87 if (decode_srgb)
88 srgb = util_format_is_srgb(pformat);
89 else
90 pformat = util_format_linear(pformat);
91
92 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
93
94 offset = fd_resource_offset(rsc, psurf->u.tex.level,
95 psurf->u.tex.first_layer);
96
97 if (bin_w) {
98 stride = bin_w * rsc->cpp;
99
100 if (bases) {
101 base = bases[i];
102 }
103 } else {
104 stride = slice->pitch * rsc->cpp;
105 }
106 } else if (i < nr_bufs && bases) {
107 base = bases[i];
108 }
109
110 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
111 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
112 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
115 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
116 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
117 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
118 } else {
119 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
120 }
121
122 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
123 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
124 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
125 fd3_fs_output_format(pformat))));
126 }
127 }
128
129 static bool
130 use_hw_binning(struct fd_context *ctx)
131 {
132 struct fd_gmem_stateobj *gmem = &ctx->gmem;
133
134 /* workaround: combining scissor optimization and hw binning
135 * seems problematic. Seems like we end up with a mismatch
136 * between binning pass and rendering pass, wrt. where the hw
137 * thinks the vertices belong. And the blob driver doesn't
138 * seem to implement anything like scissor optimization, so
139 * not entirely sure what I might be missing.
140 *
141 * But scissor optimization is mainly for window managers,
142 * which don't have many vertices (and therefore doesn't
143 * benefit much from binning pass).
144 *
145 * So for now just disable binning if scissor optimization is
146 * used.
147 */
148 if (gmem->minx || gmem->miny)
149 return false;
150
151 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
152 }
153
154 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
155 static void update_vsc_pipe(struct fd_context *ctx);
156 static void
157 emit_binning_workaround(struct fd_context *ctx)
158 {
159 struct fd3_context *fd3_ctx = fd3_context(ctx);
160 struct fd_gmem_stateobj *gmem = &ctx->gmem;
161 struct fd_ringbuffer *ring = ctx->ring;
162 struct fd3_emit emit = {
163 .debug = &ctx->debug,
164 .vtx = &fd3_ctx->solid_vbuf_state,
165 .prog = &ctx->solid_prog,
166 .key = {
167 .half_precision = true,
168 },
169 };
170
171 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
172 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
173 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
174 A3XX_RB_MODE_CONTROL_MRT(0));
175 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
176 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
177 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
178
179 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
180 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
181 A3XX_RB_COPY_CONTROL_MODE(0) |
182 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
183 OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
184 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
185 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
186 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
187 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
188 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
189 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
190
191 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
192 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
193 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
194 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
195
196 fd3_program_emit(ring, &emit, 0, NULL);
197 fd3_emit_vertex_bufs(ring, &emit);
198
199 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
200 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
201 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
202 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
203 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
204 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
205 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
206 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
207 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
208
209 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
210 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
211 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
212
213 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
214 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
215 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
216 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
217
218 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
219 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
220
221 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
222 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
223 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
224 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
225 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
226 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
227 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
228 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
229 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
230
231 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
232 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
233
234 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
235 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
236 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
237 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
238 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
239
240 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
241 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
242 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
243 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
244 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
245
246 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
247 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
248 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
249 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
250 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
251
252 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
253 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
254 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
255 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
256 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
257
258 fd_wfi(ctx, ring);
259 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
260 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
261 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
262 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
263 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
264 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
265 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
266
267 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
268 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
269 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
270 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
271 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
272 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
273
274 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
275 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
276 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
277
278 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
279 OUT_RING(ring, 0x00000000); /* viz query info. */
280 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
281 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
282 OUT_RING(ring, 2); /* NumIndices */
283 OUT_RING(ring, 2);
284 OUT_RING(ring, 1);
285 fd_reset_wfi(ctx);
286
287 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
288 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
289
290 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
291 OUT_RING(ring, 0x00000000);
292
293 fd_wfi(ctx, ring);
294 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
295 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
296 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
297
298 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
299 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
300 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
301 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
302
303 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
304 OUT_RING(ring, 0x00000000);
305 }
306
307 /* transfer from gmem to system memory (ie. normal RAM) */
308
309 static void
310 emit_gmem2mem_surf(struct fd_context *ctx,
311 enum adreno_rb_copy_control_mode mode,
312 bool stencil,
313 uint32_t base, struct pipe_surface *psurf)
314 {
315 struct fd_ringbuffer *ring = ctx->ring;
316 struct fd_resource *rsc = fd_resource(psurf->texture);
317 enum pipe_format format = psurf->format;
318 if (stencil) {
319 rsc = rsc->stencil;
320 format = rsc->base.b.format;
321 }
322 struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
323 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
324 psurf->u.tex.first_layer);
325
326 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
327
328 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
329 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
330 A3XX_RB_COPY_CONTROL_MODE(mode) |
331 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
332 COND(format == PIPE_FORMAT_Z32_FLOAT ||
333 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
334 A3XX_RB_COPY_CONTROL_UNK12));
335
336 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
337 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
338 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
339 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
340 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
341 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
342 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
343
344 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
345 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
346 }
347
348 static void
349 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
350 {
351 struct fd3_context *fd3_ctx = fd3_context(ctx);
352 struct fd_ringbuffer *ring = ctx->ring;
353 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
354 struct fd3_emit emit = {
355 .debug = &ctx->debug,
356 .vtx = &fd3_ctx->solid_vbuf_state,
357 .prog = &ctx->solid_prog,
358 .key = {
359 .half_precision = true,
360 },
361 };
362 int i;
363
364 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
365 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
366
367 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
368 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
369 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
370 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
371 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
372 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
373 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
374 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
375 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
376
377 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
378 OUT_RING(ring, 0xff000000 |
379 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
380 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
381 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
382 OUT_RING(ring, 0xff000000 |
383 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
384 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
385 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
386
387 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
388 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
389
390 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
391 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
392
393 fd_wfi(ctx, ring);
394 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
395 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
396 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
397 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
398 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
399 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
400 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
401
402 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
403 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
404 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
405 A3XX_RB_MODE_CONTROL_MRT(0));
406
407 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
408 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
409 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
410 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
411 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
412
413 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
414 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
415 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
416 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
417
418 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
419 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
420 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
421 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
422 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
423
424 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
425 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
426 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
427 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
428 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
429
430 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
431 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
432 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
433 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
434 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
435
436 fd3_program_emit(ring, &emit, 0, NULL);
437 fd3_emit_vertex_bufs(ring, &emit);
438
439 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
440 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
441 if (!rsc->stencil || ctx->resolve & FD_BUFFER_DEPTH)
442 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, false,
443 ctx->gmem.zsbuf_base[0], pfb->zsbuf);
444 if (rsc->stencil && ctx->resolve & FD_BUFFER_STENCIL)
445 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, true,
446 ctx->gmem.zsbuf_base[1], pfb->zsbuf);
447 }
448
449 if (ctx->resolve & FD_BUFFER_COLOR) {
450 for (i = 0; i < pfb->nr_cbufs; i++) {
451 if (!pfb->cbufs[i])
452 continue;
453 if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
454 continue;
455 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, false,
456 ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
457 }
458 }
459
460 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
461 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
462 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
463 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
464
465 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
466 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
467 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
468 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
469 }
470
471 /* transfer from system memory to gmem */
472
473 static void
474 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t bases[],
475 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
476 {
477 struct fd_ringbuffer *ring = ctx->ring;
478 struct pipe_surface *zsbufs[2];
479
480 assert(bufs > 0);
481
482 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
483 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
484 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
485 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
486
487 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
488
489 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
490 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
491 /* Depth is stored as unorm in gmem, so we have to write it in using a
492 * special blit shader which writes depth.
493 */
494 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
495 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
496 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
497 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
498 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
499 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
500
501 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
502 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
503 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
504 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * ctx->gmem.bin_w));
505
506 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
507 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
508 OUT_RING(ring, 0);
509 } else {
510 /* The gmem_restore_tex logic will put the first buffer's stencil
511 * as color. Supply it with the proper information to make that
512 * happen.
513 */
514 zsbufs[0] = zsbufs[1] = psurf[0];
515 psurf = zsbufs;
516 bufs = 2;
517 }
518 } else {
519 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
520 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
521 }
522
523 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
524
525 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
526 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
527 }
528
529 static void
530 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
531 {
532 struct fd3_context *fd3_ctx = fd3_context(ctx);
533 struct fd_gmem_stateobj *gmem = &ctx->gmem;
534 struct fd_ringbuffer *ring = ctx->ring;
535 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
536 struct fd3_emit emit = {
537 .debug = &ctx->debug,
538 .vtx = &fd3_ctx->blit_vbuf_state,
539 .sprite_coord_enable = 1,
540 /* NOTE: They all use the same VP, this is for vtx bufs. */
541 .prog = &ctx->blit_prog[0],
542 .key = {
543 .half_precision = fd_half_precision(pfb),
544 },
545 };
546 float x0, y0, x1, y1;
547 unsigned bin_w = tile->bin_w;
548 unsigned bin_h = tile->bin_h;
549 unsigned i;
550
551 /* write texture coordinates to vertexbuf: */
552 x0 = ((float)tile->xoff) / ((float)pfb->width);
553 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
554 y0 = ((float)tile->yoff) / ((float)pfb->height);
555 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
556
557 OUT_PKT3(ring, CP_MEM_WRITE, 5);
558 OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
559 OUT_RING(ring, fui(x0));
560 OUT_RING(ring, fui(y0));
561 OUT_RING(ring, fui(x1));
562 OUT_RING(ring, fui(y1));
563
564 fd3_emit_cache_flush(ctx, ring);
565
566 for (i = 0; i < 4; i++) {
567 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
568 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
569 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
570 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
571
572 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
573 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
574 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
575 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
576 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
577 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
578 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
579 }
580
581 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
582 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
583 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
584
585 fd_wfi(ctx, ring);
586 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
587 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
588
589 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
590 OUT_RING(ring, 0);
591 OUT_RING(ring, 0);
592
593 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
594 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
595
596 fd_wfi(ctx, ring);
597 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
598 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
599 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
600 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
601 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
602 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
603 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
604
605 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
606 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
607 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
608 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
609 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
610
611 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
612 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
613 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
614 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
615 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
616
617 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
618 OUT_RING(ring, 0x2 |
619 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
620 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
621 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
622 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
623 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
624 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
625 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
626 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
627
628 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
629 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
630 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
631
632 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
633 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
634 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
635 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
636
637 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
638 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
639 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
640 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
641 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
642
643 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
644 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
645 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
646 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
647 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
648
649 fd3_emit_vertex_bufs(ring, &emit);
650
651 /* for gmem pitch/base calculations, we need to use the non-
652 * truncated tile sizes:
653 */
654 bin_w = gmem->bin_w;
655 bin_h = gmem->bin_h;
656
657 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
658 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
659 emit.fp = NULL; /* frag shader changed so clear cache */
660 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
661 emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
662 }
663
664 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
665 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
666 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
667 /* Non-float can use a regular color write. It's split over 8-bit
668 * components, so half precision is always sufficient.
669 */
670 emit.prog = &ctx->blit_prog[0];
671 emit.key.half_precision = true;
672 } else {
673 /* Float depth needs special blit shader that writes depth */
674 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
675 emit.prog = &ctx->blit_z;
676 else
677 emit.prog = &ctx->blit_zs;
678 emit.key.half_precision = false;
679 }
680 emit.fp = NULL; /* frag shader changed so clear cache */
681 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
682 emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
683 }
684
685 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
686 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
687 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
688 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
689
690 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
691 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
692 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
693 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
694 }
695
696 static void
697 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
698 {
699 unsigned i;
700 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
701 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
702 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
703 }
704 util_dynarray_resize(&ctx->draw_patches, 0);
705 }
706
707 static void
708 patch_rbrc(struct fd_context *ctx, uint32_t val)
709 {
710 struct fd3_context *fd3_ctx = fd3_context(ctx);
711 unsigned i;
712 for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
713 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
714 *patch->cs = patch->val | val;
715 }
716 util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
717 }
718
719 /* for rendering directly to system memory: */
720 static void
721 fd3_emit_sysmem_prep(struct fd_context *ctx)
722 {
723 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
724 struct fd_ringbuffer *ring = ctx->ring;
725 uint32_t i, pitch = 0;
726
727 for (i = 0; i < pfb->nr_cbufs; i++) {
728 struct pipe_surface *psurf = pfb->cbufs[i];
729 if (!psurf)
730 continue;
731 pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
732 }
733
734 fd3_emit_restore(ctx);
735
736 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
737 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
738 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
739
740 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
741
742 /* setup scissor/offset for current tile: */
743 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
744 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
745 A3XX_RB_WINDOW_OFFSET_Y(0));
746
747 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
748 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
749 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
750 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
751 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
752
753 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
754 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
755 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
756 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
757 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
758
759 patch_draws(ctx, IGNORE_VISIBILITY);
760 patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
761 }
762
763 static void
764 update_vsc_pipe(struct fd_context *ctx)
765 {
766 struct fd3_context *fd3_ctx = fd3_context(ctx);
767 struct fd_ringbuffer *ring = ctx->ring;
768 int i;
769
770 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
771 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
772
773 for (i = 0; i < 8; i++) {
774 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
775
776 if (!pipe->bo) {
777 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
778 DRM_FREEDRENO_GEM_TYPE_KMEM);
779 }
780
781 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
782 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
783 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
784 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
785 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
786 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
787 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
788 }
789 }
790
791 static void
792 emit_binning_pass(struct fd_context *ctx)
793 {
794 struct fd_gmem_stateobj *gmem = &ctx->gmem;
795 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
796 struct fd_ringbuffer *ring = ctx->ring;
797 int i;
798
799 uint32_t x1 = gmem->minx;
800 uint32_t y1 = gmem->miny;
801 uint32_t x2 = gmem->minx + gmem->width - 1;
802 uint32_t y2 = gmem->miny + gmem->height - 1;
803
804 if (ctx->screen->gpu_id == 320) {
805 emit_binning_workaround(ctx);
806 fd_wfi(ctx, ring);
807 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
808 OUT_RING(ring, 0x00007fff);
809 }
810
811 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
812 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
813
814 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
815 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
816 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
817 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
818
819 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
820 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
821 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
822
823 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
824 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
825 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
826 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
827
828 /* setup scissor/offset for whole screen: */
829 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
830 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
831 A3XX_RB_WINDOW_OFFSET_Y(y1));
832
833 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
834 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
835
836 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
837 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
838 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
839 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
840 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
841
842 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
843 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
844 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
845 A3XX_RB_MODE_CONTROL_MRT(0));
846
847 for (i = 0; i < 4; i++) {
848 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
849 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
850 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
851 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
852 }
853
854 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
855 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
856 A3XX_PC_VSTREAM_CONTROL_N(0));
857
858 /* emit IB to binning drawcmds: */
859 ctx->emit_ib(ring, ctx->binning_start, ctx->binning_end);
860 fd_reset_wfi(ctx);
861
862 fd_wfi(ctx, ring);
863
864 /* and then put stuff back the way it was: */
865
866 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
867 OUT_RING(ring, 0x00000000);
868
869 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
870 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
871 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
872 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
873 A3XX_SP_SP_CTRL_REG_L0MODE(0));
874
875 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
876 OUT_RING(ring, 0x00000000);
877
878 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
879 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
880 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
881 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
882
883 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
884 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
885 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
886 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
887 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
888 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
889 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
890
891 fd_event_write(ctx, ring, CACHE_FLUSH);
892 fd_wfi(ctx, ring);
893
894 if (ctx->screen->gpu_id == 320) {
895 /* dummy-draw workaround: */
896 OUT_PKT3(ring, CP_DRAW_INDX, 3);
897 OUT_RING(ring, 0x00000000);
898 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
899 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
900 OUT_RING(ring, 0); /* NumIndices */
901 fd_reset_wfi(ctx);
902 }
903
904 OUT_PKT3(ring, CP_NOP, 4);
905 OUT_RING(ring, 0x00000000);
906 OUT_RING(ring, 0x00000000);
907 OUT_RING(ring, 0x00000000);
908 OUT_RING(ring, 0x00000000);
909
910 fd_wfi(ctx, ring);
911
912 if (ctx->screen->gpu_id == 320) {
913 emit_binning_workaround(ctx);
914 }
915 }
916
917 /* before first tile */
918 static void
919 fd3_emit_tile_init(struct fd_context *ctx)
920 {
921 struct fd_ringbuffer *ring = ctx->ring;
922 struct fd_gmem_stateobj *gmem = &ctx->gmem;
923 uint32_t rb_render_control;
924
925 fd3_emit_restore(ctx);
926
927 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
928 * at the right and bottom edge tiles
929 */
930 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
931 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
932 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
933
934 update_vsc_pipe(ctx);
935
936 if (use_hw_binning(ctx)) {
937 /* emit hw binning pass: */
938 emit_binning_pass(ctx);
939
940 patch_draws(ctx, USE_VISIBILITY);
941 } else {
942 patch_draws(ctx, IGNORE_VISIBILITY);
943 }
944
945 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
946 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
947
948 patch_rbrc(ctx, rb_render_control);
949 }
950
951 /* before mem2gmem */
952 static void
953 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
954 {
955 struct fd_ringbuffer *ring = ctx->ring;
956 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
957
958 if (ctx->needs_rb_fbd) {
959 fd_wfi(ctx, ring);
960 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
961 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
962 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
963 ctx->needs_rb_fbd = false;
964 }
965
966 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
967 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
968 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
969 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
970 }
971
972 /* before IB to rendering cmds: */
973 static void
974 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
975 {
976 struct fd3_context *fd3_ctx = fd3_context(ctx);
977 struct fd_ringbuffer *ring = ctx->ring;
978 struct fd_gmem_stateobj *gmem = &ctx->gmem;
979 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
980
981 uint32_t x1 = tile->xoff;
982 uint32_t y1 = tile->yoff;
983 uint32_t x2 = tile->xoff + tile->bin_w - 1;
984 uint32_t y2 = tile->yoff + tile->bin_h - 1;
985
986 uint32_t reg;
987
988 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
989 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
990 if (pfb->zsbuf) {
991 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
992 }
993 OUT_RING(ring, reg);
994 if (pfb->zsbuf) {
995 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
996 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
997 if (rsc->stencil) {
998 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
999 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1000 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
1001 }
1002 } else {
1003 OUT_RING(ring, 0x00000000);
1004 }
1005
1006 if (use_hw_binning(ctx)) {
1007 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
1008
1009 assert(pipe->w * pipe->h);
1010
1011 fd_event_write(ctx, ring, HLSQ_FLUSH);
1012 fd_wfi(ctx, ring);
1013
1014 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1015 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1016 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1017
1018
1019 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1020 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1021 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1022 (tile->p * 4), 0, 0);
1023 } else {
1024 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1025 OUT_RING(ring, 0x00000000);
1026 }
1027
1028 OUT_PKT3(ring, CP_SET_BIN, 3);
1029 OUT_RING(ring, 0x00000000);
1030 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1031 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1032
1033 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1034
1035 /* setup scissor/offset for current tile: */
1036 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1037 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1038 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1039
1040 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1041 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1042 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1043 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1044 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1045 }
1046
1047 void
1048 fd3_gmem_init(struct pipe_context *pctx)
1049 {
1050 struct fd_context *ctx = fd_context(pctx);
1051
1052 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1053 ctx->emit_tile_init = fd3_emit_tile_init;
1054 ctx->emit_tile_prep = fd3_emit_tile_prep;
1055 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1056 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1057 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1058 }