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8519a90ccfa2b58c1d692cee804ff948deff0285
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_util.h"
44 #include "fd3_zsa.h"
45
46 static const struct fd3_shader_key key = {
47 // XXX should set this based on render target format! We don't
48 // want half_precision if float32 render target!!!
49 .half_precision = true,
50 };
51
52 static void
53 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
54 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
55 {
56 enum a3xx_tile_mode tile_mode;
57 unsigned i;
58
59 if (bin_w) {
60 tile_mode = TILE_32X32;
61 } else {
62 tile_mode = LINEAR;
63 }
64
65 for (i = 0; i < 4; i++) {
66 enum a3xx_color_fmt format = 0;
67 enum a3xx_color_swap swap = WZYX;
68 struct fd_resource *rsc = NULL;
69 struct fd_resource_slice *slice = NULL;
70 uint32_t stride = 0;
71 uint32_t base = 0;
72
73 if ((i < nr_bufs) && bufs[i]) {
74 struct pipe_surface *psurf = bufs[i];
75
76 rsc = fd_resource(psurf->texture);
77 slice = &rsc->slices[psurf->u.tex.level];
78 format = fd3_pipe2color(psurf->format);
79 swap = fd3_pipe2swap(psurf->format);
80
81 if (bin_w) {
82 stride = bin_w * rsc->cpp;
83
84 if (bases) {
85 base = bases[i];
86 }
87 } else {
88 stride = slice->pitch * rsc->cpp;
89 }
90 }
91
92 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
93 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
94 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
95 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
96 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
97 if (bin_w || (i >= nr_bufs)) {
98 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
99 } else {
100 OUT_RELOCW(ring, rsc->bo, slice->offset, 0, -1);
101 }
102
103 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
104 OUT_RING(ring, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format));
105 }
106 }
107
108 static uint32_t
109 depth_base(struct fd_context *ctx)
110 {
111 struct fd_gmem_stateobj *gmem = &ctx->gmem;
112 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
113 uint32_t cpp = 4;
114 if (pfb->cbufs[0]) {
115 struct fd_resource *rsc =
116 fd_resource(pfb->cbufs[0]->texture);
117 cpp = rsc->cpp;
118 }
119 return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
120 }
121
122 static bool
123 use_hw_binning(struct fd_context *ctx)
124 {
125 struct fd_gmem_stateobj *gmem = &ctx->gmem;
126
127 /* workaround: combining scissor optimization and hw binning
128 * seems problematic. Seems like we end up with a mismatch
129 * between binning pass and rendering pass, wrt. where the hw
130 * thinks the vertices belong. And the blob driver doesn't
131 * seem to implement anything like scissor optimization, so
132 * not entirely sure what I might be missing.
133 *
134 * But scissor optimization is mainly for window managers,
135 * which don't have many vertices (and therefore doesn't
136 * benefit much from binning pass).
137 *
138 * So for now just disable binning if scissor optimization is
139 * used.
140 */
141 if (gmem->minx || gmem->miny)
142 return false;
143
144 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
145 }
146
147 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
148 static void update_vsc_pipe(struct fd_context *ctx);
149 static void
150 emit_binning_workaround(struct fd_context *ctx)
151 {
152 struct fd3_context *fd3_ctx = fd3_context(ctx);
153 struct fd_gmem_stateobj *gmem = &ctx->gmem;
154 struct fd_ringbuffer *ring = ctx->ring;
155
156 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
157 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
158 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
159 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
160 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
161 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
162
163 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
164 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
165 A3XX_RB_COPY_CONTROL_MODE(0) |
166 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
167 OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
168 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
169 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
170 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
171 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
172 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
173 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
174
175 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
176 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
177 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
178 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
179
180 fd3_program_emit(ring, &ctx->solid_prog, key);
181 fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
182 (struct fd3_vertex_buf[]) {{
183 .prsc = fd3_ctx->solid_vbuf,
184 .stride = 12,
185 .format = PIPE_FORMAT_R32G32B32_FLOAT,
186 }}, 1);
187
188 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
189 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
190 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
191 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
192 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
193 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
194 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
195 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
196 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
197
198 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
199 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
200 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
201
202 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
203 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
204 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
205 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
206
207 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
208 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
209
210 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
211 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
212 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
213 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
214 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
215 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
216 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
217 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
218 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
219
220 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
221 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
222
223 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
224 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
225 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
226 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
227 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
228
229 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
230 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
231 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
232 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
233 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
234
235 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
236 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
237 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
238 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
239 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
240
241 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
242 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
243 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
244 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
245 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
246
247 fd_wfi(ctx, ring);
248 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
249 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
250 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
251 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
252 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
253 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
254 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
255
256 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
257 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
258 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
259 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
260 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
261 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
262
263 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
264 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
265 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
266
267 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
268 OUT_RING(ring, 0x00000000); /* viz query info. */
269 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
270 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY));
271 OUT_RING(ring, 2); /* NumIndices */
272 OUT_RING(ring, 2);
273 OUT_RING(ring, 1);
274 fd_reset_wfi(ctx);
275
276 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
277 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
278
279 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
280 OUT_RING(ring, 0x00000000);
281
282 fd_wfi(ctx, ring);
283 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
284 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
285 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
286
287 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
288 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
289 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
290 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
291
292 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
293 OUT_RING(ring, 0x00000000);
294 }
295
296 /* transfer from gmem to system memory (ie. normal RAM) */
297
298 static void
299 emit_gmem2mem_surf(struct fd_context *ctx,
300 enum adreno_rb_copy_control_mode mode,
301 uint32_t base, struct pipe_surface *psurf)
302 {
303 struct fd_ringbuffer *ring = ctx->ring;
304 struct fd_resource *rsc = fd_resource(psurf->texture);
305 struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
306
307 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
308 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
309 A3XX_RB_COPY_CONTROL_MODE(mode) |
310 A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
311 OUT_RELOCW(ring, rsc->bo, slice->offset, 0, -1); /* RB_COPY_DEST_BASE */
312 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
313 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
314 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
315 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
316 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
317 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf->format)));
318
319 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
320 DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
321 }
322
323 static void
324 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
325 {
326 struct fd3_context *fd3_ctx = fd3_context(ctx);
327 struct fd_ringbuffer *ring = ctx->ring;
328 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
329
330 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
331 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
332
333 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
334 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
335 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
336 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
337 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
338 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
339 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
340 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
341 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
342
343 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
344 OUT_RING(ring, 0xff000000 |
345 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
346 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
347 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
348 OUT_RING(ring, 0xff000000 |
349 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
350 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
351 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
352
353 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
354 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
355
356 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
357 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
358
359 fd_wfi(ctx, ring);
360 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
361 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
362 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
363 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
364 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
365 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
366 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
367
368 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
369 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
370 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
371
372 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
373 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
374 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
375 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
376 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
377
378 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
379 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
380 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
381 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
382
383 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
384 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
385 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
386 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
387 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
388
389 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
390 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
391 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
392 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
393 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
394
395 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
396 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
397 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
398 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
399 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
400
401 fd3_program_emit(ring, &ctx->solid_prog, key);
402 fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
403 (struct fd3_vertex_buf[]) {{
404 .prsc = fd3_ctx->solid_vbuf,
405 .stride = 12,
406 .format = PIPE_FORMAT_R32G32B32_FLOAT,
407 }}, 1);
408
409 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
410 uint32_t base = depth_base(ctx);
411 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
412 }
413
414 if (ctx->resolve & FD_BUFFER_COLOR) {
415 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, 0, pfb->cbufs[0]);
416 }
417
418 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
419 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
420 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
421
422 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
423 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
424 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
425 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
426 }
427
428 /* transfer from system memory to gmem */
429
430 static void
431 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
432 struct pipe_surface *psurf, uint32_t bin_w)
433 {
434 struct fd_ringbuffer *ring = ctx->ring;
435
436 emit_mrt(ring, 1, &psurf, &base, bin_w);
437
438 fd3_emit_gmem_restore_tex(ring, psurf);
439
440 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
441 DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
442 }
443
444 static void
445 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
446 {
447 struct fd3_context *fd3_ctx = fd3_context(ctx);
448 struct fd_gmem_stateobj *gmem = &ctx->gmem;
449 struct fd_ringbuffer *ring = ctx->ring;
450 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
451 float x0, y0, x1, y1;
452 unsigned bin_w = tile->bin_w;
453 unsigned bin_h = tile->bin_h;
454 unsigned i;
455
456 /* write texture coordinates to vertexbuf: */
457 x0 = ((float)tile->xoff) / ((float)pfb->width);
458 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
459 y0 = ((float)tile->yoff) / ((float)pfb->height);
460 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
461
462 OUT_PKT3(ring, CP_MEM_WRITE, 5);
463 OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
464 OUT_RING(ring, fui(x0));
465 OUT_RING(ring, fui(y0));
466 OUT_RING(ring, fui(x1));
467 OUT_RING(ring, fui(y1));
468
469 for (i = 0; i < 4; i++) {
470 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
471 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
472 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
473 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
474
475 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
476 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
477 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
478 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
479 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
480 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
481 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
482 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
483 }
484
485 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
486 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
487 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
488
489 fd_wfi(ctx, ring);
490 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
491 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
492
493 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
494 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
495
496 fd_wfi(ctx, ring);
497 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
498 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
499 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
500 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
501 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
502 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
503 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
504
505 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
506 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
507 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
508 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
509 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
510
511 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
512 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
513 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
514 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
515 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
516
517 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
518 OUT_RING(ring, 0x2 |
519 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
520 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
521 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
522 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
523 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
524 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
525 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
526 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
527
528 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
529 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
530 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
531 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
532
533 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
534 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
535 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
536 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
537 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
538
539 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
540 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
541 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
542 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
543 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
544
545 fd3_program_emit(ring, &ctx->blit_prog, key);
546 fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->blit_prog.vp, key),
547 (struct fd3_vertex_buf[]) {{
548 .prsc = fd3_ctx->blit_texcoord_vbuf,
549 .stride = 8,
550 .format = PIPE_FORMAT_R32G32_FLOAT,
551 }, {
552 .prsc = fd3_ctx->solid_vbuf,
553 .stride = 12,
554 .format = PIPE_FORMAT_R32G32B32_FLOAT,
555 }}, 2);
556
557 /* for gmem pitch/base calculations, we need to use the non-
558 * truncated tile sizes:
559 */
560 bin_w = gmem->bin_w;
561 bin_h = gmem->bin_h;
562
563 if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
564 emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
565
566 if (ctx->restore & FD_BUFFER_COLOR)
567 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
568
569 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
570 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
571 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
572 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
573 }
574
575 static void
576 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
577 {
578 unsigned i;
579 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
580 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
581 *patch->cs = patch->val | DRAW(0, 0, 0, vismode);
582 }
583 util_dynarray_resize(&ctx->draw_patches, 0);
584 }
585
586 static void
587 patch_rbrc(struct fd_context *ctx, uint32_t val)
588 {
589 struct fd3_context *fd3_ctx = fd3_context(ctx);
590 unsigned i;
591 for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
592 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
593 *patch->cs = patch->val | val;
594 }
595 util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
596 }
597
598 /* for rendering directly to system memory: */
599 static void
600 fd3_emit_sysmem_prep(struct fd_context *ctx)
601 {
602 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
603 struct fd_ringbuffer *ring = ctx->ring;
604 uint32_t pitch = 0;
605
606 if (pfb->cbufs[0])
607 pitch = fd_resource(pfb->cbufs[0]->texture)->slices[0].pitch;
608
609 fd3_emit_restore(ctx);
610
611 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
612 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
613 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
614
615 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
616
617 /* setup scissor/offset for current tile: */
618 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
619 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
620 A3XX_RB_WINDOW_OFFSET_Y(0));
621
622 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
623 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
624 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
625 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
626 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
627
628 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
629 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
630 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
631 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
632
633 patch_draws(ctx, IGNORE_VISIBILITY);
634 patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
635 }
636
637 static void
638 update_vsc_pipe(struct fd_context *ctx)
639 {
640 struct fd3_context *fd3_ctx = fd3_context(ctx);
641 struct fd_ringbuffer *ring = ctx->ring;
642 int i;
643
644 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
645 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
646
647 for (i = 0; i < 8; i++) {
648 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
649
650 if (!pipe->bo) {
651 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
652 DRM_FREEDRENO_GEM_TYPE_KMEM);
653 }
654
655 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
656 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
657 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
658 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
659 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
660 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
661 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
662 }
663 }
664
665 static void
666 emit_binning_pass(struct fd_context *ctx)
667 {
668 struct fd_gmem_stateobj *gmem = &ctx->gmem;
669 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
670 struct fd_ringbuffer *ring = ctx->ring;
671 int i;
672
673 uint32_t x1 = gmem->minx;
674 uint32_t y1 = gmem->miny;
675 uint32_t x2 = gmem->minx + gmem->width - 1;
676 uint32_t y2 = gmem->miny + gmem->height - 1;
677
678 if (ctx->screen->gpu_id == 320) {
679 emit_binning_workaround(ctx);
680 fd_wfi(ctx, ring);
681 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
682 OUT_RING(ring, 0x00007fff);
683 }
684
685 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
686 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
687
688 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
689 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
690 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
691 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
692
693 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
694 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
695 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
696
697 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
698 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
699 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
700 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
701
702 /* setup scissor/offset for whole screen: */
703 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
704 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
705 A3XX_RB_WINDOW_OFFSET_Y(y1));
706
707 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
708 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
709
710 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
711 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
712 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
713 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
714 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
715
716 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
717 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
718 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
719
720 for (i = 0; i < 4; i++) {
721 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
722 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
723 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
724 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
725 }
726
727 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
728 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
729 A3XX_PC_VSTREAM_CONTROL_N(0));
730
731 /* emit IB to binning drawcmds: */
732 OUT_IB(ring, ctx->binning_start, ctx->binning_end);
733 fd_reset_wfi(ctx);
734
735 fd_wfi(ctx, ring);
736
737 /* and then put stuff back the way it was: */
738
739 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
740 OUT_RING(ring, 0x00000000);
741
742 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
743 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
744 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
745 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
746 A3XX_SP_SP_CTRL_REG_L0MODE(0));
747
748 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
749 OUT_RING(ring, 0x00000000);
750
751 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
752 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
753 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
754 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
755
756 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
757 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
758 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
759 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
760 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
761 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
762
763 fd_event_write(ctx, ring, CACHE_FLUSH);
764 fd_wfi(ctx, ring);
765
766 if (ctx->screen->gpu_id == 320) {
767 /* dummy-draw workaround: */
768 OUT_PKT3(ring, CP_DRAW_INDX, 3);
769 OUT_RING(ring, 0x00000000);
770 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
771 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
772 OUT_RING(ring, 0); /* NumIndices */
773 fd_reset_wfi(ctx);
774 }
775
776 OUT_PKT3(ring, CP_NOP, 4);
777 OUT_RING(ring, 0x00000000);
778 OUT_RING(ring, 0x00000000);
779 OUT_RING(ring, 0x00000000);
780 OUT_RING(ring, 0x00000000);
781
782 fd_wfi(ctx, ring);
783
784 if (ctx->screen->gpu_id == 320) {
785 emit_binning_workaround(ctx);
786 }
787 }
788
789 /* before first tile */
790 static void
791 fd3_emit_tile_init(struct fd_context *ctx)
792 {
793 struct fd_ringbuffer *ring = ctx->ring;
794 struct fd_gmem_stateobj *gmem = &ctx->gmem;
795 uint32_t rb_render_control;
796
797 fd3_emit_restore(ctx);
798
799 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
800 * at the right and bottom edge tiles
801 */
802 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
803 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
804 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
805
806 update_vsc_pipe(ctx);
807
808 if (use_hw_binning(ctx)) {
809 /* mark the end of the binning cmds: */
810 fd_ringmarker_mark(ctx->binning_end);
811
812 /* emit hw binning pass: */
813 emit_binning_pass(ctx);
814
815 patch_draws(ctx, USE_VISIBILITY);
816 } else {
817 patch_draws(ctx, IGNORE_VISIBILITY);
818 }
819
820 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
821 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
822
823 patch_rbrc(ctx, rb_render_control);
824 }
825
826 /* before mem2gmem */
827 static void
828 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
829 {
830 struct fd_ringbuffer *ring = ctx->ring;
831 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
832 struct fd_gmem_stateobj *gmem = &ctx->gmem;
833 uint32_t reg;
834
835 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
836 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
837 if (pfb->zsbuf) {
838 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
839 }
840 OUT_RING(ring, reg);
841 if (pfb->zsbuf) {
842 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
843 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
844 } else {
845 OUT_RING(ring, 0x00000000);
846 }
847
848 if (ctx->needs_rb_fbd) {
849 fd_wfi(ctx, ring);
850 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
851 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
852 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
853 ctx->needs_rb_fbd = false;
854 }
855
856 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
857 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
858 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
859 }
860
861 /* before IB to rendering cmds: */
862 static void
863 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
864 {
865 struct fd3_context *fd3_ctx = fd3_context(ctx);
866 struct fd_ringbuffer *ring = ctx->ring;
867 struct fd_gmem_stateobj *gmem = &ctx->gmem;
868 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
869
870 uint32_t x1 = tile->xoff;
871 uint32_t y1 = tile->yoff;
872 uint32_t x2 = tile->xoff + tile->bin_w - 1;
873 uint32_t y2 = tile->yoff + tile->bin_h - 1;
874
875 if (use_hw_binning(ctx)) {
876 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
877
878 assert(pipe->w * pipe->h);
879
880 fd_event_write(ctx, ring, HLSQ_FLUSH);
881 fd_wfi(ctx, ring);
882
883 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
884 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
885 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
886
887
888 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
889 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
890 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
891 (tile->p * 4), 0, 0);
892 } else {
893 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
894 OUT_RING(ring, 0x00000000);
895 }
896
897 OUT_PKT3(ring, CP_SET_BIN, 3);
898 OUT_RING(ring, 0x00000000);
899 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
900 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
901
902 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
903
904 /* setup scissor/offset for current tile: */
905 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
906 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
907 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
908
909 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
910 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
911 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
912 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
913 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
914 }
915
916 void
917 fd3_gmem_init(struct pipe_context *pctx)
918 {
919 struct fd_context *ctx = fd_context(pctx);
920
921 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
922 ctx->emit_tile_init = fd3_emit_tile_init;
923 ctx->emit_tile_prep = fd3_emit_tile_prep;
924 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
925 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
926 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
927 }