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a08b482fafb919e1ff89bd6c509d3eadadb42506
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_util.h"
44 #include "fd3_zsa.h"
45
46
47 static void
48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
49 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
50 {
51 enum a3xx_tile_mode tile_mode;
52 unsigned i;
53
54 if (bin_w) {
55 tile_mode = TILE_32X32;
56 } else {
57 tile_mode = LINEAR;
58 }
59
60 for (i = 0; i < 4; i++) {
61 enum a3xx_color_fmt format = 0;
62 enum a3xx_color_swap swap = WZYX;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t base = 0;
67
68 if (i < nr_bufs) {
69 struct pipe_surface *psurf = bufs[i];
70
71 rsc = fd_resource(psurf->texture);
72 slice = &rsc->slices[psurf->u.tex.level];
73 format = fd3_pipe2color(psurf->format);
74 swap = fd3_pipe2swap(psurf->format);
75
76 if (bin_w) {
77 stride = bin_w * rsc->cpp;
78
79 if (bases) {
80 base = bases[i] * rsc->cpp;
81 }
82 } else {
83 stride = slice->pitch * rsc->cpp;
84 }
85 }
86
87 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
88 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
89 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
90 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
91 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
92 if (bin_w || (i >= nr_bufs)) {
93 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
94 } else {
95 OUT_RELOCW(ring, rsc->bo, slice->offset, 0, -1);
96 }
97
98 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
99 OUT_RING(ring, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format));
100 }
101 }
102
103 static uint32_t
104 depth_base(struct fd_gmem_stateobj *gmem)
105 {
106 return align(gmem->bin_w * gmem->bin_h, 0x4000);
107 }
108
109 static bool
110 use_hw_binning(struct fd_context *ctx)
111 {
112 struct fd_gmem_stateobj *gmem = &ctx->gmem;
113 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
114 }
115
116 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
117 static void update_vsc_pipe(struct fd_context *ctx);
118 static void
119 emit_binning_workaround(struct fd_context *ctx)
120 {
121 struct fd3_context *fd3_ctx = fd3_context(ctx);
122 struct fd_gmem_stateobj *gmem = &ctx->gmem;
123 struct fd_ringbuffer *ring = ctx->ring;
124
125 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
126 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
127 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
128 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
129 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
130 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
131
132 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
133 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
134 A3XX_RB_COPY_CONTROL_MODE(0) |
135 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
136 OUT_RELOC(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
137 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
138 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
139 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
140 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
141 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
142 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
143
144 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
145 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
146 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
147 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
148
149 fd3_program_emit(ring, &ctx->solid_prog, false);
150
151 fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
152 { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
153 }, 1);
154
155 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
156 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
157 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
158 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
159 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
160 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
161 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
162 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
163 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
164
165 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
166 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
167 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
168
169 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
170 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
171 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
172 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
173
174 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
175 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
176
177 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
178 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
179 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
180 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
181 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
182 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
183 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
184 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
185 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
186
187 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
188 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
189
190 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
191 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
192 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
193 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
194 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
195
196 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
197 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
198 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
199 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
200 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
201
202 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
203 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
204 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
205 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
206 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
207
208 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
209 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
210 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
211 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
212 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
213
214 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
215 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
216 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
217 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
218 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
219 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
220 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
221
222 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
223 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
224 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
225 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
226 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
227 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
228
229 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
230 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
231 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
232
233 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
234 OUT_RING(ring, 0x00000000); /* viz query info. */
235 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
236 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY));
237 OUT_RING(ring, 2); /* NumIndices */
238 OUT_RING(ring, 2);
239 OUT_RING(ring, 1);
240
241 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
242 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
243
244 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
245 OUT_RING(ring, 0x00000000);
246
247 OUT_WFI(ring);
248
249 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
250 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
251 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
252
253 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
254 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
255 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
256 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
257
258 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
259 OUT_RING(ring, 0x00000000);
260 }
261
262 /* transfer from gmem to system memory (ie. normal RAM) */
263
264 static void
265 emit_gmem2mem_surf(struct fd_context *ctx,
266 enum adreno_rb_copy_control_mode mode,
267 uint32_t base, struct pipe_surface *psurf)
268 {
269 struct fd_ringbuffer *ring = ctx->ring;
270 struct fd_resource *rsc = fd_resource(psurf->texture);
271 struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
272
273 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
274 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
275 A3XX_RB_COPY_CONTROL_MODE(mode) |
276 A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
277 OUT_RELOCW(ring, rsc->bo, slice->offset, 0, -1); /* RB_COPY_DEST_BASE */
278 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
279 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
280 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
281 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
282 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
283 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf->format)));
284
285 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
286 DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
287 }
288
289 static void
290 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
291 {
292 struct fd3_context *fd3_ctx = fd3_context(ctx);
293 struct fd_ringbuffer *ring = ctx->ring;
294 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
295
296 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
297 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
298
299 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
300 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
301 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
302 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
303 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
304 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
305 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
306 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
307 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
308
309 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
310 OUT_RING(ring, 0xff000000 |
311 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
312 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
313 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
314 OUT_RING(ring, 0xff000000 |
315 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
316 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
317 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
318
319 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
320 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
321
322 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
323 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
324
325 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
326 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
327 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
328 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
329 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
330 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
331 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
332
333 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
334 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
335 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
336
337 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
338 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
339 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
340 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
341 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
342
343 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
344 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
345 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
346 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
347
348 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
349 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
350 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
351 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
352 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
353
354 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
355 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
356 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
357 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
358 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
359
360 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
361 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
362 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
363 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
364 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
365
366 fd3_program_emit(ring, &ctx->solid_prog, false);
367
368 fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
369 { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
370 }, 1);
371
372 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
373 uint32_t base = 0;
374 if (pfb->cbufs[0]) {
375 struct fd_resource *rsc =
376 fd_resource(pfb->cbufs[0]->texture);
377 base = depth_base(&ctx->gmem) * rsc->cpp;
378 }
379 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
380 }
381
382 if (ctx->resolve & FD_BUFFER_COLOR) {
383 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, 0, pfb->cbufs[0]);
384 }
385
386 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
387 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
388 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
389
390 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
391 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
392 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
393 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
394 }
395
396 /* transfer from system memory to gmem */
397
398 static void
399 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
400 struct pipe_surface *psurf, uint32_t bin_w)
401 {
402 struct fd_ringbuffer *ring = ctx->ring;
403
404 emit_mrt(ring, 1, &psurf, &base, bin_w);
405
406 fd3_emit_gmem_restore_tex(ring, psurf);
407
408 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
409 DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
410 }
411
412 static void
413 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
414 {
415 struct fd3_context *fd3_ctx = fd3_context(ctx);
416 struct fd_gmem_stateobj *gmem = &ctx->gmem;
417 struct fd_ringbuffer *ring = ctx->ring;
418 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
419 float x0, y0, x1, y1;
420 unsigned bin_w = tile->bin_w;
421 unsigned bin_h = tile->bin_h;
422 unsigned i;
423
424 /* write texture coordinates to vertexbuf: */
425 x0 = ((float)tile->xoff) / ((float)pfb->width);
426 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
427 y0 = ((float)tile->yoff) / ((float)pfb->height);
428 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
429
430 OUT_PKT3(ring, CP_MEM_WRITE, 5);
431 OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
432 OUT_RING(ring, fui(x0));
433 OUT_RING(ring, fui(y0));
434 OUT_RING(ring, fui(x1));
435 OUT_RING(ring, fui(y1));
436
437 for (i = 0; i < 4; i++) {
438 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
439 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(12) |
440 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
441 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
442
443 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
444 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
445 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
446 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
447 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
448 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
449 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
450 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
451 }
452
453 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
454 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
455 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
456
457 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
458 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
459
460 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
461 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
462
463 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
464 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
465 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
466 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
467 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
468 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
469 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
470
471 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
472 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
473 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
474 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
475 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
476
477 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
478 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
479 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
480 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
481 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
482
483 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
484 OUT_RING(ring, 0x2 |
485 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
486 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
487 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
488 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
489 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
490 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
491 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
492 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
493
494 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
495 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
496 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
497 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
498
499 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
500 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
501 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
502 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
503 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
504
505 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
506 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
507 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
508 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
509 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
510
511 fd3_program_emit(ring, &ctx->blit_prog, false);
512
513 fd3_emit_vertex_bufs(ring, &ctx->blit_prog, (struct fd3_vertex_buf[]) {
514 { .prsc = fd3_ctx->blit_texcoord_vbuf, .stride = 8, .format = PIPE_FORMAT_R32G32_FLOAT },
515 { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
516 }, 2);
517
518 /* for gmem pitch/base calculations, we need to use the non-
519 * truncated tile sizes:
520 */
521 bin_w = gmem->bin_w;
522 bin_h = gmem->bin_h;
523
524 if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
525 emit_mem2gmem_surf(ctx, depth_base(gmem), pfb->zsbuf, bin_w);
526
527 if (ctx->restore & FD_BUFFER_COLOR)
528 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
529
530 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
531 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
532 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
533 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
534 }
535
536 static void
537 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
538 {
539 unsigned i;
540 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
541 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
542 *patch->cs = patch->val | DRAW(0, 0, 0, vismode);
543 }
544 util_dynarray_resize(&ctx->draw_patches, 0);
545 }
546
547 static void
548 patch_rbrc(struct fd_context *ctx, uint32_t val)
549 {
550 struct fd3_context *fd3_ctx = fd3_context(ctx);
551 unsigned i;
552 for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
553 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
554 *patch->cs = patch->val | val;
555 }
556 util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
557 }
558
559 /* for rendering directly to system memory: */
560 static void
561 fd3_emit_sysmem_prep(struct fd_context *ctx)
562 {
563 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
564 struct fd_ringbuffer *ring = ctx->ring;
565 uint32_t pitch = 0;
566
567 if (pfb->cbufs[0])
568 pitch = fd_resource(pfb->cbufs[0]->texture)->slices[0].pitch;
569
570 fd3_emit_restore(ctx);
571
572 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
573 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
574 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
575
576 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
577
578 /* setup scissor/offset for current tile: */
579 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
580 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
581 A3XX_RB_WINDOW_OFFSET_Y(0));
582
583 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
584 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
585 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
586 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
587 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
588
589 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
590 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
591 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
592 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
593
594 patch_draws(ctx, IGNORE_VISIBILITY);
595 patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
596 }
597
598 static void
599 update_vsc_pipe(struct fd_context *ctx)
600 {
601 struct fd3_context *fd3_ctx = fd3_context(ctx);
602 struct fd_ringbuffer *ring = ctx->ring;
603 int i;
604
605 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
606 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
607
608 for (i = 0; i < 8; i++) {
609 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
610
611 if (!pipe->bo) {
612 pipe->bo = fd_bo_new(ctx->screen->dev, 0x40000,
613 DRM_FREEDRENO_GEM_TYPE_KMEM);
614 }
615
616 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
617 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
618 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
619 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
620 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
621 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
622 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
623 }
624 }
625
626 static void
627 emit_binning_pass(struct fd_context *ctx)
628 {
629 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
630 struct fd_ringbuffer *ring = ctx->ring;
631 int i;
632
633 if (ctx->screen->gpu_id == 320) {
634 emit_binning_workaround(ctx);
635
636 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
637 OUT_RING(ring, 0x00007fff);
638 }
639
640 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
641 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
642
643 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
644 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
645 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
646 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
647
648 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
649 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
650 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
651
652 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
653 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
654 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
655 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
656
657 /* setup scissor/offset for whole screen: */
658 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
659 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
660 A3XX_RB_WINDOW_OFFSET_Y(0));
661
662 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
663 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
664
665 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
666 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
667 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
668 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
669 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
670
671 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
672 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
673 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
674
675 for (i = 0; i < 4; i++) {
676 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
677 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(0) |
678 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
679 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
680 }
681
682 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
683 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
684 A3XX_PC_VSTREAM_CONTROL_N(0));
685
686 /* emit IB to binning drawcmds: */
687 OUT_IB(ring, ctx->binning_start, ctx->binning_end);
688
689 /* and then put stuff back the way it was: */
690
691 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
692 OUT_RING(ring, 0x00000000);
693
694 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
695 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
696 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
697 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
698 A3XX_SP_SP_CTRL_REG_L0MODE(0));
699
700 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
701 OUT_RING(ring, 0x00000000);
702
703 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
704 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
705 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
706 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
707
708 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
709 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
710 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
711 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
712 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
713 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
714
715 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
716 OUT_RING(ring, CACHE_FLUSH);
717
718 if (ctx->screen->gpu_id == 320) {
719 /* dummy-draw workaround: */
720 OUT_PKT3(ring, CP_DRAW_INDX, 3);
721 OUT_RING(ring, 0x00000000);
722 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
723 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
724 OUT_RING(ring, 0); /* NumIndices */
725 }
726
727 OUT_PKT3(ring, CP_NOP, 4);
728 OUT_RING(ring, 0x00000000);
729 OUT_RING(ring, 0x00000000);
730 OUT_RING(ring, 0x00000000);
731 OUT_RING(ring, 0x00000000);
732
733 OUT_WFI(ring);
734
735 if (ctx->screen->gpu_id == 320) {
736 emit_binning_workaround(ctx);
737 }
738 }
739
740 /* before first tile */
741 static void
742 fd3_emit_tile_init(struct fd_context *ctx)
743 {
744 struct fd_ringbuffer *ring = ctx->ring;
745 struct fd_gmem_stateobj *gmem = &ctx->gmem;
746
747 fd3_emit_restore(ctx);
748
749 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
750 * at the right and bottom edge tiles
751 */
752 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
753 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
754 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
755
756 update_vsc_pipe(ctx);
757
758 if (use_hw_binning(ctx)) {
759 /* mark the end of the binning cmds: */
760 fd_ringmarker_mark(ctx->binning_end);
761
762 /* emit hw binning pass: */
763 emit_binning_pass(ctx);
764
765 patch_draws(ctx, USE_VISIBILITY);
766 } else {
767 patch_draws(ctx, IGNORE_VISIBILITY);
768 }
769
770 patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
771 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
772 }
773
774 /* before mem2gmem */
775 static void
776 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
777 {
778 struct fd_ringbuffer *ring = ctx->ring;
779 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
780 struct fd_gmem_stateobj *gmem = &ctx->gmem;
781 uint32_t reg;
782
783 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
784 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(gmem));
785 if (pfb->zsbuf) {
786 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
787 }
788 OUT_RING(ring, reg);
789 if (pfb->zsbuf) {
790 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
791 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
792 } else {
793 OUT_RING(ring, 0x00000000);
794 }
795
796 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
797 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
798 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
799
800 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
801 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
802 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
803 }
804
805 /* before IB to rendering cmds: */
806 static void
807 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
808 {
809 struct fd3_context *fd3_ctx = fd3_context(ctx);
810 struct fd_ringbuffer *ring = ctx->ring;
811 struct fd_gmem_stateobj *gmem = &ctx->gmem;
812 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
813
814 uint32_t x1 = tile->xoff;
815 uint32_t y1 = tile->yoff;
816 uint32_t x2 = tile->xoff + tile->bin_w - 1;
817 uint32_t y2 = tile->yoff + tile->bin_h - 1;
818
819 if (use_hw_binning(ctx)) {
820 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
821
822 assert(pipe->w * pipe->h);
823
824 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
825 OUT_RING(ring, HLSQ_FLUSH);
826
827 OUT_WFI(ring);
828
829 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
830 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
831 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
832
833 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
834 OUT_RING(ring, CACHE_FLUSH);
835
836 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
837 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
838 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
839 (tile->p * 4), 0, 0);
840 } else {
841 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
842 OUT_RING(ring, 0x00000000);
843 }
844
845 OUT_PKT3(ring, CP_SET_BIN, 3);
846 OUT_RING(ring, 0x00000000);
847 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
848 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
849
850 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
851
852 /* setup scissor/offset for current tile: */
853 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
854 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
855 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
856
857 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
858 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
859 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
860 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
861 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
862 }
863
864 void
865 fd3_gmem_init(struct pipe_context *pctx)
866 {
867 struct fd_context *ctx = fd_context(pctx);
868
869 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
870 ctx->emit_tile_init = fd3_emit_tile_init;
871 ctx->emit_tile_prep = fd3_emit_tile_prep;
872 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
873 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
874 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
875 }