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freedreno: Make the slice pitch be bytes, not pixels.
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd3_gmem.h"
38 #include "fd3_context.h"
39 #include "fd3_emit.h"
40 #include "fd3_program.h"
41 #include "fd3_format.h"
42 #include "fd3_zsa.h"
43
44 static void
45 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
46 struct pipe_surface **bufs, const uint32_t *bases, uint32_t bin_w,
47 bool decode_srgb)
48 {
49 enum a3xx_tile_mode tile_mode;
50 unsigned i;
51
52 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
53 enum pipe_format pformat = 0;
54 enum a3xx_color_fmt format = 0;
55 enum a3xx_color_swap swap = WZYX;
56 bool srgb = false;
57 struct fd_resource *rsc = NULL;
58 struct fdl_slice *slice = NULL;
59 uint32_t stride = 0;
60 uint32_t base = 0;
61 uint32_t offset = 0;
62
63 if (bin_w) {
64 tile_mode = TILE_32X32;
65 } else {
66 tile_mode = LINEAR;
67 }
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71
72 rsc = fd_resource(psurf->texture);
73 pformat = psurf->format;
74 /* In case we're drawing to Z32F_S8, the "color" actually goes to
75 * the stencil
76 */
77 if (rsc->stencil) {
78 rsc = rsc->stencil;
79 pformat = rsc->base.format;
80 if (bases)
81 bases++;
82 }
83 slice = fd_resource_slice(rsc, psurf->u.tex.level);
84 format = fd3_pipe2color(pformat);
85 if (decode_srgb)
86 srgb = util_format_is_srgb(pformat);
87 else
88 pformat = util_format_linear(pformat);
89
90 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
91
92 offset = fd_resource_offset(rsc, psurf->u.tex.level,
93 psurf->u.tex.first_layer);
94 swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
95
96 if (bin_w) {
97 stride = bin_w << fdl_cpp_shift(&rsc->layout);
98
99 if (bases) {
100 base = bases[i];
101 }
102 } else {
103 stride = slice->pitch;
104 tile_mode = rsc->layout.tile_mode;
105 }
106 } else if (i < nr_bufs && bases) {
107 base = bases[i];
108 }
109
110 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
111 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
112 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
115 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
116 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
117 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
118 } else {
119 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
120 }
121
122 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
123 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
124 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
125 fd3_fs_output_format(pformat))));
126 }
127 }
128
129 static bool
130 use_hw_binning(struct fd_batch *batch)
131 {
132 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
133
134 /* workaround: combining scissor optimization and hw binning
135 * seems problematic. Seems like we end up with a mismatch
136 * between binning pass and rendering pass, wrt. where the hw
137 * thinks the vertices belong. And the blob driver doesn't
138 * seem to implement anything like scissor optimization, so
139 * not entirely sure what I might be missing.
140 *
141 * But scissor optimization is mainly for window managers,
142 * which don't have many vertices (and therefore doesn't
143 * benefit much from binning pass).
144 *
145 * So for now just disable binning if scissor optimization is
146 * used.
147 */
148 if (gmem->minx || gmem->miny)
149 return false;
150
151 if ((gmem->maxpw * gmem->maxph) > 32)
152 return false;
153
154 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
155 return false;
156
157 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
158 }
159
160 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
161 static void update_vsc_pipe(struct fd_batch *batch);
162 static void
163 emit_binning_workaround(struct fd_batch *batch)
164 {
165 struct fd_context *ctx = batch->ctx;
166 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
167 struct fd_ringbuffer *ring = batch->gmem;
168 struct fd3_emit emit = {
169 .debug = &ctx->debug,
170 .vtx = &ctx->solid_vbuf_state,
171 .prog = &ctx->solid_prog,
172 .key = {
173 .half_precision = true,
174 },
175 };
176
177 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
178 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
179 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
180 A3XX_RB_MODE_CONTROL_MRT(0));
181 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
182 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
183 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
184
185 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
186 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
187 A3XX_RB_COPY_CONTROL_MODE(0) |
188 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
189 OUT_RELOCW(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
190 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
191 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
192 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
193 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
194 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
195 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
196
197 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
198 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
199 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
200 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
201
202 fd3_program_emit(ring, &emit, 0, NULL);
203 fd3_emit_vertex_bufs(ring, &emit);
204
205 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
206 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
207 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
208 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
209 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
210 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
211 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
212 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
213 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
214
215 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
216 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
217 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
218
219 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
220 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
221 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
222 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
223
224 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
225 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
226
227 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
228 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
229 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
230 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
231 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
232 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
233 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
234 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
235 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
236
237 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
238 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
239
240 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
241 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
242 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
243 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
244 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
245
246 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
247 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
248 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
249 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
250 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
251
252 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
253 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
254 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
255 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
256 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
257
258 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
259 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
260 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
261 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
262 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
263
264 fd_wfi(batch, ring);
265 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
266 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
267 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
268 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
269 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
270 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
271 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
272
273 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
274 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
275 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
276 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
277 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
278 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
279
280 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
281 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
282 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
283
284 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
285 OUT_RING(ring, 0x00000000); /* viz query info. */
286 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
287 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
288 OUT_RING(ring, 2); /* NumIndices */
289 OUT_RING(ring, 2);
290 OUT_RING(ring, 1);
291 fd_reset_wfi(batch);
292
293 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
294 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
295
296 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
297 OUT_RING(ring, 0x00000000);
298
299 fd_wfi(batch, ring);
300 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
301 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
302 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
303
304 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
305 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
306 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
307 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
308
309 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
310 OUT_RING(ring, 0x00000000);
311 }
312
313 /* transfer from gmem to system memory (ie. normal RAM) */
314
315 static void
316 emit_gmem2mem_surf(struct fd_batch *batch,
317 enum adreno_rb_copy_control_mode mode,
318 bool stencil,
319 uint32_t base, struct pipe_surface *psurf)
320 {
321 struct fd_ringbuffer *ring = batch->gmem;
322 struct fd_resource *rsc = fd_resource(psurf->texture);
323 enum pipe_format format = psurf->format;
324
325 if (!rsc->valid)
326 return;
327
328 if (stencil) {
329 rsc = rsc->stencil;
330 format = rsc->base.format;
331 }
332
333 struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
334 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
335 psurf->u.tex.first_layer);
336
337 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
338
339 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
340 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
341 A3XX_RB_COPY_CONTROL_MODE(mode) |
342 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
343 COND(format == PIPE_FORMAT_Z32_FLOAT ||
344 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
345 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
346
347 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
348 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch));
349 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
350 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
351 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
352 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
353 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
354
355 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
356 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
357 }
358
359 static void
360 fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
361 {
362 struct fd_context *ctx = batch->ctx;
363 struct fd_ringbuffer *ring = batch->gmem;
364 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
365 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
366 struct fd3_emit emit = {
367 .debug = &ctx->debug,
368 .vtx = &ctx->solid_vbuf_state,
369 .prog = &ctx->solid_prog,
370 .key = {
371 .half_precision = true,
372 },
373 };
374 int i;
375
376 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
377 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
378
379 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
380 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
381 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
382 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
383 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
384 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
385 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
386 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
387 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
388
389 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
390 OUT_RING(ring, 0xff000000 |
391 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
392 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
393 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
394 OUT_RING(ring, 0xff000000 |
395 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
396 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
397 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
398
399 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
400 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
401
402 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
403 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
404
405 fd_wfi(batch, ring);
406 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
407 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
408 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
409 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
410 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
411 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
412 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
413
414 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
415 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
416 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
417 A3XX_RB_MODE_CONTROL_MRT(0));
418
419 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
420 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
421 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
422 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
423 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(batch->gmem_state->bin_w));
424
425 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
426 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
427 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
428 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
429
430 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
431 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
432 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
433 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
434 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
435
436 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
437 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
438 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
439 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
440 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
441
442 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
443 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
444 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
445 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
446 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
447
448 fd3_program_emit(ring, &emit, 0, NULL);
449 fd3_emit_vertex_bufs(ring, &emit);
450
451 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
452 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
453 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
454 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
455 gmem->zsbuf_base[0], pfb->zsbuf);
456 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
457 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
458 gmem->zsbuf_base[1], pfb->zsbuf);
459 }
460
461 if (batch->resolve & FD_BUFFER_COLOR) {
462 for (i = 0; i < pfb->nr_cbufs; i++) {
463 if (!pfb->cbufs[i])
464 continue;
465 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
466 continue;
467 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
468 gmem->cbuf_base[i], pfb->cbufs[i]);
469 }
470 }
471
472 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
473 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
474 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
475 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
476
477 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
478 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
479 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
480 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
481 }
482
483 /* transfer from system memory to gmem */
484
485 static void
486 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
487 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
488 {
489 struct fd_ringbuffer *ring = batch->gmem;
490 struct pipe_surface *zsbufs[2];
491
492 assert(bufs > 0);
493
494 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
495 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
496 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
497 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
498
499 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
500
501 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
502 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
503 /* Depth is stored as unorm in gmem, so we have to write it in using a
504 * special blit shader which writes depth.
505 */
506 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
507 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
508 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
509 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
510 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
511 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
512
513 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
514 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
515 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
516 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->gmem_state->bin_w));
517
518 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
519 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
520 OUT_RING(ring, 0);
521 } else {
522 /* The gmem_restore_tex logic will put the first buffer's stencil
523 * as color. Supply it with the proper information to make that
524 * happen.
525 */
526 zsbufs[0] = zsbufs[1] = psurf[0];
527 psurf = zsbufs;
528 bufs = 2;
529 }
530 } else {
531 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
532 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
533 }
534
535 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
536
537 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
538 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
539 }
540
541 static void
542 fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
543 {
544 struct fd_context *ctx = batch->ctx;
545 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
546 struct fd_ringbuffer *ring = batch->gmem;
547 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
548 struct fd3_emit emit = {
549 .debug = &ctx->debug,
550 .vtx = &ctx->blit_vbuf_state,
551 .sprite_coord_enable = 1,
552 /* NOTE: They all use the same VP, this is for vtx bufs. */
553 .prog = &ctx->blit_prog[0],
554 .key = {
555 .half_precision = fd_half_precision(pfb),
556 },
557 };
558 float x0, y0, x1, y1;
559 unsigned bin_w = tile->bin_w;
560 unsigned bin_h = tile->bin_h;
561 unsigned i;
562
563 /* write texture coordinates to vertexbuf: */
564 x0 = ((float)tile->xoff) / ((float)pfb->width);
565 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
566 y0 = ((float)tile->yoff) / ((float)pfb->height);
567 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
568
569 OUT_PKT3(ring, CP_MEM_WRITE, 5);
570 OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
571 OUT_RING(ring, fui(x0));
572 OUT_RING(ring, fui(y0));
573 OUT_RING(ring, fui(x1));
574 OUT_RING(ring, fui(y1));
575
576 fd3_emit_cache_flush(batch, ring);
577
578 for (i = 0; i < 4; i++) {
579 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
580 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
581 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
582 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
583
584 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
585 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
586 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
587 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
588 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
589 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
590 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
591 }
592
593 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
594 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
595 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
596
597 fd_wfi(batch, ring);
598 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
599 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
600
601 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
602 OUT_RING(ring, 0);
603 OUT_RING(ring, 0);
604
605 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
606 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
607
608 fd_wfi(batch, ring);
609 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
610 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
611 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
612 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
613 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
614 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
615 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
616
617 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
618 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
619 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
620 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
621 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
622
623 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
624 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
625 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
626 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
627 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
628
629 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
630 OUT_RING(ring, 0x2 |
631 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
632 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
633 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
634 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
635 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
636 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
637 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
638 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
639
640 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
641 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
642 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
643
644 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
645 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
646 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
647 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
648
649 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
650 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
651 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
652 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
653 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
654
655 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
656 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
657 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
658 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
659 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
660
661 fd3_emit_vertex_bufs(ring, &emit);
662
663 /* for gmem pitch/base calculations, we need to use the non-
664 * truncated tile sizes:
665 */
666 bin_w = gmem->bin_w;
667 bin_h = gmem->bin_h;
668
669 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
670 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
671 emit.fs = NULL; /* frag shader changed so clear cache */
672 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
673 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
674 }
675
676 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
677 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
678 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
679 /* Non-float can use a regular color write. It's split over 8-bit
680 * components, so half precision is always sufficient.
681 */
682 emit.prog = &ctx->blit_prog[0];
683 emit.key.half_precision = true;
684 } else {
685 /* Float depth needs special blit shader that writes depth */
686 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
687 emit.prog = &ctx->blit_z;
688 else
689 emit.prog = &ctx->blit_zs;
690 emit.key.half_precision = false;
691 }
692 emit.fs = NULL; /* frag shader changed so clear cache */
693 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
694 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
695 }
696
697 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
698 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
699 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
700 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
701
702 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
703 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
704 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
705 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
706 }
707
708 static void
709 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
710 {
711 unsigned i;
712 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
713 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
714 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
715 }
716 util_dynarray_clear(&batch->draw_patches);
717 }
718
719 static void
720 patch_rbrc(struct fd_batch *batch, uint32_t val)
721 {
722 unsigned i;
723 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
724 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
725 *patch->cs = patch->val | val;
726 }
727 util_dynarray_clear(&batch->rbrc_patches);
728 }
729
730 /* for rendering directly to system memory: */
731 static void
732 fd3_emit_sysmem_prep(struct fd_batch *batch)
733 {
734 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
735 struct fd_ringbuffer *ring = batch->gmem;
736 uint32_t i, pitch = 0;
737
738 for (i = 0; i < pfb->nr_cbufs; i++) {
739 struct pipe_surface *psurf = pfb->cbufs[i];
740 if (!psurf)
741 continue;
742 struct fd_resource *rsc = fd_resource(psurf->texture);
743 struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
744 pitch = slice->pitch / rsc->layout.cpp;
745 }
746
747 fd3_emit_restore(batch, ring);
748
749 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
750 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
751 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
752
753 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
754
755 /* setup scissor/offset for current tile: */
756 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
757 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
758 A3XX_RB_WINDOW_OFFSET_Y(0));
759
760 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
761 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
762 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
763 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
764 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
765
766 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
767 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
768 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
769 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
770 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
771
772 patch_draws(batch, IGNORE_VISIBILITY);
773 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
774 }
775
776 static void
777 update_vsc_pipe(struct fd_batch *batch)
778 {
779 struct fd_context *ctx = batch->ctx;
780 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
781 struct fd3_context *fd3_ctx = fd3_context(ctx);
782 struct fd_ringbuffer *ring = batch->gmem;
783 int i;
784
785 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
786 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
787
788 for (i = 0; i < 8; i++) {
789 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
790
791 if (!ctx->vsc_pipe_bo[i]) {
792 ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
793 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
794 }
795
796 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
797 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
798 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
799 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
800 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
801 OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
802 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
803 }
804 }
805
806 static void
807 emit_binning_pass(struct fd_batch *batch)
808 {
809 struct fd_context *ctx = batch->ctx;
810 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
811 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
812 struct fd_ringbuffer *ring = batch->gmem;
813 int i;
814
815 uint32_t x1 = gmem->minx;
816 uint32_t y1 = gmem->miny;
817 uint32_t x2 = gmem->minx + gmem->width - 1;
818 uint32_t y2 = gmem->miny + gmem->height - 1;
819
820 if (ctx->screen->gpu_id == 320) {
821 emit_binning_workaround(batch);
822 fd_wfi(batch, ring);
823 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
824 OUT_RING(ring, 0x00007fff);
825 }
826
827 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
828 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
829
830 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
831 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
832 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
833 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
834
835 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
836 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
837 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
838
839 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
840 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
841 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
842 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
843
844 /* setup scissor/offset for whole screen: */
845 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
846 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
847 A3XX_RB_WINDOW_OFFSET_Y(y1));
848
849 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
850 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
851
852 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
853 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
854 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
855 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
856 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
857
858 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
859 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
860 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
861 A3XX_RB_MODE_CONTROL_MRT(0));
862
863 for (i = 0; i < 4; i++) {
864 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
865 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
866 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
867 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
868 }
869
870 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
871 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
872 A3XX_PC_VSTREAM_CONTROL_N(0));
873
874 /* emit IB to binning drawcmds: */
875 fd3_emit_ib(ring, batch->binning);
876 fd_reset_wfi(batch);
877
878 fd_wfi(batch, ring);
879
880 /* and then put stuff back the way it was: */
881
882 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
883 OUT_RING(ring, 0x00000000);
884
885 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
886 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
887 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
888 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
889 A3XX_SP_SP_CTRL_REG_L0MODE(0));
890
891 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
892 OUT_RING(ring, 0x00000000);
893
894 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
895 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
896 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
897 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
898
899 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
900 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
901 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
902 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
903 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
904 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
905 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
906
907 fd_event_write(batch, ring, CACHE_FLUSH);
908 fd_wfi(batch, ring);
909
910 if (ctx->screen->gpu_id == 320) {
911 /* dummy-draw workaround: */
912 OUT_PKT3(ring, CP_DRAW_INDX, 3);
913 OUT_RING(ring, 0x00000000);
914 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
915 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
916 OUT_RING(ring, 0); /* NumIndices */
917 fd_reset_wfi(batch);
918 }
919
920 OUT_PKT3(ring, CP_NOP, 4);
921 OUT_RING(ring, 0x00000000);
922 OUT_RING(ring, 0x00000000);
923 OUT_RING(ring, 0x00000000);
924 OUT_RING(ring, 0x00000000);
925
926 fd_wfi(batch, ring);
927
928 if (ctx->screen->gpu_id == 320) {
929 emit_binning_workaround(batch);
930 }
931 }
932
933 /* before first tile */
934 static void
935 fd3_emit_tile_init(struct fd_batch *batch)
936 {
937 struct fd_ringbuffer *ring = batch->gmem;
938 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
939 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
940 uint32_t rb_render_control;
941
942 fd3_emit_restore(batch, ring);
943
944 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
945 * at the right and bottom edge tiles
946 */
947 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
948 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
949 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
950
951 update_vsc_pipe(batch);
952
953 fd_wfi(batch, ring);
954 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
955 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
956 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
957
958 if (use_hw_binning(batch)) {
959 /* emit hw binning pass: */
960 emit_binning_pass(batch);
961
962 patch_draws(batch, USE_VISIBILITY);
963 } else {
964 patch_draws(batch, IGNORE_VISIBILITY);
965 }
966
967 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
968 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
969
970 patch_rbrc(batch, rb_render_control);
971 }
972
973 /* before mem2gmem */
974 static void
975 fd3_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
976 {
977 struct fd_ringbuffer *ring = batch->gmem;
978 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
979
980 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
981 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
982 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
983 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
984 }
985
986 /* before IB to rendering cmds: */
987 static void
988 fd3_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
989 {
990 struct fd_context *ctx = batch->ctx;
991 struct fd3_context *fd3_ctx = fd3_context(ctx);
992 struct fd_ringbuffer *ring = batch->gmem;
993 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
994 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
995
996 uint32_t x1 = tile->xoff;
997 uint32_t y1 = tile->yoff;
998 uint32_t x2 = tile->xoff + tile->bin_w - 1;
999 uint32_t y2 = tile->yoff + tile->bin_h - 1;
1000
1001 uint32_t reg;
1002
1003 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
1004 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
1005 if (pfb->zsbuf) {
1006 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
1007 }
1008 OUT_RING(ring, reg);
1009 if (pfb->zsbuf) {
1010 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1011 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(gmem->bin_w <<
1012 fdl_cpp_shift(&rsc->layout)));
1013 if (rsc->stencil) {
1014 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1015 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1016 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(gmem->bin_w <<
1017 fdl_cpp_shift(&rsc->stencil->layout)));
1018 }
1019 } else {
1020 OUT_RING(ring, 0x00000000);
1021 }
1022
1023 if (use_hw_binning(batch)) {
1024 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
1025 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
1026
1027 assert(pipe->w && pipe->h);
1028
1029 fd_event_write(batch, ring, HLSQ_FLUSH);
1030 fd_wfi(batch, ring);
1031
1032 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1033 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1034 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1035
1036
1037 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1038 OUT_RELOCW(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1039 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1040 (tile->p * 4), 0, 0);
1041 } else {
1042 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1043 OUT_RING(ring, 0x00000000);
1044 }
1045
1046 OUT_PKT3(ring, CP_SET_BIN, 3);
1047 OUT_RING(ring, 0x00000000);
1048 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1049 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1050
1051 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1052
1053 /* setup scissor/offset for current tile: */
1054 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1055 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1056 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1057
1058 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1059 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1060 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1061 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1062 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1063 }
1064
1065 void
1066 fd3_gmem_init(struct pipe_context *pctx)
1067 {
1068 struct fd_context *ctx = fd_context(pctx);
1069
1070 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1071 ctx->emit_tile_init = fd3_emit_tile_init;
1072 ctx->emit_tile_prep = fd3_emit_tile_prep;
1073 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1074 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1075 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1076 }