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freedreno: Replace OUT_RELOCW with OUT_RELOC.
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd3_gmem.h"
38 #include "fd3_context.h"
39 #include "fd3_emit.h"
40 #include "fd3_program.h"
41 #include "fd3_format.h"
42 #include "fd3_zsa.h"
43
44 static void
45 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
46 struct pipe_surface **bufs, const uint32_t *bases, uint32_t bin_w,
47 bool decode_srgb)
48 {
49 enum a3xx_tile_mode tile_mode;
50 unsigned i;
51
52 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
53 enum pipe_format pformat = 0;
54 enum a3xx_color_fmt format = 0;
55 enum a3xx_color_swap swap = WZYX;
56 bool srgb = false;
57 struct fd_resource *rsc = NULL;
58 struct fdl_slice *slice = NULL;
59 uint32_t stride = 0;
60 uint32_t base = 0;
61 uint32_t offset = 0;
62
63 if (bin_w) {
64 tile_mode = TILE_32X32;
65 } else {
66 tile_mode = LINEAR;
67 }
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71
72 rsc = fd_resource(psurf->texture);
73 pformat = psurf->format;
74 /* In case we're drawing to Z32F_S8, the "color" actually goes to
75 * the stencil
76 */
77 if (rsc->stencil) {
78 rsc = rsc->stencil;
79 pformat = rsc->base.format;
80 if (bases)
81 bases++;
82 }
83 slice = fd_resource_slice(rsc, psurf->u.tex.level);
84 format = fd3_pipe2color(pformat);
85 if (decode_srgb)
86 srgb = util_format_is_srgb(pformat);
87 else
88 pformat = util_format_linear(pformat);
89
90 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
91
92 offset = fd_resource_offset(rsc, psurf->u.tex.level,
93 psurf->u.tex.first_layer);
94 swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
95
96 if (bin_w) {
97 stride = bin_w << fdl_cpp_shift(&rsc->layout);
98
99 if (bases) {
100 base = bases[i];
101 }
102 } else {
103 stride = slice->pitch;
104 tile_mode = rsc->layout.tile_mode;
105 }
106 } else if (i < nr_bufs && bases) {
107 base = bases[i];
108 }
109
110 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
111 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
112 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
115 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
116 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
117 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
118 } else {
119 OUT_RELOC(ring, rsc->bo, offset, 0, -1);
120 }
121
122 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
123 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
124 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
125 fd3_fs_output_format(pformat))));
126 }
127 }
128
129 static bool
130 use_hw_binning(struct fd_batch *batch)
131 {
132 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
133
134 /* workaround: combining scissor optimization and hw binning
135 * seems problematic. Seems like we end up with a mismatch
136 * between binning pass and rendering pass, wrt. where the hw
137 * thinks the vertices belong. And the blob driver doesn't
138 * seem to implement anything like scissor optimization, so
139 * not entirely sure what I might be missing.
140 *
141 * But scissor optimization is mainly for window managers,
142 * which don't have many vertices (and therefore doesn't
143 * benefit much from binning pass).
144 *
145 * So for now just disable binning if scissor optimization is
146 * used.
147 */
148 if (gmem->minx || gmem->miny)
149 return false;
150
151 if ((gmem->maxpw * gmem->maxph) > 32)
152 return false;
153
154 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
155 return false;
156
157 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
158 }
159
160 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
161 static void update_vsc_pipe(struct fd_batch *batch);
162 static void
163 emit_binning_workaround(struct fd_batch *batch)
164 {
165 struct fd_context *ctx = batch->ctx;
166 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
167 struct fd_ringbuffer *ring = batch->gmem;
168 struct fd3_emit emit = {
169 .debug = &ctx->debug,
170 .vtx = &ctx->solid_vbuf_state,
171 .prog = &ctx->solid_prog,
172 };
173
174 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
175 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
176 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
177 A3XX_RB_MODE_CONTROL_MRT(0));
178 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
179 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
180 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
181
182 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
183 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
184 A3XX_RB_COPY_CONTROL_MODE(0) |
185 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
186 OUT_RELOC(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
187 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
188 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
189 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
190 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
191 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
192 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
193
194 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
195 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
196 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
197 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
198
199 fd3_program_emit(ring, &emit, 0, NULL);
200 fd3_emit_vertex_bufs(ring, &emit);
201
202 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
203 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
204 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
205 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
206 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
207 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
208 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
209 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
210 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
211
212 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
213 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
214 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
215
216 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
217 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
218 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
219 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
220
221 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
222 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
223
224 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
225 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
226 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
227 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
228 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
229 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
230 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
231 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
232 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
233
234 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
235 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
236
237 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
238 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
239 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
240 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
241 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
242
243 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
244 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
245 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
246 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
247 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
248
249 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
250 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
251 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
252 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
253 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
254
255 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
256 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
257 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
258 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
259 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
260
261 fd_wfi(batch, ring);
262 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
263 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
264 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
265 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
266 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
267 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
268 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
269
270 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
271 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
272 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
273 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
274 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
275 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
276
277 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
278 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
279 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
280
281 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
282 OUT_RING(ring, 0x00000000); /* viz query info. */
283 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
284 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
285 OUT_RING(ring, 2); /* NumIndices */
286 OUT_RING(ring, 2);
287 OUT_RING(ring, 1);
288 fd_reset_wfi(batch);
289
290 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
291 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
292
293 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
294 OUT_RING(ring, 0x00000000);
295
296 fd_wfi(batch, ring);
297 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
298 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
299 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
300
301 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
302 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
303 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
304 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
305
306 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
307 OUT_RING(ring, 0x00000000);
308 }
309
310 /* transfer from gmem to system memory (ie. normal RAM) */
311
312 static void
313 emit_gmem2mem_surf(struct fd_batch *batch,
314 enum adreno_rb_copy_control_mode mode,
315 bool stencil,
316 uint32_t base, struct pipe_surface *psurf)
317 {
318 struct fd_ringbuffer *ring = batch->gmem;
319 struct fd_resource *rsc = fd_resource(psurf->texture);
320 enum pipe_format format = psurf->format;
321
322 if (!rsc->valid)
323 return;
324
325 if (stencil) {
326 rsc = rsc->stencil;
327 format = rsc->base.format;
328 }
329
330 struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
331 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
332 psurf->u.tex.first_layer);
333
334 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
335
336 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
337 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
338 A3XX_RB_COPY_CONTROL_MODE(mode) |
339 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
340 COND(format == PIPE_FORMAT_Z32_FLOAT ||
341 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
342 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
343
344 OUT_RELOC(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
345 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch));
346 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
347 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
348 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
349 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
350 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
351
352 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
353 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
354 }
355
356 static void
357 fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
358 {
359 struct fd_context *ctx = batch->ctx;
360 struct fd_ringbuffer *ring = batch->gmem;
361 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
362 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
363 struct fd3_emit emit = {
364 .debug = &ctx->debug,
365 .vtx = &ctx->solid_vbuf_state,
366 .prog = &ctx->solid_prog,
367 };
368 int i;
369
370 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
371 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
372
373 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
374 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
375 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
376 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
377 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
378 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
379 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
380 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
381 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
382
383 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
384 OUT_RING(ring, 0xff000000 |
385 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
386 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
387 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
388 OUT_RING(ring, 0xff000000 |
389 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
390 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
391 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
392
393 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
394 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
395
396 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
397 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
398
399 fd_wfi(batch, ring);
400 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
401 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
402 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
403 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
404 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
405 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
406 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
407
408 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
409 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
410 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
411 A3XX_RB_MODE_CONTROL_MRT(0));
412
413 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
414 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
415 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
416 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
417 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(batch->gmem_state->bin_w));
418
419 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
420 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
421 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
422 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
423
424 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
425 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
426 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
427 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
428 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
429
430 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
431 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
432 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
433 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
434 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
435
436 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
437 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
438 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
439 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
440 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
441
442 fd3_program_emit(ring, &emit, 0, NULL);
443 fd3_emit_vertex_bufs(ring, &emit);
444
445 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
446 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
447 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
448 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
449 gmem->zsbuf_base[0], pfb->zsbuf);
450 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
451 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
452 gmem->zsbuf_base[1], pfb->zsbuf);
453 }
454
455 if (batch->resolve & FD_BUFFER_COLOR) {
456 for (i = 0; i < pfb->nr_cbufs; i++) {
457 if (!pfb->cbufs[i])
458 continue;
459 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
460 continue;
461 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
462 gmem->cbuf_base[i], pfb->cbufs[i]);
463 }
464 }
465
466 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
467 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
468 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
469 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
470
471 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
472 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
473 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
474 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
475 }
476
477 /* transfer from system memory to gmem */
478
479 static void
480 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
481 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
482 {
483 struct fd_ringbuffer *ring = batch->gmem;
484 struct pipe_surface *zsbufs[2];
485
486 assert(bufs > 0);
487
488 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
489 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
490 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
491 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
492
493 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
494
495 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
496 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
497 /* Depth is stored as unorm in gmem, so we have to write it in using a
498 * special blit shader which writes depth.
499 */
500 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
501 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
502 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
503 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
504 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
505 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
506
507 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
508 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
509 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
510 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->gmem_state->bin_w));
511
512 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
513 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
514 OUT_RING(ring, 0);
515 } else {
516 /* The gmem_restore_tex logic will put the first buffer's stencil
517 * as color. Supply it with the proper information to make that
518 * happen.
519 */
520 zsbufs[0] = zsbufs[1] = psurf[0];
521 psurf = zsbufs;
522 bufs = 2;
523 }
524 } else {
525 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
526 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
527 }
528
529 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
530
531 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
532 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
533 }
534
535 static void
536 fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
537 {
538 struct fd_context *ctx = batch->ctx;
539 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
540 struct fd_ringbuffer *ring = batch->gmem;
541 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
542 struct fd3_emit emit = {
543 .debug = &ctx->debug,
544 .vtx = &ctx->blit_vbuf_state,
545 .sprite_coord_enable = 1,
546 /* NOTE: They all use the same VP, this is for vtx bufs. */
547 .prog = &ctx->blit_prog[0],
548 };
549 float x0, y0, x1, y1;
550 unsigned bin_w = tile->bin_w;
551 unsigned bin_h = tile->bin_h;
552 unsigned i;
553
554 /* write texture coordinates to vertexbuf: */
555 x0 = ((float)tile->xoff) / ((float)pfb->width);
556 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
557 y0 = ((float)tile->yoff) / ((float)pfb->height);
558 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
559
560 OUT_PKT3(ring, CP_MEM_WRITE, 5);
561 OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
562 OUT_RING(ring, fui(x0));
563 OUT_RING(ring, fui(y0));
564 OUT_RING(ring, fui(x1));
565 OUT_RING(ring, fui(y1));
566
567 fd3_emit_cache_flush(batch, ring);
568
569 for (i = 0; i < 4; i++) {
570 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
571 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
572 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
573 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
574
575 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
576 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
577 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
578 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
579 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
580 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
581 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
582 }
583
584 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
585 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
586 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
587
588 fd_wfi(batch, ring);
589 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
590 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
591
592 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
593 OUT_RING(ring, 0);
594 OUT_RING(ring, 0);
595
596 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
597 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
598
599 fd_wfi(batch, ring);
600 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
601 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
602 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
603 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
604 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
605 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
606 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
607
608 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
609 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
610 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
611 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
612 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
613
614 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
615 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
616 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
617 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
618 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
619
620 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
621 OUT_RING(ring, 0x2 |
622 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
623 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
624 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
625 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
626 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
627 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
628 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
629 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
630
631 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
632 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
633 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
634
635 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
636 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
637 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
638 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
639
640 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
641 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
642 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
643 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
644 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
645
646 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
647 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
648 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
649 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
650 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
651
652 fd3_emit_vertex_bufs(ring, &emit);
653
654 /* for gmem pitch/base calculations, we need to use the non-
655 * truncated tile sizes:
656 */
657 bin_w = gmem->bin_w;
658 bin_h = gmem->bin_h;
659
660 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
661 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
662 emit.fs = NULL; /* frag shader changed so clear cache */
663 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
664 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
665 }
666
667 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
668 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
669 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
670 /* Non-float can use a regular color write. It's split over 8-bit
671 * components, so half precision is always sufficient.
672 */
673 emit.prog = &ctx->blit_prog[0];
674 } else {
675 /* Float depth needs special blit shader that writes depth */
676 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
677 emit.prog = &ctx->blit_z;
678 else
679 emit.prog = &ctx->blit_zs;
680 }
681 emit.fs = NULL; /* frag shader changed so clear cache */
682 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
683 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
684 }
685
686 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
687 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
688 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
689 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
690
691 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
692 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
693 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
694 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
695 }
696
697 static void
698 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
699 {
700 unsigned i;
701 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
702 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
703 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
704 }
705 util_dynarray_clear(&batch->draw_patches);
706 }
707
708 static void
709 patch_rbrc(struct fd_batch *batch, uint32_t val)
710 {
711 unsigned i;
712 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
713 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
714 *patch->cs = patch->val | val;
715 }
716 util_dynarray_clear(&batch->rbrc_patches);
717 }
718
719 /* for rendering directly to system memory: */
720 static void
721 fd3_emit_sysmem_prep(struct fd_batch *batch)
722 {
723 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
724 struct fd_ringbuffer *ring = batch->gmem;
725 uint32_t i, pitch = 0;
726
727 for (i = 0; i < pfb->nr_cbufs; i++) {
728 struct pipe_surface *psurf = pfb->cbufs[i];
729 if (!psurf)
730 continue;
731 struct fd_resource *rsc = fd_resource(psurf->texture);
732 struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
733 pitch = slice->pitch / rsc->layout.cpp;
734 }
735
736 fd3_emit_restore(batch, ring);
737
738 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
739 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
740 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
741
742 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
743
744 /* setup scissor/offset for current tile: */
745 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
746 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
747 A3XX_RB_WINDOW_OFFSET_Y(0));
748
749 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
750 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
751 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
752 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
753 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
754
755 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
756 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
757 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
758 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
759 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
760
761 patch_draws(batch, IGNORE_VISIBILITY);
762 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
763 }
764
765 static void
766 update_vsc_pipe(struct fd_batch *batch)
767 {
768 struct fd_context *ctx = batch->ctx;
769 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
770 struct fd3_context *fd3_ctx = fd3_context(ctx);
771 struct fd_ringbuffer *ring = batch->gmem;
772 int i;
773
774 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
775 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
776
777 for (i = 0; i < 8; i++) {
778 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
779
780 if (!ctx->vsc_pipe_bo[i]) {
781 ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
782 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
783 }
784
785 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
786 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
787 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
788 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
789 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
790 OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
791 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
792 }
793 }
794
795 static void
796 emit_binning_pass(struct fd_batch *batch)
797 {
798 struct fd_context *ctx = batch->ctx;
799 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
800 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
801 struct fd_ringbuffer *ring = batch->gmem;
802 int i;
803
804 uint32_t x1 = gmem->minx;
805 uint32_t y1 = gmem->miny;
806 uint32_t x2 = gmem->minx + gmem->width - 1;
807 uint32_t y2 = gmem->miny + gmem->height - 1;
808
809 if (ctx->screen->gpu_id == 320) {
810 emit_binning_workaround(batch);
811 fd_wfi(batch, ring);
812 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
813 OUT_RING(ring, 0x00007fff);
814 }
815
816 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
817 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
818
819 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
820 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
821 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
822 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
823
824 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
825 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
826 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
827
828 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
829 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
830 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
831 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
832
833 /* setup scissor/offset for whole screen: */
834 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
835 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
836 A3XX_RB_WINDOW_OFFSET_Y(y1));
837
838 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
839 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
840
841 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
842 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
843 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
844 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
845 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
846
847 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
848 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
849 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
850 A3XX_RB_MODE_CONTROL_MRT(0));
851
852 for (i = 0; i < 4; i++) {
853 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
854 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
855 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
856 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
857 }
858
859 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
860 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
861 A3XX_PC_VSTREAM_CONTROL_N(0));
862
863 /* emit IB to binning drawcmds: */
864 fd3_emit_ib(ring, batch->binning);
865 fd_reset_wfi(batch);
866
867 fd_wfi(batch, ring);
868
869 /* and then put stuff back the way it was: */
870
871 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
872 OUT_RING(ring, 0x00000000);
873
874 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
875 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
876 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
877 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
878 A3XX_SP_SP_CTRL_REG_L0MODE(0));
879
880 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
881 OUT_RING(ring, 0x00000000);
882
883 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
884 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
885 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
886 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
887
888 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
889 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
890 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
891 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
892 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
893 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
894 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
895
896 fd_event_write(batch, ring, CACHE_FLUSH);
897 fd_wfi(batch, ring);
898
899 if (ctx->screen->gpu_id == 320) {
900 /* dummy-draw workaround: */
901 OUT_PKT3(ring, CP_DRAW_INDX, 3);
902 OUT_RING(ring, 0x00000000);
903 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
904 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
905 OUT_RING(ring, 0); /* NumIndices */
906 fd_reset_wfi(batch);
907 }
908
909 OUT_PKT3(ring, CP_NOP, 4);
910 OUT_RING(ring, 0x00000000);
911 OUT_RING(ring, 0x00000000);
912 OUT_RING(ring, 0x00000000);
913 OUT_RING(ring, 0x00000000);
914
915 fd_wfi(batch, ring);
916
917 if (ctx->screen->gpu_id == 320) {
918 emit_binning_workaround(batch);
919 }
920 }
921
922 /* before first tile */
923 static void
924 fd3_emit_tile_init(struct fd_batch *batch)
925 {
926 struct fd_ringbuffer *ring = batch->gmem;
927 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
928 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
929 uint32_t rb_render_control;
930
931 fd3_emit_restore(batch, ring);
932
933 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
934 * at the right and bottom edge tiles
935 */
936 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
937 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
938 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
939
940 update_vsc_pipe(batch);
941
942 fd_wfi(batch, ring);
943 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
944 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
945 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
946
947 if (use_hw_binning(batch)) {
948 /* emit hw binning pass: */
949 emit_binning_pass(batch);
950
951 patch_draws(batch, USE_VISIBILITY);
952 } else {
953 patch_draws(batch, IGNORE_VISIBILITY);
954 }
955
956 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
957 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
958
959 patch_rbrc(batch, rb_render_control);
960 }
961
962 /* before mem2gmem */
963 static void
964 fd3_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
965 {
966 struct fd_ringbuffer *ring = batch->gmem;
967 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
968
969 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
970 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
971 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
972 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
973 }
974
975 /* before IB to rendering cmds: */
976 static void
977 fd3_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
978 {
979 struct fd_context *ctx = batch->ctx;
980 struct fd3_context *fd3_ctx = fd3_context(ctx);
981 struct fd_ringbuffer *ring = batch->gmem;
982 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
983 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
984
985 uint32_t x1 = tile->xoff;
986 uint32_t y1 = tile->yoff;
987 uint32_t x2 = tile->xoff + tile->bin_w - 1;
988 uint32_t y2 = tile->yoff + tile->bin_h - 1;
989
990 uint32_t reg;
991
992 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
993 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
994 if (pfb->zsbuf) {
995 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
996 }
997 OUT_RING(ring, reg);
998 if (pfb->zsbuf) {
999 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1000 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(gmem->bin_w <<
1001 fdl_cpp_shift(&rsc->layout)));
1002 if (rsc->stencil) {
1003 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1004 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1005 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(gmem->bin_w <<
1006 fdl_cpp_shift(&rsc->stencil->layout)));
1007 }
1008 } else {
1009 OUT_RING(ring, 0x00000000);
1010 }
1011
1012 if (use_hw_binning(batch)) {
1013 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
1014 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
1015
1016 assert(pipe->w && pipe->h);
1017
1018 fd_event_write(batch, ring, HLSQ_FLUSH);
1019 fd_wfi(batch, ring);
1020
1021 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1022 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1023 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1024
1025
1026 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1027 OUT_RELOC(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1028 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1029 (tile->p * 4), 0, 0);
1030 } else {
1031 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1032 OUT_RING(ring, 0x00000000);
1033 }
1034
1035 OUT_PKT3(ring, CP_SET_BIN, 3);
1036 OUT_RING(ring, 0x00000000);
1037 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1038 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1039
1040 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1041
1042 /* setup scissor/offset for current tile: */
1043 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1044 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1045 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1046
1047 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1048 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1049 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1050 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1051 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1052 }
1053
1054 void
1055 fd3_gmem_init(struct pipe_context *pctx)
1056 {
1057 struct fd_context *ctx = fd_context(pctx);
1058
1059 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1060 ctx->emit_tile_init = fd3_emit_tile_init;
1061 ctx->emit_tile_prep = fd3_emit_tile_prep;
1062 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1063 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1064 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1065 }