src/gallium/drivers/freedreno/a3xx/fd3_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd3_gmem.h"
  40 #include "fd3_context.h"
  41 #include "fd3_emit.h"
  42 #include "fd3_program.h"
  43 #include "fd3_format.h"
  44 #include "fd3_zsa.h"
  45
  46 static void
  47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  48                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  49 {
  50         enum a3xx_tile_mode tile_mode;
  51         unsigned i;
  52
  53         if (bin_w) {
  54                 tile_mode = TILE_32X32;
  55         } else {
  56                 tile_mode = LINEAR;
  57         }
  58
  59         for (i = 0; i < 4; i++) {
  60                 enum a3xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 struct fd_resource *rsc = NULL;
  63                 struct fd_resource_slice *slice = NULL;
  64                 uint32_t stride = 0;
  65                 uint32_t base = 0;
  66                 uint32_t layer_offset = 0;
  67
  68                 if ((i < nr_bufs) && bufs[i]) {
  69                         struct pipe_surface *psurf = bufs[i];
  70
  71                         rsc = fd_resource(psurf->texture);
  72                         slice = &rsc->slices[psurf->u.tex.level];
  73                         format = fd3_pipe2color(psurf->format);
  74                         swap = fd3_pipe2swap(psurf->format);
  75
  76                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  77
  78                         layer_offset = slice->size0 * psurf->u.tex.first_layer;
  79
  80                         if (bin_w) {
  81                                 stride = bin_w * rsc->cpp;
  82
  83                                 if (bases) {
  84                                         base = bases[i];
  85                                 }
  86                         } else {
  87                                 stride = slice->pitch * rsc->cpp;
  88                         }
  89                 }
  90
  91                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
  92                 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  93                                 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
  94                                 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  95                                 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
  96                 if (bin_w || (i >= nr_bufs)) {
  97                         OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
  98                 } else {
  99                         OUT_RELOCW(ring, rsc->bo,
 100                                         slice->offset + layer_offset, 0, -1);
 101                 }
 102
 103                 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
 104                 OUT_RING(ring, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format));
 105         }
 106 }
 107
 108 static uint32_t
 109 depth_base(struct fd_context *ctx)
 110 {
 111         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 112         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 113         uint32_t cpp = 4;
 114         if (pfb->cbufs[0]) {
 115                 struct fd_resource *rsc =
 116                                 fd_resource(pfb->cbufs[0]->texture);
 117                 cpp = rsc->cpp;
 118         }
 119         return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 120 }
 121
 122 static bool
 123 use_hw_binning(struct fd_context *ctx)
 124 {
 125         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 126
 127         /* workaround: combining scissor optimization and hw binning
 128          * seems problematic.  Seems like we end up with a mismatch
 129          * between binning pass and rendering pass, wrt. where the hw
 130          * thinks the vertices belong.  And the blob driver doesn't
 131          * seem to implement anything like scissor optimization, so
 132          * not entirely sure what I might be missing.
 133          *
 134          * But scissor optimization is mainly for window managers,
 135          * which don't have many vertices (and therefore doesn't
 136          * benefit much from binning pass).
 137          *
 138          * So for now just disable binning if scissor optimization is
 139          * used.
 140          */
 141         if (gmem->minx || gmem->miny)
 142                 return false;
 143
 144         return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
 145 }
 146
 147 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
 148 static void update_vsc_pipe(struct fd_context *ctx);
 149 static void
 150 emit_binning_workaround(struct fd_context *ctx)
 151 {
 152         struct fd3_context *fd3_ctx = fd3_context(ctx);
 153         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 154         struct fd_ringbuffer *ring = ctx->ring;
 155         struct fd3_emit emit = {
 156                         .vtx = &fd3_ctx->solid_vbuf_state,
 157                         .prog = &ctx->solid_prog,
 158                         .key = {
 159                                 .half_precision = true,
 160                         },
 161         };
 162
 163         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
 164         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 165                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 166         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
 167                         A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 168                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 169
 170         OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 171         OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 172                         A3XX_RB_COPY_CONTROL_MODE(0) |
 173                         A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
 174         OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
 175         OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
 176         OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 177                         A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
 178                         A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
 179                         A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 180                         A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
 181
 182         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 183         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 184                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 185                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 186
 187         fd3_program_emit(ring, &emit);
 188         fd3_emit_vertex_bufs(ring, &emit);
 189
 190         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
 191         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 192                         A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
 193                         A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
 194                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 195         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 196                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
 197         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 198         OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
 199
 200         OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
 201         OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
 202                         A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
 203
 204         OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
 205         OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 206                         A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 207                         A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
 208
 209         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 210         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 211
 212         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 213         OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 214                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 215                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 216                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 217                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 218                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 219                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 220                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 221
 222         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 223         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
 224
 225         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 226         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 227         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 228         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 229         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 230
 231         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 232         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 233                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 234                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 235                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 236
 237         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 238         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 239                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
 240         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
 241                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
 242
 243         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 244         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 245                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 246         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
 247                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
 248
 249         fd_wfi(ctx, ring);
 250         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 251         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
 252         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
 253         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
 254         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
 255         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 256         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 257
 258         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 259         OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
 260                         A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
 261                         A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
 262                         A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
 263                         A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
 264
 265         OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
 266         OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
 267                         A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
 268
 269         OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
 270         OUT_RING(ring, 0x00000000);   /* viz query info. */
 271         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
 272                         INDEX_SIZE_32_BIT, IGNORE_VISIBILITY));
 273         OUT_RING(ring, 2);            /* NumIndices */
 274         OUT_RING(ring, 2);
 275         OUT_RING(ring, 1);
 276         fd_reset_wfi(ctx);
 277
 278         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
 279         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
 280
 281         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 282         OUT_RING(ring, 0x00000000);
 283
 284         fd_wfi(ctx, ring);
 285         OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
 286         OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 287                         A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 288
 289         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 290         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 291                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 292                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 293
 294         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 295         OUT_RING(ring, 0x00000000);
 296 }
 297
 298 /* transfer from gmem to system memory (ie. normal RAM) */
 299
 300 static void
 301 emit_gmem2mem_surf(struct fd_context *ctx,
 302                 enum adreno_rb_copy_control_mode mode,
 303                 uint32_t base, struct pipe_surface *psurf)
 304 {
 305         struct fd_ringbuffer *ring = ctx->ring;
 306         struct fd_resource *rsc = fd_resource(psurf->texture);
 307         struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
 308         uint32_t layer_offset = slice->size0 * psurf->u.tex.first_layer;
 309
 310         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 311
 312         OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 313         OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 314                         A3XX_RB_COPY_CONTROL_MODE(mode) |
 315                         A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
 316
 317         OUT_RELOCW(ring, rsc->bo, slice->offset + layer_offset, 0, -1);    /* RB_COPY_DEST_BASE */
 318         OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 319         OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 320                         A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
 321                         A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 322                         A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 323                         A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf->format)));
 324
 325         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 326                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 327 }
 328
 329 static void
 330 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 331 {
 332         struct fd3_context *fd3_ctx = fd3_context(ctx);
 333         struct fd_ringbuffer *ring = ctx->ring;
 334         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 335         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 336         struct fd3_emit emit = {
 337                         .vtx = &fd3_ctx->solid_vbuf_state,
 338                         .prog = &ctx->solid_prog,
 339                         .key = {
 340                                 .half_precision = fd3_half_precision(format),
 341                         },
 342                         .format = format,
 343         };
 344
 345         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 346         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 347
 348         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 349         OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 350                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 351                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 352                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 353                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 354                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 355                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 356                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 357
 358         OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 359         OUT_RING(ring, 0xff000000 |
 360                         A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 361                         A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 362                         A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 363         OUT_RING(ring, 0xff000000 |
 364                         A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 365                         A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 366                         A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 367
 368         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 369         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 370
 371         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 372         OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
 373
 374         fd_wfi(ctx, ring);
 375         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 376         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
 377         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
 378         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
 379         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
 380         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 381         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 382
 383         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 384         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 385                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 386
 387         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 388         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 389                         A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 390                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 391                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
 392
 393         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 394         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 395                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 396                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 397
 398         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 399         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 400                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 401                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 402                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 403
 404         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 405         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 406                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 407         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 408                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 409
 410         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 411         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 412         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 413         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 414         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 415
 416         fd3_program_emit(ring, &emit);
 417         fd3_emit_vertex_bufs(ring, &emit);
 418
 419         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 420                 uint32_t base = depth_base(ctx);
 421                 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 422         }
 423
 424         if (ctx->resolve & FD_BUFFER_COLOR) {
 425                 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, 0, pfb->cbufs[0]);
 426         }
 427
 428         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 429         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 430                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 431
 432         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 433         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 434                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 435                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 436 }
 437
 438 /* transfer from system memory to gmem */
 439
 440 static void
 441 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
 442                 struct pipe_surface *psurf, uint32_t bin_w)
 443 {
 444         struct fd_ringbuffer *ring = ctx->ring;
 445
 446         emit_mrt(ring, 1, &psurf, &base, bin_w);
 447
 448         fd3_emit_gmem_restore_tex(ring, psurf);
 449
 450         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 451                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 452 }
 453
 454 static void
 455 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 456 {
 457         struct fd3_context *fd3_ctx = fd3_context(ctx);
 458         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 459         struct fd_ringbuffer *ring = ctx->ring;
 460         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 461         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 462         struct fd3_emit emit = {
 463                         .vtx = &fd3_ctx->blit_vbuf_state,
 464                         .prog = &ctx->blit_prog,
 465                         .key = {
 466                                 .half_precision = fd3_half_precision(format),
 467                         },
 468                         .format = format,
 469         };
 470         float x0, y0, x1, y1;
 471         unsigned bin_w = tile->bin_w;
 472         unsigned bin_h = tile->bin_h;
 473         unsigned i;
 474
 475         /* write texture coordinates to vertexbuf: */
 476         x0 = ((float)tile->xoff) / ((float)pfb->width);
 477         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 478         y0 = ((float)tile->yoff) / ((float)pfb->height);
 479         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 480
 481         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 482         OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 483         OUT_RING(ring, fui(x0));
 484         OUT_RING(ring, fui(y0));
 485         OUT_RING(ring, fui(x1));
 486         OUT_RING(ring, fui(y1));
 487
 488         for (i = 0; i < 4; i++) {
 489                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 490                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 491                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
 492                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 493
 494                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 495                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 496                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 497                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 498                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 499                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 500                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 501         }
 502
 503         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 504         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
 505                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 506
 507         fd_wfi(ctx, ring);
 508         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 509         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 510
 511         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 512         OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);   /* GRAS_CL_CLIP_CNTL */
 513
 514         fd_wfi(ctx, ring);
 515         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 516         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
 517         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
 518         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
 519         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
 520         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 521         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 522
 523         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 524         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 525                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 526         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 527                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 528
 529         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 530         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 531                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 532         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 533                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 534
 535         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 536         OUT_RING(ring, 0x2 |
 537                         A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 538                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 539                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 540                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 541                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 542                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 543                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 544                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 545
 546         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 547         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 548                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 549                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 550
 551         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 552         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
 553                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 554                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 555                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 556
 557         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 558         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 559         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 560         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 561         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 562
 563         fd3_program_emit(ring, &emit);
 564         fd3_emit_vertex_bufs(ring, &emit);
 565
 566         /* for gmem pitch/base calculations, we need to use the non-
 567          * truncated tile sizes:
 568          */
 569         bin_w = gmem->bin_w;
 570         bin_h = gmem->bin_h;
 571
 572         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 573                 emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
 574
 575         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
 576                 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
 577
 578         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 579         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 580                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 581                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 582 }
 583
 584 static void
 585 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 586 {
 587         unsigned i;
 588         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 589                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 590                 *patch->cs = patch->val | DRAW(0, 0, 0, vismode);
 591         }
 592         util_dynarray_resize(&ctx->draw_patches, 0);
 593 }
 594
 595 static void
 596 patch_rbrc(struct fd_context *ctx, uint32_t val)
 597 {
 598         struct fd3_context *fd3_ctx = fd3_context(ctx);
 599         unsigned i;
 600         for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
 601                 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
 602                 *patch->cs = patch->val | val;
 603         }
 604         util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
 605 }
 606
 607 /* for rendering directly to system memory: */
 608 static void
 609 fd3_emit_sysmem_prep(struct fd_context *ctx)
 610 {
 611         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 612         struct fd_ringbuffer *ring = ctx->ring;
 613         uint32_t pitch = 0;
 614
 615         if (pfb->cbufs[0]) {
 616                 struct pipe_surface *psurf = pfb->cbufs[0];
 617                 unsigned lvl = psurf->u.tex.level;
 618                 pitch = fd_resource(psurf->texture)->slices[lvl].pitch;
 619         }
 620
 621         fd3_emit_restore(ctx);
 622
 623         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 624         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 625                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 626
 627         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
 628
 629         /* setup scissor/offset for current tile: */
 630         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 631         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
 632                         A3XX_RB_WINDOW_OFFSET_Y(0));
 633
 634         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 635         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 636                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 637         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 638                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 639
 640         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 641         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 642                         A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
 643                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 644
 645         patch_draws(ctx, IGNORE_VISIBILITY);
 646         patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
 647 }
 648
 649 static void
 650 update_vsc_pipe(struct fd_context *ctx)
 651 {
 652         struct fd3_context *fd3_ctx = fd3_context(ctx);
 653         struct fd_ringbuffer *ring = ctx->ring;
 654         int i;
 655
 656         OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
 657         OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 658
 659         for (i = 0; i < 8; i++) {
 660                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 661
 662                 if (!pipe->bo) {
 663                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 664                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 665                 }
 666
 667                 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
 668                 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
 669                                 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
 670                                 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
 671                                 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
 672                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
 673                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
 674         }
 675 }
 676
 677 static void
 678 emit_binning_pass(struct fd_context *ctx)
 679 {
 680         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 681         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 682         struct fd_ringbuffer *ring = ctx->ring;
 683         int i;
 684
 685         uint32_t x1 = gmem->minx;
 686         uint32_t y1 = gmem->miny;
 687         uint32_t x2 = gmem->minx + gmem->width - 1;
 688         uint32_t y2 = gmem->miny + gmem->height - 1;
 689
 690         if (ctx->screen->gpu_id == 320) {
 691                 emit_binning_workaround(ctx);
 692                 fd_wfi(ctx, ring);
 693                 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 694                 OUT_RING(ring, 0x00007fff);
 695         }
 696
 697         OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
 698         OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
 699
 700         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 701         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 702                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 703                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 704
 705         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 706         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 707                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 708
 709         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 710         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 711                         A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 712                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 713
 714         /* setup scissor/offset for whole screen: */
 715         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 716         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
 717                         A3XX_RB_WINDOW_OFFSET_Y(y1));
 718
 719         OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
 720         OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
 721
 722         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 723         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 724                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 725         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 726                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 727
 728         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 729         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 730                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 731
 732         for (i = 0; i < 4; i++) {
 733                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 734                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
 735                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
 736                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
 737         }
 738
 739         OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 740         OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
 741                         A3XX_PC_VSTREAM_CONTROL_N(0));
 742
 743         /* emit IB to binning drawcmds: */
 744         OUT_IB(ring, ctx->binning_start, ctx->binning_end);
 745         fd_reset_wfi(ctx);
 746
 747         fd_wfi(ctx, ring);
 748
 749         /* and then put stuff back the way it was: */
 750
 751         OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
 752         OUT_RING(ring, 0x00000000);
 753
 754         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 755         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
 756                         A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
 757                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 758                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 759
 760         OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
 761         OUT_RING(ring, 0x00000000);
 762
 763         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 764         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 765                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 766                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 767
 768         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
 769         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 770                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 771         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 772                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 773                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 774
 775         fd_event_write(ctx, ring, CACHE_FLUSH);
 776         fd_wfi(ctx, ring);
 777
 778         if (ctx->screen->gpu_id == 320) {
 779                 /* dummy-draw workaround: */
 780                 OUT_PKT3(ring, CP_DRAW_INDX, 3);
 781                 OUT_RING(ring, 0x00000000);
 782                 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
 783                                 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 784                 OUT_RING(ring, 0);             /* NumIndices */
 785                 fd_reset_wfi(ctx);
 786         }
 787
 788         OUT_PKT3(ring, CP_NOP, 4);
 789         OUT_RING(ring, 0x00000000);
 790         OUT_RING(ring, 0x00000000);
 791         OUT_RING(ring, 0x00000000);
 792         OUT_RING(ring, 0x00000000);
 793
 794         fd_wfi(ctx, ring);
 795
 796         if (ctx->screen->gpu_id == 320) {
 797                 emit_binning_workaround(ctx);
 798         }
 799 }
 800
 801 /* before first tile */
 802 static void
 803 fd3_emit_tile_init(struct fd_context *ctx)
 804 {
 805         struct fd_ringbuffer *ring = ctx->ring;
 806         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 807         uint32_t rb_render_control;
 808
 809         fd3_emit_restore(ctx);
 810
 811         /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
 812          * at the right and bottom edge tiles
 813          */
 814         OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
 815         OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 816                         A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 817
 818         update_vsc_pipe(ctx);
 819
 820         if (use_hw_binning(ctx)) {
 821                 /* mark the end of the binning cmds: */
 822                 fd_ringmarker_mark(ctx->binning_end);
 823
 824                 /* emit hw binning pass: */
 825                 emit_binning_pass(ctx);
 826
 827                 patch_draws(ctx, USE_VISIBILITY);
 828         } else {
 829                 patch_draws(ctx, IGNORE_VISIBILITY);
 830         }
 831
 832         rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 833                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
 834
 835         patch_rbrc(ctx, rb_render_control);
 836 }
 837
 838 /* before mem2gmem */
 839 static void
 840 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 841 {
 842         struct fd_ringbuffer *ring = ctx->ring;
 843         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 844         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 845         uint32_t reg;
 846
 847         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
 848         reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 849         if (pfb->zsbuf) {
 850                 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 851         }
 852         OUT_RING(ring, reg);
 853         if (pfb->zsbuf) {
 854                 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
 855                 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 856         } else {
 857                 OUT_RING(ring, 0x00000000);
 858         }
 859
 860         if (ctx->needs_rb_fbd) {
 861                 fd_wfi(ctx, ring);
 862                 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 863                 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 864                                 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 865                 ctx->needs_rb_fbd = false;
 866         }
 867
 868         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 869         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 870                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 871 }
 872
 873 /* before IB to rendering cmds: */
 874 static void
 875 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 876 {
 877         struct fd3_context *fd3_ctx = fd3_context(ctx);
 878         struct fd_ringbuffer *ring = ctx->ring;
 879         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 880         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 881
 882         uint32_t x1 = tile->xoff;
 883         uint32_t y1 = tile->yoff;
 884         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 885         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 886
 887         if (use_hw_binning(ctx)) {
 888                 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
 889
 890                 assert(pipe->w * pipe->h);
 891
 892                 fd_event_write(ctx, ring, HLSQ_FLUSH);
 893                 fd_wfi(ctx, ring);
 894
 895                 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 896                 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
 897                                 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
 898
 899
 900                 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
 901                 OUT_RELOC(ring, pipe->bo, 0, 0, 0);    /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
 902                 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
 903                                 (tile->p * 4), 0, 0);
 904         } else {
 905                 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 906                 OUT_RING(ring, 0x00000000);
 907         }
 908
 909         OUT_PKT3(ring, CP_SET_BIN, 3);
 910         OUT_RING(ring, 0x00000000);
 911         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 912         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 913
 914         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
 915
 916         /* setup scissor/offset for current tile: */
 917         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 918         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
 919                         A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
 920
 921         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 922         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 923                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 924         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 925                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 926 }
 927
 928 void
 929 fd3_gmem_init(struct pipe_context *pctx)
 930 {
 931         struct fd_context *ctx = fd_context(pctx);
 932
 933         ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
 934         ctx->emit_tile_init = fd3_emit_tile_init;
 935         ctx->emit_tile_prep = fd3_emit_tile_prep;
 936         ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
 937         ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
 938         ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
 939 }