src/gallium/drivers/freedreno/a3xx/fd3_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd3_gmem.h"
  40 #include "fd3_context.h"
  41 #include "fd3_emit.h"
  42 #include "fd3_program.h"
  43 #include "fd3_format.h"
  44 #include "fd3_zsa.h"
  45
  46 static void
  47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  48                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  49 {
  50         enum a3xx_tile_mode tile_mode;
  51         unsigned i;
  52
  53         if (bin_w) {
  54                 tile_mode = TILE_32X32;
  55         } else {
  56                 tile_mode = LINEAR;
  57         }
  58
  59         for (i = 0; i < 4; i++) {
  60                 enum a3xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 bool srgb = false;
  63                 struct fd_resource *rsc = NULL;
  64                 struct fd_resource_slice *slice = NULL;
  65                 uint32_t stride = 0;
  66                 uint32_t base = 0;
  67                 uint32_t offset = 0;
  68
  69                 if ((i < nr_bufs) && bufs[i]) {
  70                         struct pipe_surface *psurf = bufs[i];
  71
  72                         rsc = fd_resource(psurf->texture);
  73                         slice = fd_resource_slice(rsc, psurf->u.tex.level);
  74                         format = fd3_pipe2color(psurf->format);
  75                         swap = fd3_pipe2swap(psurf->format);
  76                         srgb = util_format_is_srgb(psurf->format);
  77
  78                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  79
  80                         offset = fd_resource_offset(rsc, psurf->u.tex.level,
  81                                         psurf->u.tex.first_layer);
  82
  83                         if (bin_w) {
  84                                 stride = bin_w * rsc->cpp;
  85
  86                                 if (bases) {
  87                                         base = bases[i];
  88                                 }
  89                         } else {
  90                                 stride = slice->pitch * rsc->cpp;
  91                         }
  92                 }
  93
  94                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
  95                 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  96                                 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
  97                                 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  98                                 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
  99                                 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
 100                 if (bin_w || (i >= nr_bufs)) {
 101                         OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
 102                 } else {
 103                         OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
 104                 }
 105
 106                 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
 107                 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
 108                                                         A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
 109                                                                         fd3_fs_output_format(bufs[i]->format))));
 110         }
 111 }
 112
 113 static uint32_t
 114 depth_base(struct fd_context *ctx)
 115 {
 116         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 117         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 118         uint32_t cpp = 4;
 119         if (pfb->cbufs[0]) {
 120                 struct fd_resource *rsc =
 121                                 fd_resource(pfb->cbufs[0]->texture);
 122                 cpp = rsc->cpp;
 123         }
 124         return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 125 }
 126
 127 static bool
 128 use_hw_binning(struct fd_context *ctx)
 129 {
 130         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 131
 132         /* workaround: combining scissor optimization and hw binning
 133          * seems problematic.  Seems like we end up with a mismatch
 134          * between binning pass and rendering pass, wrt. where the hw
 135          * thinks the vertices belong.  And the blob driver doesn't
 136          * seem to implement anything like scissor optimization, so
 137          * not entirely sure what I might be missing.
 138          *
 139          * But scissor optimization is mainly for window managers,
 140          * which don't have many vertices (and therefore doesn't
 141          * benefit much from binning pass).
 142          *
 143          * So for now just disable binning if scissor optimization is
 144          * used.
 145          */
 146         if (gmem->minx || gmem->miny)
 147                 return false;
 148
 149         return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
 150 }
 151
 152 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
 153 static void update_vsc_pipe(struct fd_context *ctx);
 154 static void
 155 emit_binning_workaround(struct fd_context *ctx)
 156 {
 157         struct fd3_context *fd3_ctx = fd3_context(ctx);
 158         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 159         struct fd_ringbuffer *ring = ctx->ring;
 160         struct fd3_emit emit = {
 161                         .vtx = &fd3_ctx->solid_vbuf_state,
 162                         .prog = &ctx->solid_prog,
 163                         .key = {
 164                                 .half_precision = true,
 165                         },
 166         };
 167
 168         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
 169         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 170                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 171         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
 172                         A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 173                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 174
 175         OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 176         OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 177                         A3XX_RB_COPY_CONTROL_MODE(0) |
 178                         A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
 179         OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
 180         OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
 181         OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 182                         A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
 183                         A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
 184                         A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 185                         A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
 186
 187         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 188         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 189                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 190                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 191
 192         fd3_program_emit(ring, &emit);
 193         fd3_emit_vertex_bufs(ring, &emit);
 194
 195         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
 196         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 197                         A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
 198                         A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
 199                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 200         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 201                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
 202         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 203         OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
 204
 205         OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
 206         OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
 207                         A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
 208
 209         OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
 210         OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 211                         A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 212                         A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
 213
 214         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 215         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 216
 217         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 218         OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 219                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 220                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 221                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 222                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 223                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 224                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 225                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 226
 227         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 228         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
 229
 230         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 231         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 232         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 233         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 234         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 235
 236         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 237         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 238                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 239                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 240                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 241
 242         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 243         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 244                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
 245         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
 246                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
 247
 248         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 249         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 250                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 251         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
 252                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
 253
 254         fd_wfi(ctx, ring);
 255         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 256         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
 257         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
 258         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
 259         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
 260         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 261         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 262
 263         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 264         OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
 265                         A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
 266                         A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
 267                         A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
 268                         A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
 269
 270         OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
 271         OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
 272                         A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
 273
 274         OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
 275         OUT_RING(ring, 0x00000000);   /* viz query info. */
 276         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
 277                                                 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
 278         OUT_RING(ring, 2);            /* NumIndices */
 279         OUT_RING(ring, 2);
 280         OUT_RING(ring, 1);
 281         fd_reset_wfi(ctx);
 282
 283         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
 284         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
 285
 286         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 287         OUT_RING(ring, 0x00000000);
 288
 289         fd_wfi(ctx, ring);
 290         OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
 291         OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 292                         A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 293
 294         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 295         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 296                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 297                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 298
 299         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 300         OUT_RING(ring, 0x00000000);
 301 }
 302
 303 /* transfer from gmem to system memory (ie. normal RAM) */
 304
 305 static void
 306 emit_gmem2mem_surf(struct fd_context *ctx,
 307                 enum adreno_rb_copy_control_mode mode,
 308                 uint32_t base, struct pipe_surface *psurf)
 309 {
 310         struct fd_ringbuffer *ring = ctx->ring;
 311         struct fd_resource *rsc = fd_resource(psurf->texture);
 312         struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
 313         uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
 314                         psurf->u.tex.first_layer);
 315
 316         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 317
 318         OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 319         OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 320                         A3XX_RB_COPY_CONTROL_MODE(mode) |
 321                         A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
 322
 323         OUT_RELOCW(ring, rsc->bo, offset, 0, -1);    /* RB_COPY_DEST_BASE */
 324         OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 325         OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 326                         A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
 327                         A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 328                         A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 329                         A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf->format)));
 330
 331         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 332                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 333 }
 334
 335 static void
 336 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 337 {
 338         struct fd3_context *fd3_ctx = fd3_context(ctx);
 339         struct fd_ringbuffer *ring = ctx->ring;
 340         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 341         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 342         struct fd3_emit emit = {
 343                         .vtx = &fd3_ctx->solid_vbuf_state,
 344                         .prog = &ctx->solid_prog,
 345                         .key = {
 346                                 .half_precision = fd3_half_precision(format),
 347                         },
 348                         .format = format,
 349         };
 350
 351         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 352         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 353
 354         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 355         OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 356                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 357                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 358                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 359                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 360                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 361                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 362                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 363
 364         OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 365         OUT_RING(ring, 0xff000000 |
 366                         A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 367                         A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 368                         A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 369         OUT_RING(ring, 0xff000000 |
 370                         A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 371                         A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 372                         A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 373
 374         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 375         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 376
 377         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 378         OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
 379
 380         fd_wfi(ctx, ring);
 381         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 382         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
 383         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
 384         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
 385         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
 386         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 387         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 388
 389         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 390         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 391                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 392
 393         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 394         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 395                         A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 396                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 397                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
 398
 399         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 400         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 401                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 402                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 403
 404         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 405         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 406                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 407                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 408                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 409
 410         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 411         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 412                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 413         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 414                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 415
 416         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 417         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 418         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 419         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 420         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 421
 422         fd3_program_emit(ring, &emit);
 423         fd3_emit_vertex_bufs(ring, &emit);
 424
 425         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 426                 uint32_t base = depth_base(ctx);
 427                 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 428         }
 429
 430         if (ctx->resolve & FD_BUFFER_COLOR) {
 431                 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, 0, pfb->cbufs[0]);
 432         }
 433
 434         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 435         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 436                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 437
 438         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 439         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 440                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 441                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 442 }
 443
 444 /* transfer from system memory to gmem */
 445
 446 static void
 447 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
 448                 struct pipe_surface *psurf, uint32_t bin_w)
 449 {
 450         struct fd_ringbuffer *ring = ctx->ring;
 451
 452         emit_mrt(ring, 1, &psurf, &base, bin_w);
 453
 454         fd3_emit_gmem_restore_tex(ring, psurf);
 455
 456         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 457                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 458 }
 459
 460 static void
 461 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 462 {
 463         struct fd3_context *fd3_ctx = fd3_context(ctx);
 464         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 465         struct fd_ringbuffer *ring = ctx->ring;
 466         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 467         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 468         struct fd3_emit emit = {
 469                         .vtx = &fd3_ctx->blit_vbuf_state,
 470                         .prog = &ctx->blit_prog[0],
 471                         .sprite_coord_enable = 1,
 472                         .key = {
 473                                 .half_precision = fd3_half_precision(format),
 474                         },
 475                         .format = format,
 476         };
 477         float x0, y0, x1, y1;
 478         unsigned bin_w = tile->bin_w;
 479         unsigned bin_h = tile->bin_h;
 480         unsigned i;
 481
 482         /* write texture coordinates to vertexbuf: */
 483         x0 = ((float)tile->xoff) / ((float)pfb->width);
 484         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 485         y0 = ((float)tile->yoff) / ((float)pfb->height);
 486         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 487
 488         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 489         OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 490         OUT_RING(ring, fui(x0));
 491         OUT_RING(ring, fui(y0));
 492         OUT_RING(ring, fui(x1));
 493         OUT_RING(ring, fui(y1));
 494
 495         for (i = 0; i < 4; i++) {
 496                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 497                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 498                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
 499                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 500
 501                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 502                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 503                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 504                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 505                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 506                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 507                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 508         }
 509
 510         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 511         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
 512                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 513
 514         fd_wfi(ctx, ring);
 515         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 516         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 517
 518         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 519         OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);   /* GRAS_CL_CLIP_CNTL */
 520
 521         fd_wfi(ctx, ring);
 522         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 523         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
 524         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
 525         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
 526         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
 527         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 528         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 529
 530         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 531         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 532                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 533         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 534                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 535
 536         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 537         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 538                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 539         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 540                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 541
 542         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 543         OUT_RING(ring, 0x2 |
 544                         A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 545                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 546                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 547                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 548                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 549                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 550                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 551                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 552
 553         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 554         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 555                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 556                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 557
 558         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 559         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
 560                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 561                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 562                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 563
 564         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 565         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 566         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 567         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 568         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 569
 570         fd3_program_emit(ring, &emit);
 571         fd3_emit_vertex_bufs(ring, &emit);
 572
 573         /* for gmem pitch/base calculations, we need to use the non-
 574          * truncated tile sizes:
 575          */
 576         bin_w = gmem->bin_w;
 577         bin_h = gmem->bin_h;
 578
 579         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 580                 emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
 581
 582         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
 583                 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
 584
 585         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 586         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 587                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 588                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 589 }
 590
 591 static void
 592 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 593 {
 594         unsigned i;
 595         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 596                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 597                 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
 598         }
 599         util_dynarray_resize(&ctx->draw_patches, 0);
 600 }
 601
 602 static void
 603 patch_rbrc(struct fd_context *ctx, uint32_t val)
 604 {
 605         struct fd3_context *fd3_ctx = fd3_context(ctx);
 606         unsigned i;
 607         for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
 608                 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
 609                 *patch->cs = patch->val | val;
 610         }
 611         util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
 612 }
 613
 614 /* for rendering directly to system memory: */
 615 static void
 616 fd3_emit_sysmem_prep(struct fd_context *ctx)
 617 {
 618         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 619         struct fd_ringbuffer *ring = ctx->ring;
 620         uint32_t pitch = 0;
 621
 622         if (pfb->cbufs[0]) {
 623                 struct pipe_surface *psurf = pfb->cbufs[0];
 624                 unsigned lvl = psurf->u.tex.level;
 625                 pitch = fd_resource(psurf->texture)->slices[lvl].pitch;
 626         }
 627
 628         fd3_emit_restore(ctx);
 629
 630         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 631         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 632                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 633
 634         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
 635
 636         /* setup scissor/offset for current tile: */
 637         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 638         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
 639                         A3XX_RB_WINDOW_OFFSET_Y(0));
 640
 641         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 642         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 643                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 644         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 645                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 646
 647         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 648         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 649                         A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
 650                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 651
 652         patch_draws(ctx, IGNORE_VISIBILITY);
 653         patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
 654 }
 655
 656 static void
 657 update_vsc_pipe(struct fd_context *ctx)
 658 {
 659         struct fd3_context *fd3_ctx = fd3_context(ctx);
 660         struct fd_ringbuffer *ring = ctx->ring;
 661         int i;
 662
 663         OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
 664         OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 665
 666         for (i = 0; i < 8; i++) {
 667                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 668
 669                 if (!pipe->bo) {
 670                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 671                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 672                 }
 673
 674                 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
 675                 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
 676                                 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
 677                                 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
 678                                 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
 679                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
 680                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
 681         }
 682 }
 683
 684 static void
 685 emit_binning_pass(struct fd_context *ctx)
 686 {
 687         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 688         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 689         struct fd_ringbuffer *ring = ctx->ring;
 690         int i;
 691
 692         uint32_t x1 = gmem->minx;
 693         uint32_t y1 = gmem->miny;
 694         uint32_t x2 = gmem->minx + gmem->width - 1;
 695         uint32_t y2 = gmem->miny + gmem->height - 1;
 696
 697         if (ctx->screen->gpu_id == 320) {
 698                 emit_binning_workaround(ctx);
 699                 fd_wfi(ctx, ring);
 700                 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 701                 OUT_RING(ring, 0x00007fff);
 702         }
 703
 704         OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
 705         OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
 706
 707         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 708         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 709                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 710                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 711
 712         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 713         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 714                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 715
 716         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 717         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 718                         A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 719                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 720
 721         /* setup scissor/offset for whole screen: */
 722         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 723         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
 724                         A3XX_RB_WINDOW_OFFSET_Y(y1));
 725
 726         OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
 727         OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
 728
 729         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 730         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 731                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 732         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 733                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 734
 735         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 736         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 737                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 738
 739         for (i = 0; i < 4; i++) {
 740                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 741                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
 742                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
 743                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
 744         }
 745
 746         OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 747         OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
 748                         A3XX_PC_VSTREAM_CONTROL_N(0));
 749
 750         /* emit IB to binning drawcmds: */
 751         OUT_IB(ring, ctx->binning_start, ctx->binning_end);
 752         fd_reset_wfi(ctx);
 753
 754         fd_wfi(ctx, ring);
 755
 756         /* and then put stuff back the way it was: */
 757
 758         OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
 759         OUT_RING(ring, 0x00000000);
 760
 761         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 762         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
 763                         A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
 764                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 765                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 766
 767         OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
 768         OUT_RING(ring, 0x00000000);
 769
 770         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 771         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 772                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 773                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 774
 775         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
 776         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 777                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 778         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 779                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 780                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 781
 782         fd_event_write(ctx, ring, CACHE_FLUSH);
 783         fd_wfi(ctx, ring);
 784
 785         if (ctx->screen->gpu_id == 320) {
 786                 /* dummy-draw workaround: */
 787                 OUT_PKT3(ring, CP_DRAW_INDX, 3);
 788                 OUT_RING(ring, 0x00000000);
 789                 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
 790                                                         INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
 791                 OUT_RING(ring, 0);             /* NumIndices */
 792                 fd_reset_wfi(ctx);
 793         }
 794
 795         OUT_PKT3(ring, CP_NOP, 4);
 796         OUT_RING(ring, 0x00000000);
 797         OUT_RING(ring, 0x00000000);
 798         OUT_RING(ring, 0x00000000);
 799         OUT_RING(ring, 0x00000000);
 800
 801         fd_wfi(ctx, ring);
 802
 803         if (ctx->screen->gpu_id == 320) {
 804                 emit_binning_workaround(ctx);
 805         }
 806 }
 807
 808 /* before first tile */
 809 static void
 810 fd3_emit_tile_init(struct fd_context *ctx)
 811 {
 812         struct fd_ringbuffer *ring = ctx->ring;
 813         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 814         uint32_t rb_render_control;
 815
 816         fd3_emit_restore(ctx);
 817
 818         /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
 819          * at the right and bottom edge tiles
 820          */
 821         OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
 822         OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 823                         A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 824
 825         update_vsc_pipe(ctx);
 826
 827         if (use_hw_binning(ctx)) {
 828                 /* mark the end of the binning cmds: */
 829                 fd_ringmarker_mark(ctx->binning_end);
 830
 831                 /* emit hw binning pass: */
 832                 emit_binning_pass(ctx);
 833
 834                 patch_draws(ctx, USE_VISIBILITY);
 835         } else {
 836                 patch_draws(ctx, IGNORE_VISIBILITY);
 837         }
 838
 839         rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 840                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
 841
 842         patch_rbrc(ctx, rb_render_control);
 843 }
 844
 845 /* before mem2gmem */
 846 static void
 847 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 848 {
 849         struct fd_ringbuffer *ring = ctx->ring;
 850         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 851         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 852         uint32_t reg;
 853
 854         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
 855         reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 856         if (pfb->zsbuf) {
 857                 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 858         }
 859         OUT_RING(ring, reg);
 860         if (pfb->zsbuf) {
 861                 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
 862                 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 863         } else {
 864                 OUT_RING(ring, 0x00000000);
 865         }
 866
 867         if (ctx->needs_rb_fbd) {
 868                 fd_wfi(ctx, ring);
 869                 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 870                 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 871                                 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 872                 ctx->needs_rb_fbd = false;
 873         }
 874
 875         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 876         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 877                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 878 }
 879
 880 /* before IB to rendering cmds: */
 881 static void
 882 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 883 {
 884         struct fd3_context *fd3_ctx = fd3_context(ctx);
 885         struct fd_ringbuffer *ring = ctx->ring;
 886         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 887         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 888
 889         uint32_t x1 = tile->xoff;
 890         uint32_t y1 = tile->yoff;
 891         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 892         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 893
 894         if (use_hw_binning(ctx)) {
 895                 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
 896
 897                 assert(pipe->w * pipe->h);
 898
 899                 fd_event_write(ctx, ring, HLSQ_FLUSH);
 900                 fd_wfi(ctx, ring);
 901
 902                 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 903                 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
 904                                 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
 905
 906
 907                 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
 908                 OUT_RELOC(ring, pipe->bo, 0, 0, 0);    /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
 909                 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
 910                                 (tile->p * 4), 0, 0);
 911         } else {
 912                 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 913                 OUT_RING(ring, 0x00000000);
 914         }
 915
 916         OUT_PKT3(ring, CP_SET_BIN, 3);
 917         OUT_RING(ring, 0x00000000);
 918         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 919         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 920
 921         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
 922
 923         /* setup scissor/offset for current tile: */
 924         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 925         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
 926                         A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
 927
 928         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 929         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 930                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 931         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 932                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 933 }
 934
 935 void
 936 fd3_gmem_init(struct pipe_context *pctx)
 937 {
 938         struct fd_context *ctx = fd_context(pctx);
 939
 940         ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
 941         ctx->emit_tile_init = fd3_emit_tile_init;
 942         ctx->emit_tile_prep = fd3_emit_tile_prep;
 943         ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
 944         ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
 945         ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
 946 }