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freedreno: helper to calc layer/level offset
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static void
47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
48 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
49 {
50 enum a3xx_tile_mode tile_mode;
51 unsigned i;
52
53 if (bin_w) {
54 tile_mode = TILE_32X32;
55 } else {
56 tile_mode = LINEAR;
57 }
58
59 for (i = 0; i < 4; i++) {
60 enum a3xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool srgb = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t base = 0;
67 uint32_t offset = 0;
68
69 if ((i < nr_bufs) && bufs[i]) {
70 struct pipe_surface *psurf = bufs[i];
71
72 rsc = fd_resource(psurf->texture);
73 slice = fd_resource_slice(rsc, psurf->u.tex.level);
74 format = fd3_pipe2color(psurf->format);
75 swap = fd3_pipe2swap(psurf->format);
76 srgb = util_format_is_srgb(psurf->format);
77
78 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
79
80 offset = fd_resource_offset(rsc, psurf->u.tex.level,
81 psurf->u.tex.first_layer);
82
83 if (bin_w) {
84 stride = bin_w * rsc->cpp;
85
86 if (bases) {
87 base = bases[i];
88 }
89 } else {
90 stride = slice->pitch * rsc->cpp;
91 }
92 }
93
94 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
95 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
96 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
97 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
98 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
99 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
100 if (bin_w || (i >= nr_bufs)) {
101 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
102 } else {
103 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
104 }
105
106 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
107 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
108 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
109 fd3_fs_output_format(bufs[i]->format))));
110 }
111 }
112
113 static uint32_t
114 depth_base(struct fd_context *ctx)
115 {
116 struct fd_gmem_stateobj *gmem = &ctx->gmem;
117 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
118 uint32_t cpp = 4;
119 if (pfb->cbufs[0]) {
120 struct fd_resource *rsc =
121 fd_resource(pfb->cbufs[0]->texture);
122 cpp = rsc->cpp;
123 }
124 return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
125 }
126
127 static bool
128 use_hw_binning(struct fd_context *ctx)
129 {
130 struct fd_gmem_stateobj *gmem = &ctx->gmem;
131
132 /* workaround: combining scissor optimization and hw binning
133 * seems problematic. Seems like we end up with a mismatch
134 * between binning pass and rendering pass, wrt. where the hw
135 * thinks the vertices belong. And the blob driver doesn't
136 * seem to implement anything like scissor optimization, so
137 * not entirely sure what I might be missing.
138 *
139 * But scissor optimization is mainly for window managers,
140 * which don't have many vertices (and therefore doesn't
141 * benefit much from binning pass).
142 *
143 * So for now just disable binning if scissor optimization is
144 * used.
145 */
146 if (gmem->minx || gmem->miny)
147 return false;
148
149 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
150 }
151
152 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
153 static void update_vsc_pipe(struct fd_context *ctx);
154 static void
155 emit_binning_workaround(struct fd_context *ctx)
156 {
157 struct fd3_context *fd3_ctx = fd3_context(ctx);
158 struct fd_gmem_stateobj *gmem = &ctx->gmem;
159 struct fd_ringbuffer *ring = ctx->ring;
160 struct fd3_emit emit = {
161 .vtx = &fd3_ctx->solid_vbuf_state,
162 .prog = &ctx->solid_prog,
163 .key = {
164 .half_precision = true,
165 },
166 };
167
168 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
169 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
170 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
171 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
172 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
173 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
174
175 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
176 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
177 A3XX_RB_COPY_CONTROL_MODE(0) |
178 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
179 OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
180 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
181 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
182 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
183 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
184 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
185 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
186
187 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
188 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
189 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
190 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
191
192 fd3_program_emit(ring, &emit);
193 fd3_emit_vertex_bufs(ring, &emit);
194
195 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
196 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
197 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
198 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
199 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
200 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
201 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
202 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
203 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
204
205 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
206 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
207 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
208
209 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
210 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
211 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
212 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
213
214 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
215 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
216
217 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
218 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
219 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
220 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
221 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
222 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
223 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
224 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
225 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
226
227 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
228 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
229
230 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
231 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
232 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
233 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
234 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
235
236 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
237 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
238 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
239 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
240 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
241
242 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
243 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
244 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
245 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
246 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
247
248 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
249 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
250 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
251 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
252 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
253
254 fd_wfi(ctx, ring);
255 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
256 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
257 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
258 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
259 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
260 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
261 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
262
263 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
264 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
265 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
266 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
267 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
268 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
269
270 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
271 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
272 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
273
274 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
275 OUT_RING(ring, 0x00000000); /* viz query info. */
276 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
277 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY));
278 OUT_RING(ring, 2); /* NumIndices */
279 OUT_RING(ring, 2);
280 OUT_RING(ring, 1);
281 fd_reset_wfi(ctx);
282
283 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
284 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
285
286 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
287 OUT_RING(ring, 0x00000000);
288
289 fd_wfi(ctx, ring);
290 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
291 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
292 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
293
294 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
295 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
296 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
297 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
298
299 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
300 OUT_RING(ring, 0x00000000);
301 }
302
303 /* transfer from gmem to system memory (ie. normal RAM) */
304
305 static void
306 emit_gmem2mem_surf(struct fd_context *ctx,
307 enum adreno_rb_copy_control_mode mode,
308 uint32_t base, struct pipe_surface *psurf)
309 {
310 struct fd_ringbuffer *ring = ctx->ring;
311 struct fd_resource *rsc = fd_resource(psurf->texture);
312 struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
313 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
314 psurf->u.tex.first_layer);
315
316 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
317
318 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
319 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
320 A3XX_RB_COPY_CONTROL_MODE(mode) |
321 A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
322
323 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
324 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
325 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
326 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
327 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
328 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
329 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf->format)));
330
331 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
332 DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
333 }
334
335 static void
336 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
337 {
338 struct fd3_context *fd3_ctx = fd3_context(ctx);
339 struct fd_ringbuffer *ring = ctx->ring;
340 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
341 enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
342 struct fd3_emit emit = {
343 .vtx = &fd3_ctx->solid_vbuf_state,
344 .prog = &ctx->solid_prog,
345 .key = {
346 .half_precision = fd3_half_precision(format),
347 },
348 .format = format,
349 };
350
351 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
352 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
353
354 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
355 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
356 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
357 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
358 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
359 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
360 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
361 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
362 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
363
364 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
365 OUT_RING(ring, 0xff000000 |
366 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
367 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
368 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
369 OUT_RING(ring, 0xff000000 |
370 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
371 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
372 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
373
374 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
375 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
376
377 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
378 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
379
380 fd_wfi(ctx, ring);
381 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
382 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
383 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
384 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
385 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
386 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
387 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
388
389 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
390 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
391 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
392
393 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
394 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
395 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
396 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
397 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
398
399 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
400 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
401 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
402 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
403
404 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
405 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
406 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
407 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
408 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
409
410 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
411 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
412 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
413 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
414 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
415
416 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
417 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
418 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
419 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
420 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
421
422 fd3_program_emit(ring, &emit);
423 fd3_emit_vertex_bufs(ring, &emit);
424
425 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
426 uint32_t base = depth_base(ctx);
427 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
428 }
429
430 if (ctx->resolve & FD_BUFFER_COLOR) {
431 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, 0, pfb->cbufs[0]);
432 }
433
434 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
435 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
436 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
437
438 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
439 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
440 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
441 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
442 }
443
444 /* transfer from system memory to gmem */
445
446 static void
447 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
448 struct pipe_surface *psurf, uint32_t bin_w)
449 {
450 struct fd_ringbuffer *ring = ctx->ring;
451
452 emit_mrt(ring, 1, &psurf, &base, bin_w);
453
454 fd3_emit_gmem_restore_tex(ring, psurf);
455
456 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
457 DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
458 }
459
460 static void
461 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
462 {
463 struct fd3_context *fd3_ctx = fd3_context(ctx);
464 struct fd_gmem_stateobj *gmem = &ctx->gmem;
465 struct fd_ringbuffer *ring = ctx->ring;
466 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
467 enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
468 struct fd3_emit emit = {
469 .vtx = &fd3_ctx->blit_vbuf_state,
470 .prog = &ctx->blit_prog,
471 .key = {
472 .half_precision = fd3_half_precision(format),
473 },
474 .format = format,
475 };
476 float x0, y0, x1, y1;
477 unsigned bin_w = tile->bin_w;
478 unsigned bin_h = tile->bin_h;
479 unsigned i;
480
481 /* write texture coordinates to vertexbuf: */
482 x0 = ((float)tile->xoff) / ((float)pfb->width);
483 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
484 y0 = ((float)tile->yoff) / ((float)pfb->height);
485 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
486
487 OUT_PKT3(ring, CP_MEM_WRITE, 5);
488 OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
489 OUT_RING(ring, fui(x0));
490 OUT_RING(ring, fui(y0));
491 OUT_RING(ring, fui(x1));
492 OUT_RING(ring, fui(y1));
493
494 for (i = 0; i < 4; i++) {
495 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
496 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
497 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
498 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
499
500 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
501 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
502 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
503 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
504 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
505 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
506 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
507 }
508
509 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
510 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
511 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
512
513 fd_wfi(ctx, ring);
514 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
515 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
516
517 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
518 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
519
520 fd_wfi(ctx, ring);
521 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
522 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
523 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
524 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
525 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
526 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
527 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
528
529 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
530 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
531 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
532 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
533 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
534
535 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
536 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
537 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
538 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
539 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
540
541 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
542 OUT_RING(ring, 0x2 |
543 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
544 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
545 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
546 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
547 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
548 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
549 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
550 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
551
552 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
553 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
554 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
555 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
556
557 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
558 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
559 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
560 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
561 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
562
563 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
564 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
565 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
566 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
567 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
568
569 fd3_program_emit(ring, &emit);
570 fd3_emit_vertex_bufs(ring, &emit);
571
572 /* for gmem pitch/base calculations, we need to use the non-
573 * truncated tile sizes:
574 */
575 bin_w = gmem->bin_w;
576 bin_h = gmem->bin_h;
577
578 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
579 emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
580
581 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
582 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
583
584 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
585 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
586 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
587 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
588 }
589
590 static void
591 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
592 {
593 unsigned i;
594 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
595 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
596 *patch->cs = patch->val | DRAW(0, 0, 0, vismode);
597 }
598 util_dynarray_resize(&ctx->draw_patches, 0);
599 }
600
601 static void
602 patch_rbrc(struct fd_context *ctx, uint32_t val)
603 {
604 struct fd3_context *fd3_ctx = fd3_context(ctx);
605 unsigned i;
606 for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
607 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
608 *patch->cs = patch->val | val;
609 }
610 util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
611 }
612
613 /* for rendering directly to system memory: */
614 static void
615 fd3_emit_sysmem_prep(struct fd_context *ctx)
616 {
617 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
618 struct fd_ringbuffer *ring = ctx->ring;
619 uint32_t pitch = 0;
620
621 if (pfb->cbufs[0]) {
622 struct pipe_surface *psurf = pfb->cbufs[0];
623 unsigned lvl = psurf->u.tex.level;
624 pitch = fd_resource(psurf->texture)->slices[lvl].pitch;
625 }
626
627 fd3_emit_restore(ctx);
628
629 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
630 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
631 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
632
633 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
634
635 /* setup scissor/offset for current tile: */
636 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
637 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
638 A3XX_RB_WINDOW_OFFSET_Y(0));
639
640 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
641 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
642 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
643 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
644 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
645
646 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
647 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
648 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
649 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
650
651 patch_draws(ctx, IGNORE_VISIBILITY);
652 patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
653 }
654
655 static void
656 update_vsc_pipe(struct fd_context *ctx)
657 {
658 struct fd3_context *fd3_ctx = fd3_context(ctx);
659 struct fd_ringbuffer *ring = ctx->ring;
660 int i;
661
662 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
663 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
664
665 for (i = 0; i < 8; i++) {
666 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
667
668 if (!pipe->bo) {
669 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
670 DRM_FREEDRENO_GEM_TYPE_KMEM);
671 }
672
673 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
674 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
675 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
676 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
677 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
678 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
679 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
680 }
681 }
682
683 static void
684 emit_binning_pass(struct fd_context *ctx)
685 {
686 struct fd_gmem_stateobj *gmem = &ctx->gmem;
687 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
688 struct fd_ringbuffer *ring = ctx->ring;
689 int i;
690
691 uint32_t x1 = gmem->minx;
692 uint32_t y1 = gmem->miny;
693 uint32_t x2 = gmem->minx + gmem->width - 1;
694 uint32_t y2 = gmem->miny + gmem->height - 1;
695
696 if (ctx->screen->gpu_id == 320) {
697 emit_binning_workaround(ctx);
698 fd_wfi(ctx, ring);
699 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
700 OUT_RING(ring, 0x00007fff);
701 }
702
703 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
704 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
705
706 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
707 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
708 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
709 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
710
711 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
712 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
713 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
714
715 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
716 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
717 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
718 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
719
720 /* setup scissor/offset for whole screen: */
721 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
722 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
723 A3XX_RB_WINDOW_OFFSET_Y(y1));
724
725 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
726 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
727
728 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
729 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
730 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
731 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
732 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
733
734 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
735 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
736 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
737
738 for (i = 0; i < 4; i++) {
739 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
740 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
741 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
742 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
743 }
744
745 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
746 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
747 A3XX_PC_VSTREAM_CONTROL_N(0));
748
749 /* emit IB to binning drawcmds: */
750 OUT_IB(ring, ctx->binning_start, ctx->binning_end);
751 fd_reset_wfi(ctx);
752
753 fd_wfi(ctx, ring);
754
755 /* and then put stuff back the way it was: */
756
757 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
758 OUT_RING(ring, 0x00000000);
759
760 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
761 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
762 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
763 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
764 A3XX_SP_SP_CTRL_REG_L0MODE(0));
765
766 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
767 OUT_RING(ring, 0x00000000);
768
769 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
770 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
771 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
772 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
773
774 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
775 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
776 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
777 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
778 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
779 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
780
781 fd_event_write(ctx, ring, CACHE_FLUSH);
782 fd_wfi(ctx, ring);
783
784 if (ctx->screen->gpu_id == 320) {
785 /* dummy-draw workaround: */
786 OUT_PKT3(ring, CP_DRAW_INDX, 3);
787 OUT_RING(ring, 0x00000000);
788 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
789 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
790 OUT_RING(ring, 0); /* NumIndices */
791 fd_reset_wfi(ctx);
792 }
793
794 OUT_PKT3(ring, CP_NOP, 4);
795 OUT_RING(ring, 0x00000000);
796 OUT_RING(ring, 0x00000000);
797 OUT_RING(ring, 0x00000000);
798 OUT_RING(ring, 0x00000000);
799
800 fd_wfi(ctx, ring);
801
802 if (ctx->screen->gpu_id == 320) {
803 emit_binning_workaround(ctx);
804 }
805 }
806
807 /* before first tile */
808 static void
809 fd3_emit_tile_init(struct fd_context *ctx)
810 {
811 struct fd_ringbuffer *ring = ctx->ring;
812 struct fd_gmem_stateobj *gmem = &ctx->gmem;
813 uint32_t rb_render_control;
814
815 fd3_emit_restore(ctx);
816
817 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
818 * at the right and bottom edge tiles
819 */
820 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
821 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
822 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
823
824 update_vsc_pipe(ctx);
825
826 if (use_hw_binning(ctx)) {
827 /* mark the end of the binning cmds: */
828 fd_ringmarker_mark(ctx->binning_end);
829
830 /* emit hw binning pass: */
831 emit_binning_pass(ctx);
832
833 patch_draws(ctx, USE_VISIBILITY);
834 } else {
835 patch_draws(ctx, IGNORE_VISIBILITY);
836 }
837
838 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
839 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
840
841 patch_rbrc(ctx, rb_render_control);
842 }
843
844 /* before mem2gmem */
845 static void
846 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
847 {
848 struct fd_ringbuffer *ring = ctx->ring;
849 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
850 struct fd_gmem_stateobj *gmem = &ctx->gmem;
851 uint32_t reg;
852
853 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
854 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
855 if (pfb->zsbuf) {
856 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
857 }
858 OUT_RING(ring, reg);
859 if (pfb->zsbuf) {
860 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
861 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
862 } else {
863 OUT_RING(ring, 0x00000000);
864 }
865
866 if (ctx->needs_rb_fbd) {
867 fd_wfi(ctx, ring);
868 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
869 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
870 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
871 ctx->needs_rb_fbd = false;
872 }
873
874 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
875 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
876 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
877 }
878
879 /* before IB to rendering cmds: */
880 static void
881 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
882 {
883 struct fd3_context *fd3_ctx = fd3_context(ctx);
884 struct fd_ringbuffer *ring = ctx->ring;
885 struct fd_gmem_stateobj *gmem = &ctx->gmem;
886 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
887
888 uint32_t x1 = tile->xoff;
889 uint32_t y1 = tile->yoff;
890 uint32_t x2 = tile->xoff + tile->bin_w - 1;
891 uint32_t y2 = tile->yoff + tile->bin_h - 1;
892
893 if (use_hw_binning(ctx)) {
894 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
895
896 assert(pipe->w * pipe->h);
897
898 fd_event_write(ctx, ring, HLSQ_FLUSH);
899 fd_wfi(ctx, ring);
900
901 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
902 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
903 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
904
905
906 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
907 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
908 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
909 (tile->p * 4), 0, 0);
910 } else {
911 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
912 OUT_RING(ring, 0x00000000);
913 }
914
915 OUT_PKT3(ring, CP_SET_BIN, 3);
916 OUT_RING(ring, 0x00000000);
917 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
918 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
919
920 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
921
922 /* setup scissor/offset for current tile: */
923 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
924 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
925 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
926
927 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
928 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
929 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
930 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
931 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
932 }
933
934 void
935 fd3_gmem_init(struct pipe_context *pctx)
936 {
937 struct fd_context *ctx = fd_context(pctx);
938
939 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
940 ctx->emit_tile_init = fd3_emit_tile_init;
941 ctx->emit_tile_prep = fd3_emit_tile_prep;
942 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
943 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
944 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
945 }