src/gallium/drivers/freedreno/a3xx/fd3_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd3_gmem.h"
  40 #include "fd3_context.h"
  41 #include "fd3_emit.h"
  42 #include "fd3_program.h"
  43 #include "fd3_util.h"
  44 #include "fd3_zsa.h"
  45
  46
  47 static void
  48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  49                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  50 {
  51         enum a3xx_tile_mode tile_mode;
  52         unsigned i;
  53
  54         if (bin_w) {
  55                 tile_mode = TILE_32X32;
  56         } else {
  57                 tile_mode = LINEAR;
  58         }
  59
  60         for (i = 0; i < 4; i++) {
  61                 enum a3xx_color_fmt format = 0;
  62                 enum a3xx_color_swap swap = WZYX;
  63                 struct fd_resource *rsc = NULL;
  64                 struct fd_resource_slice *slice = NULL;
  65                 uint32_t stride = 0;
  66                 uint32_t base = 0;
  67
  68                 if ((i < nr_bufs) && bufs[i]) {
  69                         struct pipe_surface *psurf = bufs[i];
  70
  71                         rsc = fd_resource(psurf->texture);
  72                         slice = &rsc->slices[psurf->u.tex.level];
  73                         format = fd3_pipe2color(psurf->format);
  74                         swap = fd3_pipe2swap(psurf->format);
  75
  76                         if (bin_w) {
  77                                 stride = bin_w * rsc->cpp;
  78
  79                                 if (bases) {
  80                                         base = bases[i] * rsc->cpp;
  81                                 }
  82                         } else {
  83                                 stride = slice->pitch * rsc->cpp;
  84                         }
  85                 }
  86
  87                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
  88                 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  89                                 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
  90                                 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  91                                 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
  92                 if (bin_w || (i >= nr_bufs)) {
  93                         OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
  94                 } else {
  95                         OUT_RELOCW(ring, rsc->bo, slice->offset, 0, -1);
  96                 }
  97
  98                 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
  99                 OUT_RING(ring, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format));
 100         }
 101 }
 102
 103 static uint32_t
 104 depth_base(struct fd_gmem_stateobj *gmem)
 105 {
 106         return align(gmem->bin_w * gmem->bin_h, 0x4000);
 107 }
 108
 109 static bool
 110 use_hw_binning(struct fd_context *ctx)
 111 {
 112         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 113         return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
 114 }
 115
 116 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
 117 static void update_vsc_pipe(struct fd_context *ctx);
 118 static void
 119 emit_binning_workaround(struct fd_context *ctx)
 120 {
 121         struct fd3_context *fd3_ctx = fd3_context(ctx);
 122         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 123         struct fd_ringbuffer *ring = ctx->ring;
 124
 125         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
 126         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 127                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 128         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
 129                         A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 130                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 131
 132         OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 133         OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 134                         A3XX_RB_COPY_CONTROL_MODE(0) |
 135                         A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
 136         OUT_RELOC(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
 137         OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
 138         OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 139                         A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
 140                         A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
 141                         A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 142                         A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
 143
 144         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 145         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 146                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 147                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 148
 149         fd_wfi(ctx, ring);
 150         fd3_program_emit(ring, &ctx->solid_prog, false);
 151
 152         fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
 153                         { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
 154                 }, 1);
 155
 156         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
 157         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 158                         A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
 159                         A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
 160                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 161         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 162                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
 163         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 164         OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
 165
 166         OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
 167         OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
 168                         A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
 169
 170         OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
 171         OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
 172                         A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
 173                         A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
 174
 175         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 176         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 177
 178         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 179         OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 180                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 181                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 182                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 183                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 184                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 185                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 186                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 187
 188         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 189         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
 190
 191         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 192         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 193         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 194         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 195         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 196
 197         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 198         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 199                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 200                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 201                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 202
 203         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 204         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 205                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
 206         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
 207                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
 208
 209         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 210         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 211                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 212         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
 213                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
 214
 215         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 216         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
 217         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
 218         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
 219         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
 220         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 221         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 222
 223         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 224         OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
 225                         A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
 226                         A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
 227                         A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
 228                         A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
 229
 230         OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
 231         OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
 232                         A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
 233
 234         OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
 235         OUT_RING(ring, 0x00000000);   /* viz query info. */
 236         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
 237                         INDEX_SIZE_32_BIT, IGNORE_VISIBILITY));
 238         OUT_RING(ring, 2);            /* NumIndices */
 239         OUT_RING(ring, 2);
 240         OUT_RING(ring, 1);
 241         fd_reset_wfi(ctx);
 242
 243         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
 244         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
 245
 246         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 247         OUT_RING(ring, 0x00000000);
 248
 249         fd_wfi(ctx, ring);
 250         OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
 251         OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 252                         A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 253
 254         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 255         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 256                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 257                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 258
 259         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 260         OUT_RING(ring, 0x00000000);
 261 }
 262
 263 /* transfer from gmem to system memory (ie. normal RAM) */
 264
 265 static void
 266 emit_gmem2mem_surf(struct fd_context *ctx,
 267                 enum adreno_rb_copy_control_mode mode,
 268                 uint32_t base, struct pipe_surface *psurf)
 269 {
 270         struct fd_ringbuffer *ring = ctx->ring;
 271         struct fd_resource *rsc = fd_resource(psurf->texture);
 272         struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
 273
 274         OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 275         OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 276                         A3XX_RB_COPY_CONTROL_MODE(mode) |
 277                         A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
 278         OUT_RELOCW(ring, rsc->bo, slice->offset, 0, -1);    /* RB_COPY_DEST_BASE */
 279         OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 280         OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 281                         A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
 282                         A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 283                         A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 284                         A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(psurf->format)));
 285
 286         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 287                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 288 }
 289
 290 static void
 291 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 292 {
 293         struct fd3_context *fd3_ctx = fd3_context(ctx);
 294         struct fd_ringbuffer *ring = ctx->ring;
 295         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 296
 297         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 298         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 299
 300         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 301         OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 302                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 303                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 304                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 305                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 306                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 307                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 308                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 309
 310         OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 311         OUT_RING(ring, 0xff000000 |
 312                         A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 313                         A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 314                         A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 315         OUT_RING(ring, 0xff000000 |
 316                         A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 317                         A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 318                         A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 319
 320         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 321         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 322
 323         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 324         OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
 325
 326         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 327         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
 328         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
 329         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
 330         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
 331         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 332         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 333
 334         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 335         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 336                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 337
 338         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 339         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 340                         A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 341                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 342                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
 343
 344         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 345         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 346                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 347                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 348
 349         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 350         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 351                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 352                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 353                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 354
 355         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 356         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 357                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 358         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 359                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 360
 361         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 362         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 363         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 364         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 365         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 366
 367         fd_wfi(ctx, ring);
 368         fd3_program_emit(ring, &ctx->solid_prog, false);
 369
 370         fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
 371                         { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
 372                 }, 1);
 373
 374         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 375                 uint32_t base = 0;
 376                 if (pfb->cbufs[0]) {
 377                         struct fd_resource *rsc =
 378                                         fd_resource(pfb->cbufs[0]->texture);
 379                         base = depth_base(&ctx->gmem) * rsc->cpp;
 380                 }
 381                 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 382         }
 383
 384         if (ctx->resolve & FD_BUFFER_COLOR) {
 385                 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, 0, pfb->cbufs[0]);
 386         }
 387
 388         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 389         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 390                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 391
 392         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 393         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 394                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 395                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 396 }
 397
 398 /* transfer from system memory to gmem */
 399
 400 static void
 401 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
 402                 struct pipe_surface *psurf, uint32_t bin_w)
 403 {
 404         struct fd_ringbuffer *ring = ctx->ring;
 405
 406         emit_mrt(ring, 1, &psurf, &base, bin_w);
 407
 408         fd_wfi(ctx, ring);
 409         fd3_emit_gmem_restore_tex(ring, psurf);
 410
 411         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 412                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 413 }
 414
 415 static void
 416 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 417 {
 418         struct fd3_context *fd3_ctx = fd3_context(ctx);
 419         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 420         struct fd_ringbuffer *ring = ctx->ring;
 421         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 422         float x0, y0, x1, y1;
 423         unsigned bin_w = tile->bin_w;
 424         unsigned bin_h = tile->bin_h;
 425         unsigned i;
 426
 427         /* write texture coordinates to vertexbuf: */
 428         x0 = ((float)tile->xoff) / ((float)pfb->width);
 429         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 430         y0 = ((float)tile->yoff) / ((float)pfb->height);
 431         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 432
 433         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 434         OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 435         OUT_RING(ring, fui(x0));
 436         OUT_RING(ring, fui(y0));
 437         OUT_RING(ring, fui(x1));
 438         OUT_RING(ring, fui(y1));
 439
 440         for (i = 0; i < 4; i++) {
 441                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 442                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 443                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
 444                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 445
 446                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 447                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 448                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 449                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 450                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 451                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 452                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
 453                                 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
 454         }
 455
 456         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 457         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
 458                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 459
 460         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 461         OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 462
 463         OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 464         OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);   /* GRAS_CL_CLIP_CNTL */
 465
 466         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
 467         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
 468         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
 469         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
 470         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
 471         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 472         OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
 473
 474         OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 475         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 476                         A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 477         OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 478                         A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 479
 480         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 481         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 482                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 483         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 484                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 485
 486         OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 487         OUT_RING(ring, 0x2 |
 488                         A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 489                         A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 490                         A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 491                         A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 492                         A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 493                         A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 494                         A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 495                         A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 496
 497         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 498         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 499                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 500                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 501
 502         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 503         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
 504                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 505                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 506                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 507
 508         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 509         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 510         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 511         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 512         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 513
 514         fd_wfi(ctx, ring);
 515         fd3_program_emit(ring, &ctx->blit_prog, false);
 516
 517         fd3_emit_vertex_bufs(ring, &ctx->blit_prog, (struct fd3_vertex_buf[]) {
 518                         { .prsc = fd3_ctx->blit_texcoord_vbuf, .stride = 8, .format = PIPE_FORMAT_R32G32_FLOAT },
 519                         { .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
 520                 }, 2);
 521
 522         /* for gmem pitch/base calculations, we need to use the non-
 523          * truncated tile sizes:
 524          */
 525         bin_w = gmem->bin_w;
 526         bin_h = gmem->bin_h;
 527
 528         if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 529                 emit_mem2gmem_surf(ctx, depth_base(gmem), pfb->zsbuf, bin_w);
 530
 531         if (ctx->restore & FD_BUFFER_COLOR)
 532                 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
 533
 534         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 535         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 536                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 537                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 538 }
 539
 540 static void
 541 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 542 {
 543         unsigned i;
 544         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 545                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 546                 *patch->cs = patch->val | DRAW(0, 0, 0, vismode);
 547         }
 548         util_dynarray_resize(&ctx->draw_patches, 0);
 549 }
 550
 551 static void
 552 patch_rbrc(struct fd_context *ctx, uint32_t val)
 553 {
 554         struct fd3_context *fd3_ctx = fd3_context(ctx);
 555         unsigned i;
 556         for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
 557                 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
 558                 *patch->cs = patch->val | val;
 559         }
 560         util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
 561 }
 562
 563 /* for rendering directly to system memory: */
 564 static void
 565 fd3_emit_sysmem_prep(struct fd_context *ctx)
 566 {
 567         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 568         struct fd_ringbuffer *ring = ctx->ring;
 569         uint32_t pitch = 0;
 570
 571         if (pfb->cbufs[0])
 572                 pitch = fd_resource(pfb->cbufs[0]->texture)->slices[0].pitch;
 573
 574         fd3_emit_restore(ctx);
 575
 576         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 577         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 578                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 579
 580         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
 581
 582         /* setup scissor/offset for current tile: */
 583         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 584         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
 585                         A3XX_RB_WINDOW_OFFSET_Y(0));
 586
 587         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 588         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 589                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 590         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 591                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 592
 593         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 594         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 595                         A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
 596                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 597
 598         patch_draws(ctx, IGNORE_VISIBILITY);
 599         patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
 600 }
 601
 602 static void
 603 update_vsc_pipe(struct fd_context *ctx)
 604 {
 605         struct fd3_context *fd3_ctx = fd3_context(ctx);
 606         struct fd_ringbuffer *ring = ctx->ring;
 607         int i;
 608
 609         OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
 610         OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 611
 612         for (i = 0; i < 8; i++) {
 613                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 614
 615                 if (!pipe->bo) {
 616                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 617                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 618                 }
 619
 620                 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
 621                 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
 622                                 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
 623                                 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
 624                                 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
 625                 OUT_RELOC(ring, pipe->bo, 0, 0, 0);        /* VSC_PIPE[i].DATA_ADDRESS */
 626                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
 627         }
 628 }
 629
 630 static void
 631 emit_binning_pass(struct fd_context *ctx)
 632 {
 633         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 634         struct fd_ringbuffer *ring = ctx->ring;
 635         int i;
 636
 637         if (ctx->screen->gpu_id == 320) {
 638                 emit_binning_workaround(ctx);
 639
 640                 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 641                 OUT_RING(ring, 0x00007fff);
 642         }
 643
 644         OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
 645         OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
 646
 647         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 648         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 649                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 650                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 651
 652         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 653         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 654                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 655
 656         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 657         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 658                         A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 659                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
 660
 661         /* setup scissor/offset for whole screen: */
 662         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 663         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
 664                         A3XX_RB_WINDOW_OFFSET_Y(0));
 665
 666         OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
 667         OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
 668
 669         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 670         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 671                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 672         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 673                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 674
 675         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 676         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 677                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 678
 679         for (i = 0; i < 4; i++) {
 680                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 681                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
 682                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
 683                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
 684         }
 685
 686         OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 687         OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
 688                         A3XX_PC_VSTREAM_CONTROL_N(0));
 689
 690         /* emit IB to binning drawcmds: */
 691         OUT_IB(ring, ctx->binning_start, ctx->binning_end);
 692         fd_reset_wfi(ctx);
 693
 694         fd_wfi(ctx, ring);
 695
 696         /* and then put stuff back the way it was: */
 697
 698         OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
 699         OUT_RING(ring, 0x00000000);
 700
 701         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 702         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
 703                         A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
 704                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 705                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 706
 707         OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
 708         OUT_RING(ring, 0x00000000);
 709
 710         OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 711         OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 712                         A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 713                         A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 714
 715         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
 716         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 717                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 718         OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 719                         A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
 720                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
 721
 722         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 723         OUT_RING(ring, CACHE_FLUSH);
 724
 725         if (ctx->screen->gpu_id == 320) {
 726                 /* dummy-draw workaround: */
 727                 OUT_PKT3(ring, CP_DRAW_INDX, 3);
 728                 OUT_RING(ring, 0x00000000);
 729                 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
 730                                 INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 731                 OUT_RING(ring, 0);             /* NumIndices */
 732                 fd_reset_wfi(ctx);
 733         }
 734
 735         OUT_PKT3(ring, CP_NOP, 4);
 736         OUT_RING(ring, 0x00000000);
 737         OUT_RING(ring, 0x00000000);
 738         OUT_RING(ring, 0x00000000);
 739         OUT_RING(ring, 0x00000000);
 740
 741         fd_wfi(ctx, ring);
 742
 743         if (ctx->screen->gpu_id == 320) {
 744                 emit_binning_workaround(ctx);
 745         }
 746 }
 747
 748 /* before first tile */
 749 static void
 750 fd3_emit_tile_init(struct fd_context *ctx)
 751 {
 752         struct fd_ringbuffer *ring = ctx->ring;
 753         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 754
 755         fd3_emit_restore(ctx);
 756
 757         /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
 758          * at the right and bottom edge tiles
 759          */
 760         OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
 761         OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 762                         A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 763
 764         update_vsc_pipe(ctx);
 765
 766         if (use_hw_binning(ctx)) {
 767                 /* mark the end of the binning cmds: */
 768                 fd_ringmarker_mark(ctx->binning_end);
 769
 770                 /* emit hw binning pass: */
 771                 emit_binning_pass(ctx);
 772
 773                 patch_draws(ctx, USE_VISIBILITY);
 774         } else {
 775                 patch_draws(ctx, IGNORE_VISIBILITY);
 776         }
 777
 778         patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 779                         A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
 780 }
 781
 782 /* before mem2gmem */
 783 static void
 784 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 785 {
 786         struct fd_ringbuffer *ring = ctx->ring;
 787         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 788         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 789         uint32_t reg;
 790
 791         OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
 792         reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(gmem));
 793         if (pfb->zsbuf) {
 794                 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 795         }
 796         OUT_RING(ring, reg);
 797         if (pfb->zsbuf) {
 798                 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
 799                 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 800         } else {
 801                 OUT_RING(ring, 0x00000000);
 802         }
 803
 804         OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
 805         OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 806                         A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 807
 808         OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 809         OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 810                         A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
 811 }
 812
 813 /* before IB to rendering cmds: */
 814 static void
 815 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 816 {
 817         struct fd3_context *fd3_ctx = fd3_context(ctx);
 818         struct fd_ringbuffer *ring = ctx->ring;
 819         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 820         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 821
 822         uint32_t x1 = tile->xoff;
 823         uint32_t y1 = tile->yoff;
 824         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 825         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 826
 827         if (use_hw_binning(ctx)) {
 828                 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
 829
 830                 assert(pipe->w * pipe->h);
 831
 832                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 833                 OUT_RING(ring, HLSQ_FLUSH);
 834
 835                 OUT_WFI(ring);
 836
 837                 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 838                 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
 839                                 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
 840
 841                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 842                 OUT_RING(ring, CACHE_FLUSH);
 843
 844                 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
 845                 OUT_RELOC(ring, pipe->bo, 0, 0, 0);    /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
 846                 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
 847                                 (tile->p * 4), 0, 0);
 848         } else {
 849                 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
 850                 OUT_RING(ring, 0x00000000);
 851         }
 852
 853         OUT_PKT3(ring, CP_SET_BIN, 3);
 854         OUT_RING(ring, 0x00000000);
 855         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 856         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 857
 858         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
 859
 860         /* setup scissor/offset for current tile: */
 861         OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
 862         OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
 863                         A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
 864
 865         OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 866         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 867                         A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 868         OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 869                         A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 870 }
 871
 872 void
 873 fd3_gmem_init(struct pipe_context *pctx)
 874 {
 875         struct fd_context *ctx = fd_context(pctx);
 876
 877         ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
 878         ctx->emit_tile_init = fd3_emit_tile_init;
 879         ctx->emit_tile_prep = fd3_emit_tile_prep;
 880         ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
 881         ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
 882         ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
 883 }