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freedreno/a3xx: remove duplicate mark of end of binning cmds
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static void
47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
48 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
49 bool decode_srgb)
50 {
51 enum a3xx_tile_mode tile_mode;
52 unsigned i;
53
54 if (bin_w) {
55 tile_mode = TILE_32X32;
56 } else {
57 tile_mode = LINEAR;
58 }
59
60 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
61 enum pipe_format pformat = 0;
62 enum a3xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73
74 rsc = fd_resource(psurf->texture);
75 pformat = psurf->format;
76 /* In case we're drawing to Z32F_S8, the "color" actually goes to
77 * the stencil
78 */
79 if (rsc->stencil) {
80 rsc = rsc->stencil;
81 pformat = rsc->base.b.format;
82 bases++;
83 }
84 slice = fd_resource_slice(rsc, psurf->u.tex.level);
85 format = fd3_pipe2color(pformat);
86 swap = fd3_pipe2swap(pformat);
87 if (decode_srgb)
88 srgb = util_format_is_srgb(pformat);
89 else
90 pformat = util_format_linear(pformat);
91
92 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
93
94 offset = fd_resource_offset(rsc, psurf->u.tex.level,
95 psurf->u.tex.first_layer);
96
97 if (bin_w) {
98 stride = bin_w * rsc->cpp;
99
100 if (bases) {
101 base = bases[i];
102 }
103 } else {
104 stride = slice->pitch * rsc->cpp;
105 }
106 } else if (i < nr_bufs && bases) {
107 base = bases[i];
108 }
109
110 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
111 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
112 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
115 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
116 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
117 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
118 } else {
119 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
120 }
121
122 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
123 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
124 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
125 fd3_fs_output_format(pformat))));
126 }
127 }
128
129 static bool
130 use_hw_binning(struct fd_context *ctx)
131 {
132 struct fd_gmem_stateobj *gmem = &ctx->gmem;
133
134 /* workaround: combining scissor optimization and hw binning
135 * seems problematic. Seems like we end up with a mismatch
136 * between binning pass and rendering pass, wrt. where the hw
137 * thinks the vertices belong. And the blob driver doesn't
138 * seem to implement anything like scissor optimization, so
139 * not entirely sure what I might be missing.
140 *
141 * But scissor optimization is mainly for window managers,
142 * which don't have many vertices (and therefore doesn't
143 * benefit much from binning pass).
144 *
145 * So for now just disable binning if scissor optimization is
146 * used.
147 */
148 if (gmem->minx || gmem->miny)
149 return false;
150
151 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
152 }
153
154 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
155 static void update_vsc_pipe(struct fd_context *ctx);
156 static void
157 emit_binning_workaround(struct fd_context *ctx)
158 {
159 struct fd3_context *fd3_ctx = fd3_context(ctx);
160 struct fd_gmem_stateobj *gmem = &ctx->gmem;
161 struct fd_ringbuffer *ring = ctx->ring;
162 struct fd3_emit emit = {
163 .vtx = &fd3_ctx->solid_vbuf_state,
164 .prog = &ctx->solid_prog,
165 .key = {
166 .half_precision = true,
167 },
168 };
169
170 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
171 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
172 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
173 A3XX_RB_MODE_CONTROL_MRT(0));
174 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
175 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
176 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
177
178 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
179 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
180 A3XX_RB_COPY_CONTROL_MODE(0) |
181 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
182 OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
183 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
184 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
185 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
186 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
187 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
188 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
189
190 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
191 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
192 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
193 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
194
195 fd3_program_emit(ring, &emit, 0, NULL);
196 fd3_emit_vertex_bufs(ring, &emit);
197
198 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
199 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
200 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
201 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
202 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
203 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
204 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
205 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
206 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
207
208 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
209 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
210 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
211
212 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
213 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
214 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
215 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
216
217 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
218 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
219
220 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
221 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
222 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
223 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
224 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
225 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
226 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
227 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
228 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
229
230 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
231 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
232
233 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
234 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
235 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
236 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
237 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
238
239 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
240 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
241 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
242 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
243 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
244
245 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
246 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
247 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
248 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
249 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
250
251 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
252 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
253 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
254 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
255 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
256
257 fd_wfi(ctx, ring);
258 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
259 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
260 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
261 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
262 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
263 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
264 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
265
266 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
267 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
268 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
269 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
270 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
271 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
272
273 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
274 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
275 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
276
277 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
278 OUT_RING(ring, 0x00000000); /* viz query info. */
279 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
280 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
281 OUT_RING(ring, 2); /* NumIndices */
282 OUT_RING(ring, 2);
283 OUT_RING(ring, 1);
284 fd_reset_wfi(ctx);
285
286 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
287 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
288
289 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
290 OUT_RING(ring, 0x00000000);
291
292 fd_wfi(ctx, ring);
293 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
294 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
295 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
296
297 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
298 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
299 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
300 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
301
302 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
303 OUT_RING(ring, 0x00000000);
304 }
305
306 /* transfer from gmem to system memory (ie. normal RAM) */
307
308 static void
309 emit_gmem2mem_surf(struct fd_context *ctx,
310 enum adreno_rb_copy_control_mode mode,
311 bool stencil,
312 uint32_t base, struct pipe_surface *psurf)
313 {
314 struct fd_ringbuffer *ring = ctx->ring;
315 struct fd_resource *rsc = fd_resource(psurf->texture);
316 enum pipe_format format = psurf->format;
317 if (stencil) {
318 rsc = rsc->stencil;
319 format = rsc->base.b.format;
320 }
321 struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
322 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
323 psurf->u.tex.first_layer);
324
325 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
326
327 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
328 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
329 A3XX_RB_COPY_CONTROL_MODE(mode) |
330 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
331 COND(format == PIPE_FORMAT_Z32_FLOAT ||
332 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
333 A3XX_RB_COPY_CONTROL_UNK12));
334
335 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
336 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
337 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
338 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
339 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
340 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
341 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
342
343 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
344 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
345 }
346
347 static void
348 fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
349 {
350 struct fd3_context *fd3_ctx = fd3_context(ctx);
351 struct fd_ringbuffer *ring = ctx->ring;
352 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
353 struct fd3_emit emit = {
354 .vtx = &fd3_ctx->solid_vbuf_state,
355 .prog = &ctx->solid_prog,
356 .key = {
357 .half_precision = true,
358 },
359 };
360 int i;
361
362 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
363 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
364
365 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
366 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
367 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
368 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
369 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
370 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
371 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
372 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
373 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
374
375 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
376 OUT_RING(ring, 0xff000000 |
377 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
378 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
379 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
380 OUT_RING(ring, 0xff000000 |
381 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
382 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
383 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
384
385 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
386 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
387
388 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
389 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
390
391 fd_wfi(ctx, ring);
392 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
393 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
394 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
395 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
396 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
397 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
398 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
399
400 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
401 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
402 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
403 A3XX_RB_MODE_CONTROL_MRT(0));
404
405 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
406 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
407 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
408 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
409 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
410
411 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
412 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
413 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
414 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
415
416 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
417 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
418 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
419 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
420 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
421
422 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
423 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
424 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
425 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
426 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
427
428 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
429 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
430 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
431 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
432 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
433
434 fd3_program_emit(ring, &emit, 0, NULL);
435 fd3_emit_vertex_bufs(ring, &emit);
436
437 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
438 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
439 if (!rsc->stencil || ctx->resolve & FD_BUFFER_DEPTH)
440 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, false,
441 ctx->gmem.zsbuf_base[0], pfb->zsbuf);
442 if (rsc->stencil && ctx->resolve & FD_BUFFER_STENCIL)
443 emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, true,
444 ctx->gmem.zsbuf_base[1], pfb->zsbuf);
445 }
446
447 if (ctx->resolve & FD_BUFFER_COLOR) {
448 for (i = 0; i < pfb->nr_cbufs; i++) {
449 if (!pfb->cbufs[i])
450 continue;
451 if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
452 continue;
453 emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, false,
454 ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
455 }
456 }
457
458 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
459 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
460 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
461 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
462
463 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
464 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
465 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
466 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
467 }
468
469 /* transfer from system memory to gmem */
470
471 static void
472 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t bases[],
473 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
474 {
475 struct fd_ringbuffer *ring = ctx->ring;
476 struct pipe_surface *zsbufs[2];
477
478 assert(bufs > 0);
479
480 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
481 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
482 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
483 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
484
485 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
486
487 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
488 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
489 /* Depth is stored as unorm in gmem, so we have to write it in using a
490 * special blit shader which writes depth.
491 */
492 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
493 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
494 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
495 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
496 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
497 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
498
499 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
500 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
501 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
502 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * ctx->gmem.bin_w));
503
504 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
505 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
506 OUT_RING(ring, 0);
507 } else {
508 /* The gmem_restore_tex logic will put the first buffer's stencil
509 * as color. Supply it with the proper information to make that
510 * happen.
511 */
512 zsbufs[0] = zsbufs[1] = psurf[0];
513 psurf = zsbufs;
514 bufs = 2;
515 }
516 } else {
517 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
518 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
519 }
520
521 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
522
523 fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
524 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
525 }
526
527 static void
528 fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
529 {
530 struct fd3_context *fd3_ctx = fd3_context(ctx);
531 struct fd_gmem_stateobj *gmem = &ctx->gmem;
532 struct fd_ringbuffer *ring = ctx->ring;
533 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
534 struct fd3_emit emit = {
535 .vtx = &fd3_ctx->blit_vbuf_state,
536 .sprite_coord_enable = 1,
537 /* NOTE: They all use the same VP, this is for vtx bufs. */
538 .prog = &ctx->blit_prog[0],
539 .key = {
540 .half_precision = fd_half_precision(pfb),
541 },
542 };
543 float x0, y0, x1, y1;
544 unsigned bin_w = tile->bin_w;
545 unsigned bin_h = tile->bin_h;
546 unsigned i;
547
548 /* write texture coordinates to vertexbuf: */
549 x0 = ((float)tile->xoff) / ((float)pfb->width);
550 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
551 y0 = ((float)tile->yoff) / ((float)pfb->height);
552 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
553
554 OUT_PKT3(ring, CP_MEM_WRITE, 5);
555 OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
556 OUT_RING(ring, fui(x0));
557 OUT_RING(ring, fui(y0));
558 OUT_RING(ring, fui(x1));
559 OUT_RING(ring, fui(y1));
560
561 fd3_emit_cache_flush(ctx, ring);
562
563 for (i = 0; i < 4; i++) {
564 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
565 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
566 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
567 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
568
569 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
570 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
571 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
572 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
573 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
574 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
575 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
576 }
577
578 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
579 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
580 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
581
582 fd_wfi(ctx, ring);
583 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
584 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
585
586 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
587 OUT_RING(ring, 0);
588 OUT_RING(ring, 0);
589
590 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
591 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
592
593 fd_wfi(ctx, ring);
594 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
595 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
596 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
597 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
598 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
599 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
600 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
601
602 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
603 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
604 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
605 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
606 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
607
608 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
609 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
610 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
611 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
612 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
613
614 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
615 OUT_RING(ring, 0x2 |
616 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
617 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
618 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
619 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
620 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
621 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
622 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
623 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
624
625 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
626 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
627 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
628
629 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
630 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
631 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
632 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
633
634 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
635 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
636 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
637 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
638 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
639
640 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
641 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
642 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
643 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
644 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
645
646 fd3_emit_vertex_bufs(ring, &emit);
647
648 /* for gmem pitch/base calculations, we need to use the non-
649 * truncated tile sizes:
650 */
651 bin_w = gmem->bin_w;
652 bin_h = gmem->bin_h;
653
654 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
655 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
656 emit.fp = NULL; /* frag shader changed so clear cache */
657 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
658 emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
659 }
660
661 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
662 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
663 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
664 /* Non-float can use a regular color write. It's split over 8-bit
665 * components, so half precision is always sufficient.
666 */
667 emit.prog = &ctx->blit_prog[0];
668 emit.key.half_precision = true;
669 } else {
670 /* Float depth needs special blit shader that writes depth */
671 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
672 emit.prog = &ctx->blit_z;
673 else
674 emit.prog = &ctx->blit_zs;
675 emit.key.half_precision = false;
676 }
677 emit.fp = NULL; /* frag shader changed so clear cache */
678 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
679 emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
680 }
681
682 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
683 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
684 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
685 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
686
687 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
688 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
689 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
690 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
691 }
692
693 static void
694 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
695 {
696 unsigned i;
697 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
698 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
699 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
700 }
701 util_dynarray_resize(&ctx->draw_patches, 0);
702 }
703
704 static void
705 patch_rbrc(struct fd_context *ctx, uint32_t val)
706 {
707 struct fd3_context *fd3_ctx = fd3_context(ctx);
708 unsigned i;
709 for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
710 struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
711 *patch->cs = patch->val | val;
712 }
713 util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
714 }
715
716 /* for rendering directly to system memory: */
717 static void
718 fd3_emit_sysmem_prep(struct fd_context *ctx)
719 {
720 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
721 struct fd_ringbuffer *ring = ctx->ring;
722 uint32_t i, pitch = 0;
723
724 for (i = 0; i < pfb->nr_cbufs; i++) {
725 struct pipe_surface *psurf = pfb->cbufs[i];
726 if (!psurf)
727 continue;
728 pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
729 }
730
731 fd3_emit_restore(ctx);
732
733 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
734 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
735 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
736
737 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
738
739 /* setup scissor/offset for current tile: */
740 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
741 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
742 A3XX_RB_WINDOW_OFFSET_Y(0));
743
744 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
745 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
746 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
747 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
748 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
749
750 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
751 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
752 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
753 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
754 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
755
756 patch_draws(ctx, IGNORE_VISIBILITY);
757 patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
758 }
759
760 static void
761 update_vsc_pipe(struct fd_context *ctx)
762 {
763 struct fd3_context *fd3_ctx = fd3_context(ctx);
764 struct fd_ringbuffer *ring = ctx->ring;
765 int i;
766
767 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
768 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
769
770 for (i = 0; i < 8; i++) {
771 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
772
773 if (!pipe->bo) {
774 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
775 DRM_FREEDRENO_GEM_TYPE_KMEM);
776 }
777
778 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
779 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
780 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
781 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
782 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
783 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
784 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
785 }
786 }
787
788 static void
789 emit_binning_pass(struct fd_context *ctx)
790 {
791 struct fd_gmem_stateobj *gmem = &ctx->gmem;
792 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
793 struct fd_ringbuffer *ring = ctx->ring;
794 int i;
795
796 uint32_t x1 = gmem->minx;
797 uint32_t y1 = gmem->miny;
798 uint32_t x2 = gmem->minx + gmem->width - 1;
799 uint32_t y2 = gmem->miny + gmem->height - 1;
800
801 if (ctx->screen->gpu_id == 320) {
802 emit_binning_workaround(ctx);
803 fd_wfi(ctx, ring);
804 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
805 OUT_RING(ring, 0x00007fff);
806 }
807
808 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
809 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
810
811 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
812 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
813 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
814 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
815
816 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
817 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
818 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
819
820 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
821 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
822 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
823 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
824
825 /* setup scissor/offset for whole screen: */
826 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
827 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
828 A3XX_RB_WINDOW_OFFSET_Y(y1));
829
830 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
831 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
832
833 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
834 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
835 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
836 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
837 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
838
839 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
840 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
841 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
842 A3XX_RB_MODE_CONTROL_MRT(0));
843
844 for (i = 0; i < 4; i++) {
845 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
846 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
847 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
848 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
849 }
850
851 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
852 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
853 A3XX_PC_VSTREAM_CONTROL_N(0));
854
855 /* emit IB to binning drawcmds: */
856 ctx->emit_ib(ring, ctx->binning_start, ctx->binning_end);
857 fd_reset_wfi(ctx);
858
859 fd_wfi(ctx, ring);
860
861 /* and then put stuff back the way it was: */
862
863 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
864 OUT_RING(ring, 0x00000000);
865
866 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
867 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
868 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
869 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
870 A3XX_SP_SP_CTRL_REG_L0MODE(0));
871
872 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
873 OUT_RING(ring, 0x00000000);
874
875 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
876 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
877 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
878 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
879
880 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
881 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
882 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
883 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
884 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
885 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
886 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
887
888 fd_event_write(ctx, ring, CACHE_FLUSH);
889 fd_wfi(ctx, ring);
890
891 if (ctx->screen->gpu_id == 320) {
892 /* dummy-draw workaround: */
893 OUT_PKT3(ring, CP_DRAW_INDX, 3);
894 OUT_RING(ring, 0x00000000);
895 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
896 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
897 OUT_RING(ring, 0); /* NumIndices */
898 fd_reset_wfi(ctx);
899 }
900
901 OUT_PKT3(ring, CP_NOP, 4);
902 OUT_RING(ring, 0x00000000);
903 OUT_RING(ring, 0x00000000);
904 OUT_RING(ring, 0x00000000);
905 OUT_RING(ring, 0x00000000);
906
907 fd_wfi(ctx, ring);
908
909 if (ctx->screen->gpu_id == 320) {
910 emit_binning_workaround(ctx);
911 }
912 }
913
914 /* before first tile */
915 static void
916 fd3_emit_tile_init(struct fd_context *ctx)
917 {
918 struct fd_ringbuffer *ring = ctx->ring;
919 struct fd_gmem_stateobj *gmem = &ctx->gmem;
920 uint32_t rb_render_control;
921
922 fd3_emit_restore(ctx);
923
924 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
925 * at the right and bottom edge tiles
926 */
927 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
928 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
929 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
930
931 update_vsc_pipe(ctx);
932
933 if (use_hw_binning(ctx)) {
934 /* emit hw binning pass: */
935 emit_binning_pass(ctx);
936
937 patch_draws(ctx, USE_VISIBILITY);
938 } else {
939 patch_draws(ctx, IGNORE_VISIBILITY);
940 }
941
942 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
943 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
944
945 patch_rbrc(ctx, rb_render_control);
946 }
947
948 /* before mem2gmem */
949 static void
950 fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
951 {
952 struct fd_ringbuffer *ring = ctx->ring;
953 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
954
955 if (ctx->needs_rb_fbd) {
956 fd_wfi(ctx, ring);
957 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
958 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
959 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
960 ctx->needs_rb_fbd = false;
961 }
962
963 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
964 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
965 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
966 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
967 }
968
969 /* before IB to rendering cmds: */
970 static void
971 fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
972 {
973 struct fd3_context *fd3_ctx = fd3_context(ctx);
974 struct fd_ringbuffer *ring = ctx->ring;
975 struct fd_gmem_stateobj *gmem = &ctx->gmem;
976 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
977
978 uint32_t x1 = tile->xoff;
979 uint32_t y1 = tile->yoff;
980 uint32_t x2 = tile->xoff + tile->bin_w - 1;
981 uint32_t y2 = tile->yoff + tile->bin_h - 1;
982
983 uint32_t reg;
984
985 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
986 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
987 if (pfb->zsbuf) {
988 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
989 }
990 OUT_RING(ring, reg);
991 if (pfb->zsbuf) {
992 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
993 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
994 if (rsc->stencil) {
995 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
996 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
997 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
998 }
999 } else {
1000 OUT_RING(ring, 0x00000000);
1001 }
1002
1003 if (use_hw_binning(ctx)) {
1004 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
1005
1006 assert(pipe->w * pipe->h);
1007
1008 fd_event_write(ctx, ring, HLSQ_FLUSH);
1009 fd_wfi(ctx, ring);
1010
1011 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1012 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1013 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1014
1015
1016 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1017 OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1018 OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1019 (tile->p * 4), 0, 0);
1020 } else {
1021 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1022 OUT_RING(ring, 0x00000000);
1023 }
1024
1025 OUT_PKT3(ring, CP_SET_BIN, 3);
1026 OUT_RING(ring, 0x00000000);
1027 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1028 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1029
1030 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1031
1032 /* setup scissor/offset for current tile: */
1033 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1034 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1035 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1036
1037 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1038 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1039 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1040 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1041 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1042 }
1043
1044 void
1045 fd3_gmem_init(struct pipe_context *pctx)
1046 {
1047 struct fd_context *ctx = fd_context(pctx);
1048
1049 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1050 ctx->emit_tile_init = fd3_emit_tile_init;
1051 ctx->emit_tile_prep = fd3_emit_tile_prep;
1052 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1053 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1054 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1055 }