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freedreno: move more batch related tracking to fd_batch
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd3_gmem.h"
40 #include "fd3_context.h"
41 #include "fd3_emit.h"
42 #include "fd3_program.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static void
47 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
48 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
49 bool decode_srgb)
50 {
51 enum a3xx_tile_mode tile_mode;
52 unsigned i;
53
54 if (bin_w) {
55 tile_mode = TILE_32X32;
56 } else {
57 tile_mode = LINEAR;
58 }
59
60 for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
61 enum pipe_format pformat = 0;
62 enum a3xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73
74 rsc = fd_resource(psurf->texture);
75 pformat = psurf->format;
76 /* In case we're drawing to Z32F_S8, the "color" actually goes to
77 * the stencil
78 */
79 if (rsc->stencil) {
80 rsc = rsc->stencil;
81 pformat = rsc->base.b.format;
82 if (bases)
83 bases++;
84 }
85 slice = fd_resource_slice(rsc, psurf->u.tex.level);
86 format = fd3_pipe2color(pformat);
87 swap = fd3_pipe2swap(pformat);
88 if (decode_srgb)
89 srgb = util_format_is_srgb(pformat);
90 else
91 pformat = util_format_linear(pformat);
92
93 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
94
95 offset = fd_resource_offset(rsc, psurf->u.tex.level,
96 psurf->u.tex.first_layer);
97
98 if (bin_w) {
99 stride = bin_w * rsc->cpp;
100
101 if (bases) {
102 base = bases[i];
103 }
104 } else {
105 stride = slice->pitch * rsc->cpp;
106 }
107 } else if (i < nr_bufs && bases) {
108 base = bases[i];
109 }
110
111 OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
112 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
113 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
114 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
115 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
116 COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
117 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
118 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
119 } else {
120 OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
121 }
122
123 OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
124 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
125 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
126 fd3_fs_output_format(pformat))));
127 }
128 }
129
130 static bool
131 use_hw_binning(struct fd_batch *batch)
132 {
133 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
134
135 /* workaround: combining scissor optimization and hw binning
136 * seems problematic. Seems like we end up with a mismatch
137 * between binning pass and rendering pass, wrt. where the hw
138 * thinks the vertices belong. And the blob driver doesn't
139 * seem to implement anything like scissor optimization, so
140 * not entirely sure what I might be missing.
141 *
142 * But scissor optimization is mainly for window managers,
143 * which don't have many vertices (and therefore doesn't
144 * benefit much from binning pass).
145 *
146 * So for now just disable binning if scissor optimization is
147 * used.
148 */
149 if (gmem->minx || gmem->miny)
150 return false;
151
152 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
153 }
154
155 /* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
156 static void update_vsc_pipe(struct fd_batch *batch);
157 static void
158 emit_binning_workaround(struct fd_batch *batch)
159 {
160 struct fd_context *ctx = batch->ctx;
161 struct fd3_context *fd3_ctx = fd3_context(ctx);
162 struct fd_gmem_stateobj *gmem = &ctx->gmem;
163 struct fd_ringbuffer *ring = batch->gmem;
164 struct fd3_emit emit = {
165 .debug = &ctx->debug,
166 .vtx = &fd3_ctx->solid_vbuf_state,
167 .prog = &ctx->solid_prog,
168 .key = {
169 .half_precision = true,
170 },
171 };
172
173 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
174 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
175 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
176 A3XX_RB_MODE_CONTROL_MRT(0));
177 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
178 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
179 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
180
181 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
182 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
183 A3XX_RB_COPY_CONTROL_MODE(0) |
184 A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
185 OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
186 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
187 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
188 A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
189 A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
190 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
191 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
192
193 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
194 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
195 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
196 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
197
198 fd3_program_emit(ring, &emit, 0, NULL);
199 fd3_emit_vertex_bufs(ring, &emit);
200
201 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
202 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
203 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
204 A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
205 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
206 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
207 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
208 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
209 OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
210
211 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
212 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
213 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
214
215 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
216 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
217 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
218 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
219
220 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
221 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
222
223 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
224 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
225 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
226 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
227 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
228 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
229 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
230 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
231 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
232
233 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
234 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
235
236 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
237 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
238 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
239 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
240 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
241
242 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
243 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
244 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
245 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
246 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
247
248 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
249 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
250 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
251 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
252 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
253
254 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
255 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
256 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
257 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
258 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
259
260 fd_wfi(ctx, ring);
261 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
262 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
263 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
264 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
265 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
266 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
267 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
268
269 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
270 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
271 A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
272 A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
273 A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
274 A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
275
276 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
277 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
278 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
279
280 OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
281 OUT_RING(ring, 0x00000000); /* viz query info. */
282 OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
283 INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
284 OUT_RING(ring, 2); /* NumIndices */
285 OUT_RING(ring, 2);
286 OUT_RING(ring, 1);
287 fd_reset_wfi(ctx);
288
289 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
290 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
291
292 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
293 OUT_RING(ring, 0x00000000);
294
295 fd_wfi(ctx, ring);
296 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
297 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
298 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
299
300 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
301 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
302 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
303 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
304
305 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
306 OUT_RING(ring, 0x00000000);
307 }
308
309 /* transfer from gmem to system memory (ie. normal RAM) */
310
311 static void
312 emit_gmem2mem_surf(struct fd_batch *batch,
313 enum adreno_rb_copy_control_mode mode,
314 bool stencil,
315 uint32_t base, struct pipe_surface *psurf)
316 {
317 struct fd_ringbuffer *ring = batch->gmem;
318 struct fd_resource *rsc = fd_resource(psurf->texture);
319 enum pipe_format format = psurf->format;
320 if (stencil) {
321 rsc = rsc->stencil;
322 format = rsc->base.b.format;
323 }
324 struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
325 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
326 psurf->u.tex.first_layer);
327
328 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
329
330 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
331 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
332 A3XX_RB_COPY_CONTROL_MODE(mode) |
333 A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
334 COND(format == PIPE_FORMAT_Z32_FLOAT ||
335 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
336 A3XX_RB_COPY_CONTROL_UNK12));
337
338 OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
339 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
340 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
341 A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
342 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
343 A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
344 A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
345
346 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
347 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
348 }
349
350 static void
351 fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
352 {
353 struct fd_context *ctx = batch->ctx;
354 struct fd3_context *fd3_ctx = fd3_context(ctx);
355 struct fd_ringbuffer *ring = batch->gmem;
356 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
357 struct fd3_emit emit = {
358 .debug = &ctx->debug,
359 .vtx = &fd3_ctx->solid_vbuf_state,
360 .prog = &ctx->solid_prog,
361 .key = {
362 .half_precision = true,
363 },
364 };
365 int i;
366
367 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
368 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
369
370 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
371 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
372 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
373 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
374 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
375 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
376 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
377 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
378 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
379
380 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
381 OUT_RING(ring, 0xff000000 |
382 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
383 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
384 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
385 OUT_RING(ring, 0xff000000 |
386 A3XX_RB_STENCILREFMASK_STENCILREF(0) |
387 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
388 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
389
390 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
391 OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
392
393 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
394 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
395
396 fd_wfi(ctx, ring);
397 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
398 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
399 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
400 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
401 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
402 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
403 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
404
405 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
406 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
407 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
408 A3XX_RB_MODE_CONTROL_MRT(0));
409
410 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
411 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
412 A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
413 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
414 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
415
416 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
417 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
418 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
419 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
420
421 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
422 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
423 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
424 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
425 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
426
427 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
428 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
429 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
430 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
431 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
432
433 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
434 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
435 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
436 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
437 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
438
439 fd3_program_emit(ring, &emit, 0, NULL);
440 fd3_emit_vertex_bufs(ring, &emit);
441
442 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
443 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
444 if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
445 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
446 ctx->gmem.zsbuf_base[0], pfb->zsbuf);
447 if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
448 emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
449 ctx->gmem.zsbuf_base[1], pfb->zsbuf);
450 }
451
452 if (batch->resolve & FD_BUFFER_COLOR) {
453 for (i = 0; i < pfb->nr_cbufs; i++) {
454 if (!pfb->cbufs[i])
455 continue;
456 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
457 continue;
458 emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
459 ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
460 }
461 }
462
463 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
464 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
465 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
466 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
467
468 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
469 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
470 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
471 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
472 }
473
474 /* transfer from system memory to gmem */
475
476 static void
477 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
478 struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
479 {
480 struct fd_ringbuffer *ring = batch->gmem;
481 struct pipe_surface *zsbufs[2];
482
483 assert(bufs > 0);
484
485 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
486 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
487 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
488 A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
489
490 emit_mrt(ring, bufs, psurf, bases, bin_w, false);
491
492 if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
493 psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
494 /* Depth is stored as unorm in gmem, so we have to write it in using a
495 * special blit shader which writes depth.
496 */
497 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
498 OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
499 A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
500 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
501 A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
502 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
503
504 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
505 OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
506 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
507 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->ctx->gmem.bin_w));
508
509 if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
510 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
511 OUT_RING(ring, 0);
512 } else {
513 /* The gmem_restore_tex logic will put the first buffer's stencil
514 * as color. Supply it with the proper information to make that
515 * happen.
516 */
517 zsbufs[0] = zsbufs[1] = psurf[0];
518 psurf = zsbufs;
519 bufs = 2;
520 }
521 } else {
522 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
523 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
524 }
525
526 fd3_emit_gmem_restore_tex(ring, psurf, bufs);
527
528 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
529 DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
530 }
531
532 static void
533 fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
534 {
535 struct fd_context *ctx = batch->ctx;
536 struct fd3_context *fd3_ctx = fd3_context(ctx);
537 struct fd_gmem_stateobj *gmem = &ctx->gmem;
538 struct fd_ringbuffer *ring = batch->gmem;
539 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
540 struct fd3_emit emit = {
541 .debug = &ctx->debug,
542 .vtx = &fd3_ctx->blit_vbuf_state,
543 .sprite_coord_enable = 1,
544 /* NOTE: They all use the same VP, this is for vtx bufs. */
545 .prog = &ctx->blit_prog[0],
546 .key = {
547 .half_precision = fd_half_precision(pfb),
548 },
549 };
550 float x0, y0, x1, y1;
551 unsigned bin_w = tile->bin_w;
552 unsigned bin_h = tile->bin_h;
553 unsigned i;
554
555 /* write texture coordinates to vertexbuf: */
556 x0 = ((float)tile->xoff) / ((float)pfb->width);
557 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
558 y0 = ((float)tile->yoff) / ((float)pfb->height);
559 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
560
561 OUT_PKT3(ring, CP_MEM_WRITE, 5);
562 OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
563 OUT_RING(ring, fui(x0));
564 OUT_RING(ring, fui(y0));
565 OUT_RING(ring, fui(x1));
566 OUT_RING(ring, fui(y1));
567
568 fd3_emit_cache_flush(ctx, ring);
569
570 for (i = 0; i < 4; i++) {
571 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
572 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
573 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
574 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
575
576 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
577 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
578 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
579 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
580 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
581 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
582 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
583 }
584
585 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
586 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
587 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
588
589 fd_wfi(ctx, ring);
590 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
591 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
592
593 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
594 OUT_RING(ring, 0);
595 OUT_RING(ring, 0);
596
597 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
598 OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
599
600 fd_wfi(ctx, ring);
601 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
602 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
603 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
604 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
605 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
606 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
607 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
608
609 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
610 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
611 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
612 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
613 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
614
615 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
616 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
617 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
618 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
619 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
620
621 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
622 OUT_RING(ring, 0x2 |
623 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
624 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
625 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
626 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
627 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
628 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
629 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
630 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
631
632 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
633 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
634 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
635
636 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
637 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
638 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
639 A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
640
641 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
642 OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
643 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
644 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
645 A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
646
647 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
648 OUT_RING(ring, 0); /* VFD_INDEX_MIN */
649 OUT_RING(ring, 2); /* VFD_INDEX_MAX */
650 OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
651 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
652
653 fd3_emit_vertex_bufs(ring, &emit);
654
655 /* for gmem pitch/base calculations, we need to use the non-
656 * truncated tile sizes:
657 */
658 bin_w = gmem->bin_w;
659 bin_h = gmem->bin_h;
660
661 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
662 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
663 emit.fp = NULL; /* frag shader changed so clear cache */
664 fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
665 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
666 }
667
668 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
669 if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
670 pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
671 /* Non-float can use a regular color write. It's split over 8-bit
672 * components, so half precision is always sufficient.
673 */
674 emit.prog = &ctx->blit_prog[0];
675 emit.key.half_precision = true;
676 } else {
677 /* Float depth needs special blit shader that writes depth */
678 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
679 emit.prog = &ctx->blit_z;
680 else
681 emit.prog = &ctx->blit_zs;
682 emit.key.half_precision = false;
683 }
684 emit.fp = NULL; /* frag shader changed so clear cache */
685 fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
686 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
687 }
688
689 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
690 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
691 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
692 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
693
694 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
695 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
696 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
697 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
698 }
699
700 static void
701 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
702 {
703 unsigned i;
704 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
705 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
706 *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
707 }
708 util_dynarray_resize(&batch->draw_patches, 0);
709 }
710
711 static void
712 patch_rbrc(struct fd_batch *batch, uint32_t val)
713 {
714 unsigned i;
715 for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
716 struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
717 *patch->cs = patch->val | val;
718 }
719 util_dynarray_resize(&batch->rbrc_patches, 0);
720 }
721
722 /* for rendering directly to system memory: */
723 static void
724 fd3_emit_sysmem_prep(struct fd_batch *batch)
725 {
726 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
727 struct fd_ringbuffer *ring = batch->gmem;
728 uint32_t i, pitch = 0;
729
730 for (i = 0; i < pfb->nr_cbufs; i++) {
731 struct pipe_surface *psurf = pfb->cbufs[i];
732 if (!psurf)
733 continue;
734 pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
735 }
736
737 fd3_emit_restore(batch->ctx, ring);
738
739 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
740 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
741 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
742
743 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
744
745 /* setup scissor/offset for current tile: */
746 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
747 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
748 A3XX_RB_WINDOW_OFFSET_Y(0));
749
750 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
751 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
752 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
753 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
754 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
755
756 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
757 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
758 A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
759 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
760 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
761
762 patch_draws(batch, IGNORE_VISIBILITY);
763 patch_rbrc(batch, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
764 }
765
766 static void
767 update_vsc_pipe(struct fd_batch *batch)
768 {
769 struct fd_context *ctx = batch->ctx;
770 struct fd3_context *fd3_ctx = fd3_context(ctx);
771 struct fd_ringbuffer *ring = batch->gmem;
772 int i;
773
774 OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
775 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
776
777 for (i = 0; i < 8; i++) {
778 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
779
780 if (!pipe->bo) {
781 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
782 DRM_FREEDRENO_GEM_TYPE_KMEM);
783 }
784
785 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
786 OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
787 A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
788 A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
789 A3XX_VSC_PIPE_CONFIG_H(pipe->h));
790 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
791 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
792 }
793 }
794
795 static void
796 emit_binning_pass(struct fd_batch *batch)
797 {
798 struct fd_context *ctx = batch->ctx;
799 struct fd_gmem_stateobj *gmem = &ctx->gmem;
800 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
801 struct fd_ringbuffer *ring = batch->gmem;
802 int i;
803
804 uint32_t x1 = gmem->minx;
805 uint32_t y1 = gmem->miny;
806 uint32_t x2 = gmem->minx + gmem->width - 1;
807 uint32_t y2 = gmem->miny + gmem->height - 1;
808
809 if (ctx->screen->gpu_id == 320) {
810 emit_binning_workaround(batch);
811 fd_wfi(ctx, ring);
812 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
813 OUT_RING(ring, 0x00007fff);
814 }
815
816 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
817 OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
818
819 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
820 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
821 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
822 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
823
824 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
825 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
826 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
827
828 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
829 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
830 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
831 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
832
833 /* setup scissor/offset for whole screen: */
834 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
835 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
836 A3XX_RB_WINDOW_OFFSET_Y(y1));
837
838 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
839 OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
840
841 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
842 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
843 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
844 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
845 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
846
847 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
848 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
849 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
850 A3XX_RB_MODE_CONTROL_MRT(0));
851
852 for (i = 0; i < 4; i++) {
853 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
854 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
855 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
856 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
857 }
858
859 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
860 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
861 A3XX_PC_VSTREAM_CONTROL_N(0));
862
863 /* emit IB to binning drawcmds: */
864 ctx->emit_ib(ring, batch->binning);
865 fd_reset_wfi(ctx);
866
867 fd_wfi(ctx, ring);
868
869 /* and then put stuff back the way it was: */
870
871 OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
872 OUT_RING(ring, 0x00000000);
873
874 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
875 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
876 A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
877 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
878 A3XX_SP_SP_CTRL_REG_L0MODE(0));
879
880 OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
881 OUT_RING(ring, 0x00000000);
882
883 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
884 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
885 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
886 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
887
888 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
889 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
890 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
891 A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
892 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
893 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
894 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
895
896 fd_event_write(ctx, ring, CACHE_FLUSH);
897 fd_wfi(ctx, ring);
898
899 if (ctx->screen->gpu_id == 320) {
900 /* dummy-draw workaround: */
901 OUT_PKT3(ring, CP_DRAW_INDX, 3);
902 OUT_RING(ring, 0x00000000);
903 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
904 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
905 OUT_RING(ring, 0); /* NumIndices */
906 fd_reset_wfi(ctx);
907 }
908
909 OUT_PKT3(ring, CP_NOP, 4);
910 OUT_RING(ring, 0x00000000);
911 OUT_RING(ring, 0x00000000);
912 OUT_RING(ring, 0x00000000);
913 OUT_RING(ring, 0x00000000);
914
915 fd_wfi(ctx, ring);
916
917 if (ctx->screen->gpu_id == 320) {
918 emit_binning_workaround(batch);
919 }
920 }
921
922 /* before first tile */
923 static void
924 fd3_emit_tile_init(struct fd_batch *batch)
925 {
926 struct fd_ringbuffer *ring = batch->gmem;
927 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
928 uint32_t rb_render_control;
929
930 fd3_emit_restore(batch->ctx, ring);
931
932 /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
933 * at the right and bottom edge tiles
934 */
935 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
936 OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
937 A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
938
939 update_vsc_pipe(batch);
940
941 if (use_hw_binning(batch)) {
942 /* emit hw binning pass: */
943 emit_binning_pass(batch);
944
945 patch_draws(batch, USE_VISIBILITY);
946 } else {
947 patch_draws(batch, IGNORE_VISIBILITY);
948 }
949
950 rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
951 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
952
953 patch_rbrc(batch, rb_render_control);
954 }
955
956 /* before mem2gmem */
957 static void
958 fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
959 {
960 struct fd_context *ctx = batch->ctx;
961 struct fd_ringbuffer *ring = batch->gmem;
962 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
963
964 if (ctx->needs_rb_fbd) {
965 fd_wfi(ctx, ring);
966 OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
967 OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
968 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
969 ctx->needs_rb_fbd = false;
970 }
971
972 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
973 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
974 A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
975 A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
976 }
977
978 /* before IB to rendering cmds: */
979 static void
980 fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
981 {
982 struct fd_context *ctx = batch->ctx;
983 struct fd3_context *fd3_ctx = fd3_context(ctx);
984 struct fd_ringbuffer *ring = batch->gmem;
985 struct fd_gmem_stateobj *gmem = &ctx->gmem;
986 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
987
988 uint32_t x1 = tile->xoff;
989 uint32_t y1 = tile->yoff;
990 uint32_t x2 = tile->xoff + tile->bin_w - 1;
991 uint32_t y2 = tile->yoff + tile->bin_h - 1;
992
993 uint32_t reg;
994
995 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
996 reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
997 if (pfb->zsbuf) {
998 reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
999 }
1000 OUT_RING(ring, reg);
1001 if (pfb->zsbuf) {
1002 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1003 OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
1004 if (rsc->stencil) {
1005 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
1006 OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
1007 OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
1008 }
1009 } else {
1010 OUT_RING(ring, 0x00000000);
1011 }
1012
1013 if (use_hw_binning(batch)) {
1014 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
1015
1016 assert(pipe->w * pipe->h);
1017
1018 fd_event_write(ctx, ring, HLSQ_FLUSH);
1019 fd_wfi(ctx, ring);
1020
1021 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1022 OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
1023 A3XX_PC_VSTREAM_CONTROL_N(tile->n));
1024
1025
1026 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
1027 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
1028 OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
1029 (tile->p * 4), 0, 0);
1030 } else {
1031 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
1032 OUT_RING(ring, 0x00000000);
1033 }
1034
1035 OUT_PKT3(ring, CP_SET_BIN, 3);
1036 OUT_RING(ring, 0x00000000);
1037 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
1038 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
1039
1040 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
1041
1042 /* setup scissor/offset for current tile: */
1043 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
1044 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
1045 A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
1046
1047 OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
1048 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
1049 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
1050 OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
1051 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
1052 }
1053
1054 void
1055 fd3_gmem_init(struct pipe_context *pctx)
1056 {
1057 struct fd_context *ctx = fd_context(pctx);
1058
1059 ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
1060 ctx->emit_tile_init = fd3_emit_tile_init;
1061 ctx->emit_tile_prep = fd3_emit_tile_prep;
1062 ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
1063 ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
1064 ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
1065 }