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freedreno/a3xx: support for hw binning pass
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
36
37 #include "fd3_program.h"
38 #include "fd3_compiler.h"
39 #include "fd3_emit.h"
40 #include "fd3_texture.h"
41 #include "fd3_util.h"
42
43 static void
44 delete_shader(struct fd3_shader_stateobj *so)
45 {
46 ir3_shader_destroy(so->ir);
47 fd_bo_del(so->bo);
48 free(so);
49 }
50
51 static void
52 assemble_shader(struct pipe_context *pctx, struct fd3_shader_stateobj *so)
53 {
54 struct fd_context *ctx = fd_context(pctx);
55 uint32_t sz, *bin;
56
57 bin = ir3_shader_assemble(so->ir, &so->info);
58 sz = so->info.sizedwords * 4;
59
60 so->bo = fd_bo_new(ctx->screen->dev, sz,
61 DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
62 DRM_FREEDRENO_GEM_TYPE_KMEM);
63
64 memcpy(fd_bo_map(so->bo), bin, sz);
65
66 free(bin);
67
68 so->instrlen = so->info.sizedwords / 8;
69 so->constlen = so->info.max_const + 1;
70 }
71
72 /* for vertex shader, the inputs are loaded into registers before the shader
73 * is executed, so max_regs from the shader instructions might not properly
74 * reflect the # of registers actually used:
75 */
76 static void
77 fixup_vp_regfootprint(struct fd3_shader_stateobj *so)
78 {
79 unsigned i;
80 for (i = 0; i < so->inputs_count; i++) {
81 so->info.max_reg = MAX2(so->info.max_reg, so->inputs[i].regid >> 2);
82 }
83 }
84
85 static struct fd3_shader_stateobj *
86 create_shader(struct pipe_context *pctx, const struct pipe_shader_state *cso,
87 enum shader_t type)
88 {
89 struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
90 int ret;
91
92 if (!so)
93 return NULL;
94
95 so->type = type;
96
97 if (fd_mesa_debug & FD_DBG_DISASM) {
98 DBG("dump tgsi: type=%d", so->type);
99 tgsi_dump(cso->tokens, 0);
100 }
101
102 if ((type == SHADER_FRAGMENT) && (fd_mesa_debug & FD_DBG_FRAGHALF))
103 so->half_precision = true;
104
105 ret = fd3_compile_shader(so, cso->tokens);
106 if (ret) {
107 debug_error("compile failed!");
108 goto fail;
109 }
110
111 assemble_shader(pctx, so);
112 if (!so->bo) {
113 debug_error("assemble failed!");
114 goto fail;
115 }
116
117 if (type == SHADER_VERTEX)
118 fixup_vp_regfootprint(so);
119
120 if (fd_mesa_debug & FD_DBG_DISASM) {
121 DBG("disassemble: type=%d", so->type);
122 disasm_a3xx(fd_bo_map(so->bo), so->info.sizedwords, 0, so->type);
123 }
124
125 return so;
126
127 fail:
128 delete_shader(so);
129 return NULL;
130 }
131
132 static void *
133 fd3_fp_state_create(struct pipe_context *pctx,
134 const struct pipe_shader_state *cso)
135 {
136 return create_shader(pctx, cso, SHADER_FRAGMENT);
137 }
138
139 static void
140 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
141 {
142 struct fd3_shader_stateobj *so = hwcso;
143 delete_shader(so);
144 }
145
146 static void
147 fd3_fp_state_bind(struct pipe_context *pctx, void *hwcso)
148 {
149 struct fd_context *ctx = fd_context(pctx);
150 ctx->prog.fp = hwcso;
151 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
152 ctx->dirty |= FD_DIRTY_PROG;
153 }
154
155 static void *
156 fd3_vp_state_create(struct pipe_context *pctx,
157 const struct pipe_shader_state *cso)
158 {
159 return create_shader(pctx, cso, SHADER_VERTEX);
160 }
161
162 static void
163 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
164 {
165 struct fd3_shader_stateobj *so = hwcso;
166 delete_shader(so);
167 }
168
169 static void
170 fd3_vp_state_bind(struct pipe_context *pctx, void *hwcso)
171 {
172 struct fd_context *ctx = fd_context(pctx);
173 ctx->prog.vp = hwcso;
174 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
175 ctx->dirty |= FD_DIRTY_PROG;
176 }
177
178 static void
179 emit_shader(struct fd_ringbuffer *ring, const struct fd3_shader_stateobj *so)
180 {
181 const struct ir3_shader_info *si = &so->info;
182 enum adreno_state_block sb;
183 enum adreno_state_src src;
184 uint32_t i, sz, *bin;
185
186 if (so->type == SHADER_VERTEX) {
187 sb = SB_VERT_SHADER;
188 } else {
189 sb = SB_FRAG_SHADER;
190 }
191
192 if (fd_mesa_debug & FD_DBG_DIRECT) {
193 sz = si->sizedwords;
194 src = SS_DIRECT;
195 bin = fd_bo_map(so->bo);
196 } else {
197 sz = 0;
198 src = SS_INDIRECT;
199 bin = NULL;
200 }
201
202 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
203 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
204 CP_LOAD_STATE_0_STATE_SRC(src) |
205 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
206 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
207 if (bin) {
208 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
209 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
210 } else {
211 OUT_RELOC(ring, so->bo, 0,
212 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
213 }
214 for (i = 0; i < sz; i++) {
215 OUT_RING(ring, bin[i]);
216 }
217 }
218
219 static int
220 find_output(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
221 {
222 int j;
223 for (j = 0; j < so->outputs_count; j++)
224 if (so->outputs[j].semantic == semantic)
225 return j;
226 return 0;
227 }
228
229 void
230 fd3_program_emit(struct fd_ringbuffer *ring,
231 struct fd_program_stateobj *prog, bool binning)
232 {
233 const struct fd3_shader_stateobj *vp = prog->vp;
234 const struct fd3_shader_stateobj *fp = prog->fp;
235 const struct ir3_shader_info *vsi = &vp->info;
236 const struct ir3_shader_info *fsi = &fp->info;
237 int i;
238
239 if (binning) {
240 /* use dummy stateobj to simplify binning vs non-binning: */
241 static const struct fd3_shader_stateobj binning_fp = {};
242 fp = &binning_fp;
243 fsi = &fp->info;
244 }
245
246 /* we could probably divide this up into things that need to be
247 * emitted if frag-prog is dirty vs if vert-prog is dirty..
248 */
249
250 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
251 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
252 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
253 * flush some caches? I think we only need to set those
254 * bits if we have updated const or shader..
255 */
256 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
257 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
258 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
259 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
260 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
261 OUT_RING(ring, 0x00000000); /* HLSQ_CONTROL_3_REG */
262 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
263 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
264 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vp->instrlen));
265 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
266 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
267 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fp->instrlen));
268
269 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
270 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
271 COND(binning, A3XX_SP_SP_CTRL_REG_BINNING) |
272 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
273 A3XX_SP_SP_CTRL_REG_L0MODE(0));
274
275 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
276 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
277
278 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
279 OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
280 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
281 A3XX_SP_VS_CTRL_REG0_CACHEINVALID |
282 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
283 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
284 A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
285 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
286 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
287 COND(vp->samplers_count > 0, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
288 A3XX_SP_VS_CTRL_REG0_LENGTH(vp->instrlen));
289 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
290 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
291 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vsi->max_const, 0)));
292 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(vp->pos_regid) |
293 A3XX_SP_VS_PARAM_REG_PSIZEREGID(vp->psize_regid) |
294 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->inputs_count));
295
296 for (i = 0; i < fp->inputs_count; ) {
297 uint32_t reg = 0;
298 int j;
299
300 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i/2), 1);
301
302 j = find_output(vp, fp->inputs[i].semantic);
303 reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[j].regid);
304 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[i].compmask);
305 i++;
306
307 j = find_output(vp, fp->inputs[i].semantic);
308 reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[j].regid);
309 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[i].compmask);
310 i++;
311
312 OUT_RING(ring, reg);
313 }
314
315 for (i = 0; i < fp->inputs_count; ) {
316 uint32_t reg = 0;
317
318 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i/4), 1);
319
320 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[i++].inloc);
321 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[i++].inloc);
322 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[i++].inloc);
323 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[i++].inloc);
324
325 OUT_RING(ring, reg);
326 }
327
328 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
329 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
330 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
331 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
332
333 if (binning) {
334 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
335 OUT_RING(ring, 0x00000000);
336
337 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
338 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
339 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
340 OUT_RING(ring, 0x00000000);
341 } else {
342 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
343 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
344
345 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
346 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
347 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
348 A3XX_SP_FS_CTRL_REG0_CACHEINVALID |
349 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
350 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
351 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
352 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
353 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
354 COND(fp->samplers_count > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
355 A3XX_SP_FS_CTRL_REG0_LENGTH(fp->instrlen));
356 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
357 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
358 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fsi->max_const, 0)) |
359 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
360 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
361 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
362 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
363 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
364 }
365
366 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
367 OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
368 OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
369
370 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
371 OUT_RING(ring, 0x00000000); /* SP_FS_OUTPUT_REG */
372
373 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
374 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(fp->color_regid) |
375 COND(fp->half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
376 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
377 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
378 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
379
380 if (binning) {
381 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
382 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
383 A3XX_VPC_ATTR_LMSIZE(1));
384 OUT_RING(ring, 0x00000000);
385 } else {
386 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
387 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
388 A3XX_VPC_ATTR_THRDASSIGN(1) |
389 A3XX_VPC_ATTR_LMSIZE(1));
390 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
391 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
392
393 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
394 OUT_RING(ring, fp->vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
395 OUT_RING(ring, fp->vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
396 OUT_RING(ring, fp->vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
397 OUT_RING(ring, fp->vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
398
399 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
400 OUT_RING(ring, fp->vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
401 OUT_RING(ring, fp->vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
402 OUT_RING(ring, fp->vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
403 OUT_RING(ring, fp->vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
404 }
405
406 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
407 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
408 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
409
410 emit_shader(ring, vp);
411
412 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
413 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
414
415 if (!binning) {
416 emit_shader(ring, fp);
417
418 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
419 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
420 }
421
422 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
423 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(vp->total_in) |
424 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
425 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(vp->inputs_count) |
426 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(vp->inputs_count));
427 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
428 A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
429 A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
430 }
431
432 /* once the compiler is good enough, we should construct TGSI in the
433 * core freedreno driver, and then let the a2xx/a3xx parts compile
434 * the internal shaders from TGSI the same as regular shaders. This
435 * would be the first step towards handling most of clear (and the
436 * gmem<->mem blits) from the core via normal state changes and shader
437 * state objects.
438 *
439 * (Well, there would still be some special bits, because there are
440 * some registers that don't get set for normal draw, but this should
441 * be relatively small and could be handled via callbacks from core
442 * into a2xx/a3xx..)
443 */
444 static struct fd3_shader_stateobj *
445 create_internal_shader(struct pipe_context *pctx, enum shader_t type,
446 struct ir3_shader *ir)
447 {
448 struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
449
450 if (!so) {
451 ir3_shader_destroy(ir);
452 return NULL;
453 }
454
455 so->type = type;
456 so->ir = ir;
457
458 assemble_shader(pctx, so);
459 assert(so->bo);
460
461 return so;
462 }
463
464 /* Creates shader:
465 * (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x
466 * (rpt5)nop
467 * sam (f32)(xyzw)r0.x, r0.z, s#0, t#0
468 * (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x
469 * end
470 */
471 static struct fd3_shader_stateobj *
472 create_blit_fp(struct pipe_context *pctx)
473 {
474 struct fd3_shader_stateobj *so;
475 struct ir3_shader *ir = ir3_shader_create();
476 struct ir3_instruction *instr;
477
478 /* (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x */
479 instr = ir3_instr_create(ir, 2, OPC_BARY_F);
480 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
481 instr->repeat = 1;
482
483 ir3_reg_create(instr, regid(0,2), IR3_REG_EI); /* (ei)r0.z */
484 ir3_reg_create(instr, 0, IR3_REG_R | /* (r)0 */
485 IR3_REG_IMMED)->iim_val = 0;
486 ir3_reg_create(instr, regid(0,0), 0); /* r0.x */
487
488 /* (rpt5)nop */
489 instr = ir3_instr_create(ir, 0, OPC_NOP);
490 instr->repeat = 5;
491
492 /* sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 */
493 instr = ir3_instr_create(ir, 5, OPC_SAM);
494 instr->cat5.samp = 0;
495 instr->cat5.tex = 0;
496 instr->cat5.type = TYPE_F32;
497
498 ir3_reg_create(instr, regid(0,0), /* (xyzw)r0.x */
499 0)->wrmask = 0xf;
500 ir3_reg_create(instr, regid(0,2), 0); /* r0.z */
501
502 /* (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x */
503 instr = ir3_instr_create(ir, 1, 0); /* mov/cov instructions have no opc */
504 instr->flags = IR3_INSTR_SY;
505 instr->repeat = 3;
506 instr->cat1.src_type = TYPE_F32;
507 instr->cat1.dst_type = TYPE_F16;
508
509 ir3_reg_create(instr, regid(0,0), IR3_REG_HALF); /* hr0.x */
510 ir3_reg_create(instr, regid(0,0), IR3_REG_R); /* (r)r0.x */
511
512 /* end */
513 instr = ir3_instr_create(ir, 0, OPC_END);
514
515 so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
516 if (!so)
517 return NULL;
518
519 so->color_regid = regid(0,0);
520 so->half_precision = true;
521 so->inputs_count = 1;
522 so->inputs[0].semantic = fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
523 so->inputs[0].inloc = 8;
524 so->inputs[0].compmask = 0x3;
525 so->total_in = 2;
526 so->samplers_count = 1;
527
528 so->vpsrepl[0] = 0x99999999;
529 so->vpsrepl[1] = 0x99999999;
530 so->vpsrepl[2] = 0x99999999;
531 so->vpsrepl[3] = 0x99999999;
532
533 return so;
534 }
535
536 /* Creates shader:
537 * (sy)(ss)end
538 */
539 static struct fd3_shader_stateobj *
540 create_blit_vp(struct pipe_context *pctx)
541 {
542 struct fd3_shader_stateobj *so;
543 struct ir3_shader *ir = ir3_shader_create();
544 struct ir3_instruction *instr;
545
546 /* (sy)(ss)end */
547 instr = ir3_instr_create(ir, 0, OPC_END);
548 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
549
550 so = create_internal_shader(pctx, SHADER_VERTEX, ir);
551 if (!so)
552 return NULL;
553
554 so->pos_regid = regid(1,0);
555 so->psize_regid = regid(63,0);
556 so->inputs_count = 2;
557 so->inputs[0].regid = regid(0,0);
558 so->inputs[0].compmask = 0xf;
559 so->inputs[1].regid = regid(1,0);
560 so->inputs[1].compmask = 0xf;
561 so->total_in = 8;
562 so->outputs_count = 1;
563 so->outputs[0].semantic = fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
564 so->outputs[0].regid = regid(0,0);
565
566 fixup_vp_regfootprint(so);
567
568 return so;
569 }
570
571 /* Creates shader:
572 * (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x
573 * end
574 */
575 static struct fd3_shader_stateobj *
576 create_solid_fp(struct pipe_context *pctx)
577 {
578 struct fd3_shader_stateobj *so;
579 struct ir3_shader *ir = ir3_shader_create();
580 struct ir3_instruction *instr;
581
582 /* (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x */
583 instr = ir3_instr_create(ir, 1, 0); /* mov/cov instructions have no opc */
584 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
585 instr->repeat = 3;
586 instr->cat1.src_type = TYPE_F16;
587 instr->cat1.dst_type = TYPE_F16;
588
589 ir3_reg_create(instr, regid(0,0), IR3_REG_HALF); /* hr0.x */
590 ir3_reg_create(instr, regid(0,0), IR3_REG_HALF | /* (r)hc0.x */
591 IR3_REG_CONST | IR3_REG_R);
592
593 /* end */
594 instr = ir3_instr_create(ir, 0, OPC_END);
595
596 so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
597 if (!so)
598 return NULL;
599
600 so->color_regid = regid(0,0);
601 so->half_precision = true;
602 so->inputs_count = 0;
603 so->total_in = 0;
604
605 return so;
606 }
607
608 /* Creates shader:
609 * (sy)(ss)end
610 */
611 static struct fd3_shader_stateobj *
612 create_solid_vp(struct pipe_context *pctx)
613 {
614 struct fd3_shader_stateobj *so;
615 struct ir3_shader *ir = ir3_shader_create();
616 struct ir3_instruction *instr;
617
618 /* (sy)(ss)end */
619 instr = ir3_instr_create(ir, 0, OPC_END);
620 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
621
622
623 so = create_internal_shader(pctx, SHADER_VERTEX, ir);
624 if (!so)
625 return NULL;
626
627 so->pos_regid = regid(0,0);
628 so->psize_regid = regid(63,0);
629 so->inputs_count = 1;
630 so->inputs[0].regid = regid(0,0);
631 so->inputs[0].compmask = 0xf;
632 so->total_in = 4;
633 so->outputs_count = 0;
634
635 fixup_vp_regfootprint(so);
636
637 return so;
638 }
639
640 void
641 fd3_prog_init(struct pipe_context *pctx)
642 {
643 struct fd_context *ctx = fd_context(pctx);
644
645 pctx->create_fs_state = fd3_fp_state_create;
646 pctx->bind_fs_state = fd3_fp_state_bind;
647 pctx->delete_fs_state = fd3_fp_state_delete;
648
649 pctx->create_vs_state = fd3_vp_state_create;
650 pctx->bind_vs_state = fd3_vp_state_bind;
651 pctx->delete_vs_state = fd3_vp_state_delete;
652
653 ctx->solid_prog.fp = create_solid_fp(pctx);
654 ctx->solid_prog.vp = create_solid_vp(pctx);
655 ctx->blit_prog.fp = create_blit_fp(pctx);
656 ctx->blit_prog.vp = create_blit_vp(pctx);
657 }
658
659 void
660 fd3_prog_fini(struct pipe_context *pctx)
661 {
662 struct fd_context *ctx = fd_context(pctx);
663
664 delete_shader(ctx->solid_prog.vp);
665 delete_shader(ctx->solid_prog.fp);
666 delete_shader(ctx->blit_prog.vp);
667 delete_shader(ctx->blit_prog.fp);
668 }