src/gallium/drivers/freedreno/a3xx/fd3_program.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_program.h"
  36
  37 #include "fd3_program.h"
  38 #include "fd3_emit.h"
  39 #include "fd3_texture.h"
  40 #include "fd3_format.h"
  41
  42 static void
  43 delete_shader_stateobj(struct fd3_shader_stateobj *so)
  44 {
  45         ir3_shader_destroy(so->shader);
  46         free(so);
  47 }
  48
  49 static struct fd3_shader_stateobj *
  50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
  51                 enum shader_t type)
  52 {
  53         struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
  54         so->shader = ir3_shader_create(pctx, cso, type);
  55         return so;
  56 }
  57
  58 static void *
  59 fd3_fp_state_create(struct pipe_context *pctx,
  60                 const struct pipe_shader_state *cso)
  61 {
  62         return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
  63 }
  64
  65 static void
  66 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
  67 {
  68         struct fd3_shader_stateobj *so = hwcso;
  69         delete_shader_stateobj(so);
  70 }
  71
  72 static void *
  73 fd3_vp_state_create(struct pipe_context *pctx,
  74                 const struct pipe_shader_state *cso)
  75 {
  76         return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
  77 }
  78
  79 static void
  80 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
  81 {
  82         struct fd3_shader_stateobj *so = hwcso;
  83         delete_shader_stateobj(so);
  84 }
  85
  86 static void
  87 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
  88 {
  89         const struct ir3_info *si = &so->info;
  90         enum adreno_state_block sb;
  91         enum adreno_state_src src;
  92         uint32_t i, sz, *bin;
  93
  94         if (so->type == SHADER_VERTEX) {
  95                 sb = SB_VERT_SHADER;
  96         } else {
  97                 sb = SB_FRAG_SHADER;
  98         }
  99
 100         if (fd_mesa_debug & FD_DBG_DIRECT) {
 101                 sz = si->sizedwords;
 102                 src = SS_DIRECT;
 103                 bin = fd_bo_map(so->bo);
 104         } else {
 105                 sz = 0;
 106                 src = SS_INDIRECT;
 107                 bin = NULL;
 108         }
 109
 110         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
 111         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
 112                         CP_LOAD_STATE_0_STATE_SRC(src) |
 113                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 114                         CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
 115         if (bin) {
 116                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 117                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
 118         } else {
 119                 OUT_RELOC(ring, so->bo, 0,
 120                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
 121         }
 122         for (i = 0; i < sz; i++) {
 123                 OUT_RING(ring, bin[i]);
 124         }
 125 }
 126
 127 void
 128 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 129                                  int nr, struct pipe_surface **bufs)
 130 {
 131         const struct ir3_shader_variant *vp, *fp;
 132         const struct ir3_info *vsi, *fsi;
 133         enum a3xx_instrbuffermode fpbuffer, vpbuffer;
 134         uint32_t fpbuffersz, vpbuffersz, fsoff;
 135         uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
 136         int constmode;
 137         int i, j, k;
 138
 139         debug_assert(nr <= ARRAY_SIZE(color_regid));
 140
 141         vp = fd3_emit_get_vp(emit);
 142
 143         if (emit->key.binning_pass) {
 144                 /* use dummy stateobj to simplify binning vs non-binning: */
 145                 static const struct ir3_shader_variant binning_fp = {};
 146                 fp = &binning_fp;
 147         } else {
 148                 fp = fd3_emit_get_fp(emit);
 149         }
 150
 151         vsi = &vp->info;
 152         fsi = &fp->info;
 153
 154         fpbuffer = BUFFER;
 155         vpbuffer = BUFFER;
 156         fpbuffersz = fp->instrlen;
 157         vpbuffersz = vp->instrlen;
 158
 159         /*
 160          * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
 161          * appears like 256 is the hard limit, but when the combined size
 162          * exceeds 128 then blob will try to keep FS in BUFFER mode and
 163          * switch to CACHE for VS until VS is too large.  The blob seems
 164          * to switch FS out of BUFFER mode at slightly under 128.  But
 165          * a bit fuzzy on the decision tree, so use slightly conservative
 166          * limits.
 167          *
 168          * TODO check if these thresholds for BUFFER vs CACHE mode are the
 169          *      same for all a3xx or whether we need to consider the gpuid
 170          */
 171
 172         if ((fpbuffersz + vpbuffersz) > 128) {
 173                 if (fpbuffersz < 112) {
 174                         /* FP:BUFFER   VP:CACHE  */
 175                         vpbuffer = CACHE;
 176                         vpbuffersz = 256 - fpbuffersz;
 177                 } else if (vpbuffersz < 112) {
 178                         /* FP:CACHE    VP:BUFFER */
 179                         fpbuffer = CACHE;
 180                         fpbuffersz = 256 - vpbuffersz;
 181                 } else {
 182                         /* FP:CACHE    VP:CACHE  */
 183                         vpbuffer = fpbuffer = CACHE;
 184                         vpbuffersz = fpbuffersz = 192;
 185                 }
 186         }
 187
 188         if (fpbuffer == BUFFER) {
 189                 fsoff = 128 - fpbuffersz;
 190         } else {
 191                 fsoff = 256 - fpbuffersz;
 192         }
 193
 194         /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
 195         constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
 196
 197         pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
 198         posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
 199         psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
 200         if (fp->color0_mrt) {
 201                 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
 202                         ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
 203         } else {
 204                 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
 205                 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
 206                 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
 207                 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
 208         }
 209
 210         /* adjust regids for alpha output formats. there is no alpha render
 211          * format, so it's just treated like red
 212          */
 213         for (i = 0; i < nr; i++)
 214                 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
 215                         color_regid[i] += 3;
 216
 217         /* we could probably divide this up into things that need to be
 218          * emitted if frag-prog is dirty vs if vert-prog is dirty..
 219          */
 220
 221         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
 222         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 223                         A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
 224                         /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
 225                          * flush some caches? I think we only need to set those
 226                          * bits if we have updated const or shader..
 227                          */
 228                         A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
 229                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 230         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 231                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
 232                         COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD));
 233         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 234         OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
 235         OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
 236                         A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
 237                         A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
 238         OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
 239                         A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
 240                         A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
 241
 242         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 243         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
 244                         COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
 245                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 246                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 247
 248         OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
 249         OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
 250
 251         OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
 252         OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
 253                         A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
 254                         COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
 255                         A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
 256                         A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
 257                         A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
 258                         A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
 259                         A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
 260                         COND(vp->has_samp, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
 261                         A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
 262         OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
 263                         A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
 264                         A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
 265         OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
 266                         A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
 267                         A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
 268
 269         for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
 270                 uint32_t reg = 0;
 271
 272                 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
 273
 274                 j = ir3_next_varying(fp, j);
 275                 if (j < fp->inputs_count) {
 276                         k = ir3_find_output(vp, fp->inputs[j].slot);
 277                         reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
 278                         reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
 279                 }
 280
 281                 j = ir3_next_varying(fp, j);
 282                 if (j < fp->inputs_count) {
 283                         k = ir3_find_output(vp, fp->inputs[j].slot);
 284                         reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
 285                         reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
 286                 }
 287
 288                 OUT_RING(ring, reg);
 289         }
 290
 291         for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
 292                 uint32_t reg = 0;
 293
 294                 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
 295
 296                 j = ir3_next_varying(fp, j);
 297                 if (j < fp->inputs_count)
 298                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
 299                 j = ir3_next_varying(fp, j);
 300                 if (j < fp->inputs_count)
 301                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
 302                 j = ir3_next_varying(fp, j);
 303                 if (j < fp->inputs_count)
 304                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
 305                 j = ir3_next_varying(fp, j);
 306                 if (j < fp->inputs_count)
 307                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
 308
 309                 OUT_RING(ring, reg);
 310         }
 311
 312         OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
 313         OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
 314                         A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 315         OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
 316
 317         if (emit->key.binning_pass) {
 318                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 319                 OUT_RING(ring, 0x00000000);
 320
 321                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 322                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 323                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
 324                 OUT_RING(ring, 0x00000000);
 325
 326                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
 327                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
 328                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 329         } else {
 330                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 331                 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
 332
 333                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 334                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 335                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
 336                                 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
 337                                 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
 338                                 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
 339                                 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
 340                                 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 341                                 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
 342                                 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
 343                                 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
 344                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
 345                                 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
 346                                 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
 347                                 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
 348
 349                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
 350                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
 351                                         MAX2(128, vp->constlen)) |
 352                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
 353                 OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
 354         }
 355
 356         OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
 357         OUT_RING(ring,
 358                          COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
 359                          A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
 360                          A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
 361
 362         OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
 363         for (i = 0; i < 4; i++) {
 364                 uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
 365                         COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
 366
 367                 if (i < nr) {
 368                         enum pipe_format fmt = pipe_surface_format(bufs[i]);
 369                         mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
 370                                 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
 371                 }
 372                 OUT_RING(ring, mrt_reg);
 373         }
 374
 375         if (emit->key.binning_pass) {
 376                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 377                 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
 378                                 A3XX_VPC_ATTR_LMSIZE(1) |
 379                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 380                 OUT_RING(ring, 0x00000000);
 381         } else {
 382                 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
 383
 384                 memset(vinterp, 0, sizeof(vinterp));
 385                 memset(flatshade, 0, sizeof(flatshade));
 386                 memset(vpsrepl, 0, sizeof(vpsrepl));
 387
 388                 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
 389                 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
 390
 391                         /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
 392                          * instead.. rather than -8 everywhere else..
 393                          */
 394                         uint32_t inloc = fp->inputs[j].inloc - 8;
 395
 396                         /* currently assuming varyings aligned to 4 (not
 397                          * packed):
 398                          */
 399                         debug_assert((inloc % 4) == 0);
 400
 401                         if ((fp->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
 402                                         (fp->inputs[j].rasterflat && emit->rasterflat)) {
 403                                 uint32_t loc = inloc;
 404                                 for (i = 0; i < 4; i++, loc++) {
 405                                         vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
 406                                         flatshade[loc / 32] |= 1 << (loc % 32);
 407                                 }
 408                         }
 409
 410                         gl_varying_slot slot = fp->inputs[j].slot;
 411
 412                         /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
 413                         if (slot >= VARYING_SLOT_VAR0) {
 414                                 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
 415                                 /* Replace the .xy coordinates with S/T from the point sprite. Set
 416                                  * interpolation bits for .zw such that they become .01
 417                                  */
 418                                 if (emit->sprite_coord_enable & texmask) {
 419                                         vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
 420                                                         << ((inloc % 16) * 2);
 421                                         vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
 422                                         vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
 423                                 }
 424                         }
 425                 }
 426
 427                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 428                 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
 429                                 A3XX_VPC_ATTR_THRDASSIGN(1) |
 430                                 A3XX_VPC_ATTR_LMSIZE(1) |
 431                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 432                 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
 433                                 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
 434
 435                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
 436                 OUT_RING(ring, vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
 437                 OUT_RING(ring, vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
 438                 OUT_RING(ring, vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
 439                 OUT_RING(ring, vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */
 440
 441                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
 442                 OUT_RING(ring, vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
 443                 OUT_RING(ring, vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
 444                 OUT_RING(ring, vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
 445                 OUT_RING(ring, vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */
 446
 447                 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
 448                 OUT_RING(ring, flatshade[0]);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
 449                 OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
 450         }
 451
 452         if (vpbuffer == BUFFER)
 453                 emit_shader(ring, vp);
 454
 455         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 456         OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 457
 458         if (!emit->key.binning_pass) {
 459                 if (fpbuffer == BUFFER)
 460                         emit_shader(ring, fp);
 461
 462                 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 463                 OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 464         }
 465 }
 466
 467 void
 468 fd3_prog_init(struct pipe_context *pctx)
 469 {
 470         pctx->create_fs_state = fd3_fp_state_create;
 471         pctx->delete_fs_state = fd3_fp_state_delete;
 472
 473         pctx->create_vs_state = fd3_vp_state_create;
 474         pctx->delete_vs_state = fd3_vp_state_delete;
 475
 476         fd_prog_init(pctx);
 477 }