src/gallium/drivers/freedreno/a3xx/fd3_program.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_program.h"
  36
  37 #include "fd3_program.h"
  38 #include "fd3_emit.h"
  39 #include "fd3_texture.h"
  40 #include "fd3_format.h"
  41
  42 static void
  43 delete_shader_stateobj(struct fd3_shader_stateobj *so)
  44 {
  45         ir3_shader_destroy(so->shader);
  46         free(so);
  47 }
  48
  49 static struct fd3_shader_stateobj *
  50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
  51                 enum shader_t type)
  52 {
  53         struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
  54         struct ir3_compiler *compiler = fd_context(pctx)->screen->compiler;
  55         so->shader = ir3_shader_create(compiler, cso, type);
  56         return so;
  57 }
  58
  59 static void *
  60 fd3_fp_state_create(struct pipe_context *pctx,
  61                 const struct pipe_shader_state *cso)
  62 {
  63         return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
  64 }
  65
  66 static void
  67 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
  68 {
  69         struct fd3_shader_stateobj *so = hwcso;
  70         delete_shader_stateobj(so);
  71 }
  72
  73 static void *
  74 fd3_vp_state_create(struct pipe_context *pctx,
  75                 const struct pipe_shader_state *cso)
  76 {
  77         return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
  78 }
  79
  80 static void
  81 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
  82 {
  83         struct fd3_shader_stateobj *so = hwcso;
  84         delete_shader_stateobj(so);
  85 }
  86
  87 static void
  88 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
  89 {
  90         const struct ir3_info *si = &so->info;
  91         enum adreno_state_block sb;
  92         enum adreno_state_src src;
  93         uint32_t i, sz, *bin;
  94
  95         if (so->type == SHADER_VERTEX) {
  96                 sb = SB_VERT_SHADER;
  97         } else {
  98                 sb = SB_FRAG_SHADER;
  99         }
 100
 101         if (fd_mesa_debug & FD_DBG_DIRECT) {
 102                 sz = si->sizedwords;
 103                 src = SS_DIRECT;
 104                 bin = fd_bo_map(so->bo);
 105         } else {
 106                 sz = 0;
 107                 src = SS_INDIRECT;
 108                 bin = NULL;
 109         }
 110
 111         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
 112         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
 113                         CP_LOAD_STATE_0_STATE_SRC(src) |
 114                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 115                         CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
 116         if (bin) {
 117                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 118                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
 119         } else {
 120                 OUT_RELOC(ring, so->bo, 0,
 121                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
 122         }
 123         for (i = 0; i < sz; i++) {
 124                 OUT_RING(ring, bin[i]);
 125         }
 126 }
 127
 128 void
 129 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 130                                  int nr, struct pipe_surface **bufs)
 131 {
 132         const struct ir3_shader_variant *vp, *fp;
 133         const struct ir3_info *vsi, *fsi;
 134         enum a3xx_instrbuffermode fpbuffer, vpbuffer;
 135         uint32_t fpbuffersz, vpbuffersz, fsoff;
 136         uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
 137         int constmode;
 138         int i, j, k;
 139
 140         debug_assert(nr <= ARRAY_SIZE(color_regid));
 141
 142         vp = fd3_emit_get_vp(emit);
 143         fp = fd3_emit_get_fp(emit);
 144
 145         vsi = &vp->info;
 146         fsi = &fp->info;
 147
 148         fpbuffer = BUFFER;
 149         vpbuffer = BUFFER;
 150         fpbuffersz = fp->instrlen;
 151         vpbuffersz = vp->instrlen;
 152
 153         /*
 154          * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
 155          * appears like 256 is the hard limit, but when the combined size
 156          * exceeds 128 then blob will try to keep FS in BUFFER mode and
 157          * switch to CACHE for VS until VS is too large.  The blob seems
 158          * to switch FS out of BUFFER mode at slightly under 128.  But
 159          * a bit fuzzy on the decision tree, so use slightly conservative
 160          * limits.
 161          *
 162          * TODO check if these thresholds for BUFFER vs CACHE mode are the
 163          *      same for all a3xx or whether we need to consider the gpuid
 164          */
 165
 166         if ((fpbuffersz + vpbuffersz) > 128) {
 167                 if (fpbuffersz < 112) {
 168                         /* FP:BUFFER   VP:CACHE  */
 169                         vpbuffer = CACHE;
 170                         vpbuffersz = 256 - fpbuffersz;
 171                 } else if (vpbuffersz < 112) {
 172                         /* FP:CACHE    VP:BUFFER */
 173                         fpbuffer = CACHE;
 174                         fpbuffersz = 256 - vpbuffersz;
 175                 } else {
 176                         /* FP:CACHE    VP:CACHE  */
 177                         vpbuffer = fpbuffer = CACHE;
 178                         vpbuffersz = fpbuffersz = 192;
 179                 }
 180         }
 181
 182         if (fpbuffer == BUFFER) {
 183                 fsoff = 128 - fpbuffersz;
 184         } else {
 185                 fsoff = 256 - fpbuffersz;
 186         }
 187
 188         /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
 189         constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
 190
 191         pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
 192         posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
 193         psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
 194         if (fp->color0_mrt) {
 195                 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
 196                         ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
 197         } else {
 198                 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
 199                 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
 200                 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
 201                 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
 202         }
 203
 204         /* adjust regids for alpha output formats. there is no alpha render
 205          * format, so it's just treated like red
 206          */
 207         for (i = 0; i < nr; i++)
 208                 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
 209                         color_regid[i] += 3;
 210
 211         /* we could probably divide this up into things that need to be
 212          * emitted if frag-prog is dirty vs if vert-prog is dirty..
 213          */
 214
 215         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
 216         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 217                         A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
 218                         /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
 219                          * flush some caches? I think we only need to set those
 220                          * bits if we have updated const or shader..
 221                          */
 222                         A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
 223                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 224         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 225                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
 226                         COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) |
 227                                         A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(regid(0,2))));
 228         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 229         OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
 230         OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
 231                         A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
 232                         A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
 233         OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
 234                         A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
 235                         A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
 236
 237         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 238         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
 239                         COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
 240                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 241                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 242
 243         OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
 244         OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
 245
 246         OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
 247         OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
 248                         A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
 249                         COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
 250                         A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
 251                         A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
 252                         A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
 253                         A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
 254                         A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
 255         OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
 256                         A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
 257                         A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
 258         OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
 259                         A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
 260                         A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
 261
 262         for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
 263                 uint32_t reg = 0;
 264
 265                 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
 266
 267                 j = ir3_next_varying(fp, j);
 268                 if (j < fp->inputs_count) {
 269                         k = ir3_find_output(vp, fp->inputs[j].slot);
 270                         reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
 271                         reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
 272                 }
 273
 274                 j = ir3_next_varying(fp, j);
 275                 if (j < fp->inputs_count) {
 276                         k = ir3_find_output(vp, fp->inputs[j].slot);
 277                         reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
 278                         reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
 279                 }
 280
 281                 OUT_RING(ring, reg);
 282         }
 283
 284         for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
 285                 uint32_t reg = 0;
 286
 287                 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
 288
 289                 j = ir3_next_varying(fp, j);
 290                 if (j < fp->inputs_count)
 291                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
 292                 j = ir3_next_varying(fp, j);
 293                 if (j < fp->inputs_count)
 294                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
 295                 j = ir3_next_varying(fp, j);
 296                 if (j < fp->inputs_count)
 297                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
 298                 j = ir3_next_varying(fp, j);
 299                 if (j < fp->inputs_count)
 300                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
 301
 302                 OUT_RING(ring, reg);
 303         }
 304
 305         OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
 306         OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
 307                         A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 308         OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
 309
 310         if (emit->key.binning_pass) {
 311                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 312                 OUT_RING(ring, 0x00000000);
 313
 314                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 315                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 316                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
 317                 OUT_RING(ring, 0x00000000);
 318
 319                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
 320                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
 321                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 322         } else {
 323                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 324                 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
 325
 326                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 327                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 328                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
 329                                 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
 330                                 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
 331                                 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
 332                                 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
 333                                 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 334                                 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
 335                                 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
 336                                 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
 337                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
 338                                 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
 339                                 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
 340                                 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
 341
 342                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
 343                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
 344                                         MAX2(128, vp->constlen)) |
 345                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
 346                 OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
 347         }
 348
 349         OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
 350         OUT_RING(ring,
 351                          COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
 352                          A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
 353                          A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
 354
 355         OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
 356         for (i = 0; i < 4; i++) {
 357                 uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
 358                         COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
 359
 360                 if (i < nr) {
 361                         enum pipe_format fmt = pipe_surface_format(bufs[i]);
 362                         mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
 363                                 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
 364                 }
 365                 OUT_RING(ring, mrt_reg);
 366         }
 367
 368         if (emit->key.binning_pass) {
 369                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 370                 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
 371                                 A3XX_VPC_ATTR_LMSIZE(1) |
 372                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 373                 OUT_RING(ring, 0x00000000);
 374         } else {
 375                 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
 376
 377                 memset(vinterp, 0, sizeof(vinterp));
 378                 memset(flatshade, 0, sizeof(flatshade));
 379                 memset(vpsrepl, 0, sizeof(vpsrepl));
 380
 381                 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
 382                 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
 383                         /* NOTE: varyings are packed, so if compmask is 0xb
 384                          * then first, third, and fourth component occupy
 385                          * three consecutive varying slots:
 386                          */
 387                         unsigned compmask = fp->inputs[j].compmask;
 388
 389                         /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
 390                          * instead.. rather than -8 everywhere else..
 391                          */
 392                         uint32_t inloc = fp->inputs[j].inloc - 8;
 393
 394                         if ((fp->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
 395                                         (fp->inputs[j].rasterflat && emit->rasterflat)) {
 396                                 uint32_t loc = inloc;
 397
 398                                 for (i = 0; i < 4; i++) {
 399                                         if (compmask & (1 << i)) {
 400                                                 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
 401                                                 flatshade[loc / 32] |= 1 << (loc % 32);
 402                                                 loc++;
 403                                         }
 404                                 }
 405                         }
 406
 407                         gl_varying_slot slot = fp->inputs[j].slot;
 408
 409                         /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
 410                         if (slot >= VARYING_SLOT_VAR0) {
 411                                 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
 412                                 /* Replace the .xy coordinates with S/T from the point sprite. Set
 413                                  * interpolation bits for .zw such that they become .01
 414                                  */
 415                                 if (emit->sprite_coord_enable & texmask) {
 416                                         /* mask is two 2-bit fields, where:
 417                                          *   '01' -> S
 418                                          *   '10' -> T
 419                                          *   '11' -> 1 - T  (flip mode)
 420                                          */
 421                                         unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
 422                                         uint32_t loc = inloc;
 423                                         if (compmask & 0x1) {
 424                                                 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
 425                                                 loc++;
 426                                         }
 427                                         if (compmask & 0x2) {
 428                                                 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
 429                                                 loc++;
 430                                         }
 431                                         if (compmask & 0x4) {
 432                                                 /* .z <- 0.0f */
 433                                                 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
 434                                                 loc++;
 435                                         }
 436                                         if (compmask & 0x8) {
 437                                                 /* .w <- 1.0f */
 438                                                 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
 439                                                 loc++;
 440                                         }
 441                                 }
 442                         }
 443                 }
 444
 445                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 446                 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
 447                                 A3XX_VPC_ATTR_THRDASSIGN(1) |
 448                                 A3XX_VPC_ATTR_LMSIZE(1) |
 449                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 450                 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
 451                                 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
 452
 453                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
 454                 OUT_RING(ring, vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
 455                 OUT_RING(ring, vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
 456                 OUT_RING(ring, vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
 457                 OUT_RING(ring, vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */
 458
 459                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
 460                 OUT_RING(ring, vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
 461                 OUT_RING(ring, vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
 462                 OUT_RING(ring, vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
 463                 OUT_RING(ring, vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */
 464
 465                 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
 466                 OUT_RING(ring, flatshade[0]);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
 467                 OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
 468         }
 469
 470         if (vpbuffer == BUFFER)
 471                 emit_shader(ring, vp);
 472
 473         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 474         OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 475
 476         if (!emit->key.binning_pass) {
 477                 if (fpbuffer == BUFFER)
 478                         emit_shader(ring, fp);
 479
 480                 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 481                 OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 482         }
 483 }
 484
 485 void
 486 fd3_prog_init(struct pipe_context *pctx)
 487 {
 488         pctx->create_fs_state = fd3_fp_state_create;
 489         pctx->delete_fs_state = fd3_fp_state_delete;
 490
 491         pctx->create_vs_state = fd3_vp_state_create;
 492         pctx->delete_vs_state = fd3_vp_state_delete;
 493
 494         fd_prog_init(pctx);
 495 }