projects / mesa.git / blob
? search:


64c9668129bfb49513e70c5617459075cf31677c
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
36
37 #include "freedreno_lowering.h"
38 #include "freedreno_program.h"
39
40 #include "fd3_program.h"
41 #include "fd3_emit.h"
42 #include "fd3_texture.h"
43 #include "fd3_util.h"
44
45 static void
46 delete_shader_stateobj(struct fd3_shader_stateobj *so)
47 {
48 ir3_shader_destroy(so->shader);
49 free(so);
50 }
51
52 static struct fd3_shader_stateobj *
53 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
54 enum shader_t type)
55 {
56 struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
57 so->shader = ir3_shader_create(pctx, cso->tokens, type);
58 return so;
59 }
60
61 static void *
62 fd3_fp_state_create(struct pipe_context *pctx,
63 const struct pipe_shader_state *cso)
64 {
65 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
66 }
67
68 static void
69 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
70 {
71 struct fd3_shader_stateobj *so = hwcso;
72 delete_shader_stateobj(so);
73 }
74
75 static void *
76 fd3_vp_state_create(struct pipe_context *pctx,
77 const struct pipe_shader_state *cso)
78 {
79 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
80 }
81
82 static void
83 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
84 {
85 struct fd3_shader_stateobj *so = hwcso;
86 delete_shader_stateobj(so);
87 }
88
89 static void
90 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
91 {
92 const struct ir3_info *si = &so->info;
93 enum adreno_state_block sb;
94 enum adreno_state_src src;
95 uint32_t i, sz, *bin;
96
97 if (so->type == SHADER_VERTEX) {
98 sb = SB_VERT_SHADER;
99 } else {
100 sb = SB_FRAG_SHADER;
101 }
102
103 if (fd_mesa_debug & FD_DBG_DIRECT) {
104 sz = si->sizedwords;
105 src = SS_DIRECT;
106 bin = fd_bo_map(so->bo);
107 } else {
108 sz = 0;
109 src = SS_INDIRECT;
110 bin = NULL;
111 }
112
113 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
114 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
115 CP_LOAD_STATE_0_STATE_SRC(src) |
116 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
117 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
118 if (bin) {
119 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
120 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
121 } else {
122 OUT_RELOC(ring, so->bo, 0,
123 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
124 }
125 for (i = 0; i < sz; i++) {
126 OUT_RING(ring, bin[i]);
127 }
128 }
129
130 static int
131 find_output(const struct ir3_shader_variant *so, ir3_semantic semantic)
132 {
133 int j;
134
135 for (j = 0; j < so->outputs_count; j++)
136 if (so->outputs[j].semantic == semantic)
137 return j;
138
139 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
140 * in the vertex shader.. but the fragment shader doesn't know this
141 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
142 * at link time if there is no matching OUT.BCOLOR[n], we must map
143 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
144 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
145 */
146 if (sem2name(semantic) == TGSI_SEMANTIC_BCOLOR) {
147 unsigned idx = sem2idx(semantic);
148 semantic = ir3_semantic_name(TGSI_SEMANTIC_COLOR, idx);
149 } else if (sem2name(semantic) == TGSI_SEMANTIC_COLOR) {
150 unsigned idx = sem2idx(semantic);
151 semantic = ir3_semantic_name(TGSI_SEMANTIC_BCOLOR, idx);
152 }
153
154 for (j = 0; j < so->outputs_count; j++)
155 if (so->outputs[j].semantic == semantic)
156 return j;
157
158 debug_assert(0);
159
160 return 0;
161 }
162
163 static int
164 next_varying(const struct ir3_shader_variant *so, int i)
165 {
166 while (++i < so->inputs_count)
167 if (so->inputs[i].compmask && so->inputs[i].bary)
168 break;
169 return i;
170 }
171
172 static uint32_t
173 find_output_regid(const struct ir3_shader_variant *so, ir3_semantic semantic)
174 {
175 int j;
176 for (j = 0; j < so->outputs_count; j++)
177 if (so->outputs[j].semantic == semantic)
178 return so->outputs[j].regid;
179 return regid(63, 0);
180 }
181
182 void
183 fd3_program_emit(struct fd_ringbuffer *ring,
184 struct fd_program_stateobj *prog,
185 struct ir3_shader_key key,
186 boolean rasterflat)
187 {
188 const struct ir3_shader_variant *vp, *fp;
189 const struct ir3_info *vsi, *fsi;
190 enum a3xx_instrbuffermode fpbuffer, vpbuffer;
191 uint32_t fpbuffersz, vpbuffersz, fsoff;
192 uint32_t pos_regid, posz_regid, psize_regid, color_regid;
193 int i, j, k;
194
195 vp = fd3_shader_variant(prog->vp, key);
196
197 if (key.binning_pass) {
198 /* use dummy stateobj to simplify binning vs non-binning: */
199 static const struct ir3_shader_variant binning_fp = {};
200 fp = &binning_fp;
201 } else {
202 fp = fd3_shader_variant(prog->fp, key);
203 }
204
205 vsi = &vp->info;
206 fsi = &fp->info;
207
208 fpbuffer = BUFFER;
209 vpbuffer = BUFFER;
210 fpbuffersz = fp->instrlen;
211 vpbuffersz = vp->instrlen;
212
213 /*
214 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
215 * appears like 256 is the hard limit, but when the combined size
216 * exceeds 128 then blob will try to keep FS in BUFFER mode and
217 * switch to CACHE for VS until VS is too large. The blob seems
218 * to switch FS out of BUFFER mode at slightly under 128. But
219 * a bit fuzzy on the decision tree, so use slightly conservative
220 * limits.
221 *
222 * TODO check if these thresholds for BUFFER vs CACHE mode are the
223 * same for all a3xx or whether we need to consider the gpuid
224 */
225
226 if ((fpbuffersz + vpbuffersz) > 128) {
227 if (fpbuffersz < 112) {
228 /* FP:BUFFER VP:CACHE */
229 vpbuffer = CACHE;
230 vpbuffersz = 256 - fpbuffersz;
231 } else if (vpbuffersz < 112) {
232 /* FP:CACHE VP:BUFFER */
233 fpbuffer = CACHE;
234 fpbuffersz = 256 - vpbuffersz;
235 } else {
236 /* FP:CACHE VP:CACHE */
237 vpbuffer = fpbuffer = CACHE;
238 vpbuffersz = fpbuffersz = 192;
239 }
240 }
241
242 if (fpbuffer == BUFFER) {
243 fsoff = 128 - fpbuffersz;
244 } else {
245 fsoff = 256 - fpbuffersz;
246 }
247
248 pos_regid = find_output_regid(vp,
249 ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
250 posz_regid = find_output_regid(fp,
251 ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
252 psize_regid = find_output_regid(vp,
253 ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
254 color_regid = find_output_regid(fp,
255 ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
256
257 /* we could probably divide this up into things that need to be
258 * emitted if frag-prog is dirty vs if vert-prog is dirty..
259 */
260
261 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
262 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
263 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
264 * flush some caches? I think we only need to set those
265 * bits if we have updated const or shader..
266 */
267 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
268 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
269 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
270 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
271 COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD));
272 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
273 OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
274 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
275 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
276 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
277 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
278 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
279 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
280
281 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
282 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
283 COND(key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
284 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
285 A3XX_SP_SP_CTRL_REG_L0MODE(0));
286
287 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
288 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
289
290 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
291 OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
292 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
293 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
294 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
295 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
296 A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
297 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
298 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
299 COND(vp->has_samp, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
300 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
301 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
302 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
303 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
304 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
305 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
306 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
307
308 for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
309 uint32_t reg = 0;
310
311 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
312
313 j = next_varying(fp, j);
314 if (j < fp->inputs_count) {
315 k = find_output(vp, fp->inputs[j].semantic);
316 reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
317 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
318 }
319
320 j = next_varying(fp, j);
321 if (j < fp->inputs_count) {
322 k = find_output(vp, fp->inputs[j].semantic);
323 reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
324 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
325 }
326
327 OUT_RING(ring, reg);
328 }
329
330 for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
331 uint32_t reg = 0;
332
333 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
334
335 j = next_varying(fp, j);
336 if (j < fp->inputs_count)
337 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
338 j = next_varying(fp, j);
339 if (j < fp->inputs_count)
340 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
341 j = next_varying(fp, j);
342 if (j < fp->inputs_count)
343 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
344 j = next_varying(fp, j);
345 if (j < fp->inputs_count)
346 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
347
348 OUT_RING(ring, reg);
349 }
350
351 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
352 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
353 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
354 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
355
356 if (key.binning_pass) {
357 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
358 OUT_RING(ring, 0x00000000);
359
360 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
361 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
362 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
363 OUT_RING(ring, 0x00000000);
364
365 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
366 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
367 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
368 } else {
369 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
370 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
371
372 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
373 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
374 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
375 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
376 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
377 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
378 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
379 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
380 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
381 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
382 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
383 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
384 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
385 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
386 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
387
388 /* NOTE: I believe VS.CONSTLEN should be <= FS.CONSTOBJOFFSET*/
389 debug_assert(vp->constlen <= 128);
390
391 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
392 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
393 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
394 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
395 }
396
397 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
398 if (fp->writes_pos) {
399 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
400 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
401 } else {
402 OUT_RING(ring, 0x00000000);
403 }
404
405 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
406 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
407 COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
408 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
409 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
410 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
411
412 if (key.binning_pass) {
413 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
414 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
415 A3XX_VPC_ATTR_LMSIZE(1) |
416 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
417 OUT_RING(ring, 0x00000000);
418 } else {
419 uint32_t vinterp[4] = {0}, flatshade[2] = {0};
420
421 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
422 for (j = -1; (j = next_varying(fp, j)) < (int)fp->inputs_count; ) {
423 uint32_t interp = fp->inputs[j].interpolate;
424 if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
425 ((interp == TGSI_INTERPOLATE_COLOR) && rasterflat)) {
426 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
427 * instead.. rather than -8 everywhere else..
428 */
429 uint32_t loc = fp->inputs[j].inloc - 8;
430
431 /* currently assuming varyings aligned to 4 (not
432 * packed):
433 */
434 debug_assert((loc % 4) == 0);
435
436 for (i = 0; i < 4; i++, loc++) {
437 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
438 flatshade[loc / 32] |= 1 << (loc % 32);
439 }
440 }
441 }
442
443 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
444 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
445 A3XX_VPC_ATTR_THRDASSIGN(1) |
446 A3XX_VPC_ATTR_LMSIZE(1) |
447 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
448 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
449 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
450
451 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
452 OUT_RING(ring, vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
453 OUT_RING(ring, vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
454 OUT_RING(ring, vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
455 OUT_RING(ring, vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
456
457 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
458 OUT_RING(ring, fp->shader->vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
459 OUT_RING(ring, fp->shader->vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
460 OUT_RING(ring, fp->shader->vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
461 OUT_RING(ring, fp->shader->vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
462
463 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
464 OUT_RING(ring, flatshade[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
465 OUT_RING(ring, flatshade[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
466 }
467
468 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
469 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
470 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
471
472 if (vpbuffer == BUFFER)
473 emit_shader(ring, vp);
474
475 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
476 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
477
478 if (!key.binning_pass) {
479 if (fpbuffer == BUFFER)
480 emit_shader(ring, fp);
481
482 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
483 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
484 }
485 }
486
487 /* hack.. until we figure out how to deal w/ vpsrepl properly.. */
488 static void
489 fix_blit_fp(struct pipe_context *pctx)
490 {
491 struct fd_context *ctx = fd_context(pctx);
492 struct fd3_shader_stateobj *so = ctx->blit_prog.fp;
493
494 so->shader->vpsrepl[0] = 0x99999999;
495 so->shader->vpsrepl[1] = 0x99999999;
496 so->shader->vpsrepl[2] = 0x99999999;
497 so->shader->vpsrepl[3] = 0x99999999;
498 }
499
500 void
501 fd3_prog_init(struct pipe_context *pctx)
502 {
503 pctx->create_fs_state = fd3_fp_state_create;
504 pctx->delete_fs_state = fd3_fp_state_delete;
505
506 pctx->create_vs_state = fd3_vp_state_create;
507 pctx->delete_vs_state = fd3_vp_state_delete;
508
509 fd_prog_init(pctx);
510
511 fix_blit_fp(pctx);
512 }